diff --git a/arch/risc-v/include/bl602/irq.h b/arch/risc-v/include/bl602/irq.h index 89915b090d..3f5fb0fd9b 100644 --- a/arch/risc-v/include/bl602/irq.h +++ b/arch/risc-v/include/bl602/irq.h @@ -37,165 +37,141 @@ /* Map RISC-V exception code to NuttX IRQ */ -/* IRQ 0-15 : (exception:interrupt=0) */ - -#define BL602_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */ -#define BL602_IRQ_IAFAULT (1) /* Instruction Address Fault */ -#define BL602_IRQ_IINSTRUCTION (2) /* Illegal Instruction */ -#define BL602_IRQ_BPOINT (3) /* Break Point */ -#define BL602_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */ -#define BL602_IRQ_LAFAULT (5) /* Load Access Fault */ -#define BL602_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */ -#define BL602_IRQ_SAFAULT (7) /* Store/AMO Access Fault */ -#define BL602_IRQ_ECALLU (8) /* Environment Call from U-mode */ - /* 9-10: Reserved */ - -#define BL602_IRQ_ECALLM (11) /* Environment Call from M-mode */ - /* 12-15: Reserved */ - -/* IRQ 16- : (async event:interrupt=1) */ - #define BL602_IRQ_NUM_BASE (16) -#define BL602_IRQ_ASYNC (16) -#define BL602_IRQ_MSOFT (BL602_IRQ_ASYNC + 3) /* Machine Software Int */ -#define BL602_IRQ_MTIMER (BL602_IRQ_ASYNC + 7) /* Machine Timer Int */ -#define BL602_IRQ_MEXT (BL602_IRQ_ASYNC + 11) /* Machine External Int */ - -/* Machine Global External Interrupt */ #define BL602_IRQ_BMX_ERR \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 0) /* BMX Error Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 0) /* BMX Error Interrupt */ #define BL602_IRQ_BMX_TO \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 1) /* BMX Timeout Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 1) /* BMX Timeout Interrupt */ #define BL602_IRQ_L1C_BMX_ERR \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 2) /* L1C BMX Error Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 2) /* L1C BMX Error Interrupt */ #define BL602_IRQ_L1C_BMX_TO \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 3) /* L1C BMX Timeout Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 3) /* L1C BMX Timeout Interrupt */ #define BL602_IRQ_SEC_BMX_ERR \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 4) /* SEC BMX Error Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 4) /* SEC BMX Error Interrupt */ #define BL602_IRQ_RF_TOP_INT0 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 5) /* RF_TOP_INT0 Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 5) /* RF_TOP_INT0 Interrupt */ #define BL602_IRQ_RF_TOP_INT1 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 6) /* RF_TOP_INT1 Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 6) /* RF_TOP_INT1 Interrupt */ #define BL602_IRQ_SDIO \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 7) /* SDIO Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 7) /* SDIO Interrupt */ #define BL602_IRQ_DMA_BMX_ERR \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 8) /* DMA BMX Error Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 8) /* DMA BMX Error Interrupt */ #define BL602_IRQ_SEC_GMAC \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 9) /* SEC_ENG_GMAC_INT Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 9) /* SEC_ENG_GMAC_INT Interrupt */ #define BL602_IRQ_SEC_CDET \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 10) /* SEC_ENG_CDET_INT Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 10) /* SEC_ENG_CDET_INT Interrupt */ #define BL602_IRQ_SEC_PKA \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 11) /* SEC_ENG_PKA_INT Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 11) /* SEC_ENG_PKA_INT Interrupt */ #define BL602_IRQ_SEC_TRNG \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 12) /* SEC_ENG_TRNG_INT Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 12) /* SEC_ENG_TRNG_INT Interrupt */ #define BL602_IRQ_SEC_AES \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 13) /* SEC_ENG_AES_INT Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 13) /* SEC_ENG_AES_INT Interrupt */ #define BL602_IRQ_SEC_SHA \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 14) /* SEC_ENG_SHA_INT Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 14) /* SEC_ENG_SHA_INT Interrupt */ #define BL602_IRQ_DMA_ALL \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 15) /* DMA ALL Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 15) /* DMA ALL Interrupt */ #define BL602_IRQ_RESERVED0 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 16) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 16) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED1 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 17) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 17) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED2 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 18) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 18) /* RESERVED Interrupt */ #define BL602_IRQ_IRTX_IRQn \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 19) /* IR TX Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 19) /* IR TX Interrupt */ #define BL602_IRQ_IRRX_IRQn \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 20) /* IR RX Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 20) /* IR RX Interrupt */ #define BL602_IRQ_RESERVED3 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 21) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 21) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED4 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 22) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 22) /* RESERVED Interrupt */ #define BL602_IRQ_SF_CTRL \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 23) /* SF_CTRL Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 23) /* SF_CTRL Interrupt */ #define BL602_IRQ_RESERVED5 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 24) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 24) /* RESERVED Interrupt */ #define BL602_IRQ_GPADC_DMA \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 25) /* GPADC_DMA Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 25) /* GPADC_DMA Interrupt */ #define BL602_IRQ_EFUSE \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 26) /* Efuse Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 26) /* Efuse Interrupt */ #define BL602_IRQ_SPI \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 27) /* SPI Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 27) /* SPI Interrupt */ #define BL602_IRQ_RESERVED6 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 28) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 28) /* RESERVED Interrupt */ #define BL602_IRQ_UART0 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 29) /* UART Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 29) /* UART Interrupt */ #define BL602_IRQ_UART1 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 30) /* UART1 Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 30) /* UART1 Interrupt */ #define BL602_IRQ_RESERVED7 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 31) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 31) /* RESERVED Interrupt */ #define BL602_IRQ_I2C \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 32) /* I2C Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 32) /* I2C Interrupt */ #define BL602_IRQ_RESERVED8 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 33) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 33) /* RESERVED Interrupt */ #define BL602_IRQ_PWM \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 34) /* PWM Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 34) /* PWM Interrupt */ #define BL602_IRQ_RESERVED9 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 35) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 35) /* RESERVED Interrupt */ #define BL602_IRQ_TIMER_CH0 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 36) /* Timer Channel 0 Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 36) /* Timer Channel 0 Interrupt */ #define BL602_IRQ_TIMER_CH1 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 37) /* Timer Channel 1 Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 37) /* Timer Channel 1 Interrupt */ #define BL602_IRQ_TIMER_WDT \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 38) /* Timer Watch Dog Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 38) /* Timer Watch Dog Interrupt */ #define BL602_IRQ_RESERVED10 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 39) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 39) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED11 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 40) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 40) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED12 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 41) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 41) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED13 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 42) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 42) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED14 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 43) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 43) /* RESERVED Interrupt */ #define BL602_IRQ_GPIO_INT0 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 44) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 44) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED16 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 45) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 45) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED17 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 46) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 46) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED18 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 47) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 47) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED19 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 48) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 48) /* RESERVED Interrupt */ #define BL602_IRQ_RESERVED20 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 49) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 49) /* RESERVED Interrupt */ #define BL602_IRQ_PDS_WAKEUP \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 50) /* PDS Wakeup Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 50) /* PDS Wakeup Interrupt */ #define BL602_IRQ_HBN_OUT0 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 51) /* Hibernate out 0 Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 51) /* Hibernate out 0 Interrupt */ #define BL602_IRQ_HBN_OUT1 \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 52) /* Hibernate out 1 Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 52) /* Hibernate out 1 Interrupt */ #define BL602_IRQ_BOR \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 53) /* BOR Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 53) /* BOR Interrupt */ #define BL602_IRQ_WIFI \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 54) /* WIFI To CPU Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 54) /* WIFI To CPU Interrupt */ #define BL602_IRQ_BZ_PHY \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 55) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 55) /* RESERVED Interrupt */ #define BL602_IRQ_BLE \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 56) /* RESERVED Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 56) /* RESERVED Interrupt */ #define BL602_IRQ_MAC_TXRX_TIMER \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ 57) /* mac_int_tx_rx_timer Interrupt */ #define BL602_IRQ_MAC_TXRX_MISC \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ 58) /* mac_int_tx_rx_misc Interrupt */ #define BL602_IRQ_MAC_RX_TRG \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ 59) /* mac_int_rx_trigger Interrupt */ #define BL602_IRQ_MAC_TX_TRG \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ 60) /* mac_int_tx_trigger Interrupt */ #define BL602_IRQ_MAC_GEN \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 61) /* mac_int_gen Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 61) /* mac_int_gen Interrupt */ #define BL602_IRQ_MAC_PORT_TRG \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \ 62) /* mac_int_port_trigger Interrupt */ #define BL602_IRQ_WIFI_IPC_PUBLIC \ - (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 63) /* wifi IPC public Interrupt */ + (RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 63) /* wifi IPC public Interrupt */ /* Total number of IRQs */ diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c index b2d51fb866..e7defc934e 100644 --- a/arch/risc-v/src/bl602/bl602_irq.c +++ b/arch/risc-v/src/bl602/bl602_irq.c @@ -92,7 +92,7 @@ void up_irqinitialize(void) /* Attach the ecall interrupt handler */ - irq_attach(BL602_IRQ_ECALLM, riscv_swint, NULL); + irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -114,13 +114,13 @@ void up_disable_irq(int irq) { uint32_t oldstat; - if (irq == BL602_IRQ_MSOFT) + if (irq == RISCV_IRQ_MSOFT) { /* Read mstatus & clear machine software interrupt enable in mie */ asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE)); } - else if (irq == BL602_IRQ_MTIMER) + else if (irq == RISCV_IRQ_MTIMER) { putreg8(0, CLIC_TIMER_ENABLE_ADDRESS); @@ -130,8 +130,8 @@ void up_disable_irq(int irq) } else { - ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC); - bl_irq_disable(irq - BL602_IRQ_ASYNC); + ASSERT(irq < 64 + 16 + RISCV_IRQ_ASYNC); + bl_irq_disable(irq - RISCV_IRQ_ASYNC); } } @@ -147,13 +147,13 @@ void up_enable_irq(int irq) { uint32_t oldstat; - if (irq == BL602_IRQ_MSOFT) + if (irq == RISCV_IRQ_MSOFT) { /* Read mstatus & set machine software interrupt enable in mie */ asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE)); } - else if (irq == BL602_IRQ_MTIMER) + else if (irq == RISCV_IRQ_MTIMER) { putreg8(1, CLIC_TIMER_ENABLE_ADDRESS); @@ -165,8 +165,8 @@ void up_enable_irq(int irq) } else { - ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC); - bl_irq_enable(irq - BL602_IRQ_ASYNC); + ASSERT(irq < 64 + 16 + RISCV_IRQ_ASYNC); + bl_irq_enable(irq - RISCV_IRQ_ASYNC); } } diff --git a/arch/risc-v/src/bl602/bl602_irq_dispatch.c b/arch/risc-v/src/bl602/bl602_irq_dispatch.c index 6be94dda2e..4dc2387839 100644 --- a/arch/risc-v/src/bl602/bl602_irq_dispatch.c +++ b/arch/risc-v/src/bl602/bl602_irq_dispatch.c @@ -60,12 +60,12 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) if (vector & 0x80000000u) { - irq += BL602_IRQ_ASYNC; + irq += RISCV_IRQ_ASYNC; } /* NOTE: In case of ecall, we need to adjust mepc in the context */ - if (BL602_IRQ_ECALLM == irq) + if (RISCV_IRQ_ECALLM == irq) { *mepc += 4; } diff --git a/arch/risc-v/src/bl602/bl602_timerisr.c b/arch/risc-v/src/bl602/bl602_timerisr.c index dc6011397d..ad882d5d21 100644 --- a/arch/risc-v/src/bl602/bl602_timerisr.c +++ b/arch/risc-v/src/bl602/bl602_timerisr.c @@ -138,7 +138,7 @@ void up_timer_initialize(void) { /* Attach timer interrupt handler */ - irq_attach(BL602_IRQ_MTIMER, bl602_timerisr, NULL); + irq_attach(RISCV_IRQ_MTIMER, bl602_timerisr, NULL); /* Reload CLINT mtimecmp */ @@ -146,5 +146,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(BL602_IRQ_MTIMER); + up_enable_irq(RISCV_IRQ_MTIMER); }