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SAMV7: Port the SAMA5 timer/counter driver to the SAMV7

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This commit is contained in:
Gregory Nutt 2015-12-02 07:18:25 -06:00
parent 975ea3e677
commit bda05b312e
5 changed files with 2783 additions and 48 deletions
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281
arch/arm/src/samv7/Kconfig
View File

@ -254,6 +254,10 @@ config SAMV7_SSC
bool
default n
config SAMV7_HAVE_TC
bool
default n
config SAMV7_HAVE_TWIHS2
bool
default n
@ -419,64 +423,24 @@ config SAMV7_SSC0
select SAMV7_SSC
config SAMV7_TC0
bool "Timer/Counter 0 (TC0)"
bool "Timer Counter 0 (ch. 0, 1, 2) (TC0)"
default n
select SAMV7_TC
select SAMV7_HAVE_TC
config SAMV7_TC1
bool "Timer/Counter 1 (TC1)"
bool "Timer Counter 1 (ch. 3, 4, 5) (TC1)"
default n
select SAMV7_TC
select SAMV7_HAVE_TC
config SAMV7_TC2
bool "Timer/Counter 2 (TC2)"
bool "Timer Counter 2 (ch. 6, 7, 8) (TC2)"
default n
select SAMV7_TC
select SAMV7_HAVE_TC
config SAMV7_TC3
bool "Timer/Counter 3 (TC3)"
bool "Timer Counter 3 (ch. 9, 10, 11) (TC2)"
default n
select SAMV7_TC
config SAMV7_TC4
bool "Timer/Counter 4 (TC4)"
default n
select SAMV7_TC
config SAMV7_TC5
bool "Timer/Counter 5 (TC5)"
default n
select SAMV7_TC
config SAMV7_TC6
bool "Timer/Counter 6 (TC6)"
default n
select SAMV7_TC
config SAMV7_TC7
bool "Timer/Counter 7 (TC7)"
default n
select SAMV7_TC
config SAMV7_TC8
bool "Timer/Counter 8 (TC8)"
default n
select SAMV7_TC
config SAMV7_TC9
bool "Timer/Counter 9 (TC8)"
default n
select SAMV7_TC
config SAMV7_TC10
bool "Timer/Counter 10 (TC9)"
default n
select SAMV7_TC
config SAMV7_TC11
bool "Timer/Counter 11 (TC8)"
default n
select SAMV7_TC
select SAMV7_HAVE_TC
config SAMV7_TRNG
bool "True Random Number Generator (TRNG)"
@ -1208,6 +1172,227 @@ config SAMV7_SSC_DUMPBUFFERS
endmenu # SSC Configuration
if SAMV7_HAVE_TC
menu "Timer/counter Configuration"
if SAMV7_TC0
config SAMV7_TC0_CLK0
bool "Enable TC0 channel 0 clock input pin"
default n
config SAMV7_TC0_TIOA0
bool "Enable TC0 channel 0 output A"
default n
config SAMV7_TC0_TIOB0
bool "Enable TC0 channel 0 output B"
default n
config SAMV7_TC0_CLK1
bool "Enable TC0 channel 1 clock input pin"
default n
config SAMV7_TC0_TIOA1
bool "Enable TC0 channel 1 output A"
default n
config SAMV7_TC0_TIOB1
bool "Enable TC0 channel 1 output B"
default n
config SAMV7_TC0_CLK2
bool "Enable TC0 channel 2 clock input pin"
default n
config SAMV7_TC0_TIOA2
bool "Enable TC0 channel 2 output A"
default n
config SAMV7_TC0_TIOB2
bool "Enable TC0 channel 2 output B"
default n
endif # SAMV7_TC0
if SAMV7_TC1
config SAMV7_TC1_CLK3
bool "Enable TC1 channel 3 clock input pin"
default n
config SAMV7_TC1_TIOA3
bool "Enable TC1 channel 3 output A"
default n
config SAMV7_TC1_TIOB3
bool "Enable TC1 channel 3 output B"
default n
config SAMV7_TC1_CLK4
bool "Enable TC1 channel 4 clock input pin"
default n
config SAMV7_TC1_TIOA4
bool "Enable TC1 channel 4 output A"
default n
config SAMV7_TC1_TIOB4
bool "Enable TC1 channel 4 output B"
default n
config SAMV7_TC1_CLK5
bool "Enable TC1 channel 5 clock input pin"
default n
config SAMV7_TC1_TIOA5
bool "Enable TC1 channel 5 output A"
default n
config SAMV7_TC1_TIOB5
bool "Enable TC1 channel 5 output B"
default n
endif # SAMV7_TC1
if SAMV7_TC2
config SAMV7_TC2_CLK6
bool "Enable TC2 channel 6 clock input pin"
default n
config SAMV7_TC2_TIOA6
bool "Enable TC2 channel 6 output A"
default n
config SAMV7_TC2_TIOB6
bool "Enable TC2 channel 6 output B"
default n
config SAMV7_TC2_CLK7
bool "Enable TC2 channel 7 clock input pin"
default n
config SAMV7_TC2_TIOA7
bool "Enable TC2 channel 7 output A"
default n
config SAMV7_TC2_TIOB7
bool "Enable TC2 channel 7 output B"
default n
config SAMV7_TC2_CLK8
bool "Enable TC2 channel 8 clock input pin"
default n
config SAMV7_TC2_TIOA8
bool "Enable TC2 channel 8 output A"
default n
config SAMV7_TC2_TIOB8
bool "Enable TC2 channel 8 output B"
default n
endif # SAMV7_TC2
if SAMV7_TC3
config SAMV7_TC3_CLK9
bool "Enable TC3 channel 9 clock input pin"
default n
config SAMV7_TC3_TIOA9
bool "Enable TC3 channel 9 output A"
default n
config SAMV7_TC3_TIOB9
bool "Enable TC3 channel 9 output B"
default n
config SAMV7_TC3_CLK10
bool "Enable TC3 channel 10 clock input pin"
default n
config SAMV7_TC3_TIOA10
bool "Enable TC3 channel 10 output A"
default n
config SAMV7_TC3_TIOB10
bool "Enable TC3 channel 10 output B"
default n
config SAMV7_TC3_CLK11
bool "Enable TC3 channel 11 clock input pin"
default n
config SAMV7_TC3_TIOA11
bool "Enable TC3 channel 11 output A"
default n
config SAMV7_TC3_TIOB11
bool "Enable TC3 channel 11 output B"
default n
endif # SAMV7_TC3
config SAMV7_ONESHOT
bool "TC one-shot wrapper"
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
Enable a wrapper around the low level timer/counter functions to
support one-shot timer.
config SAMV7_FREERUN
bool "TC free-running wrapper"
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
Enable a wrapper around the low level timer/counter functions to
support a free-running timer.
if SCHED_TICKLESS
config SAMV7_TICKLESS_ONESHOT
int "Tickless one-shot timer channel"
default 0
range 0 8
---help---
If the Tickless OS feature is enabled, the one clock must be
assigned to provided the one-shot timer needed by the OS.
config SAMV7_TICKLESS_FREERUN
int "Tickless free-running timer channel"
default 1
range 0 8
---help---
If the Tickless OS feature is enabled, the one clock must be
assigned to provided the free-running timer needed by the OS.
endif
config SAMV7_TC_DEBUG
bool "TC debug"
depends on DEBUG
default n
---help---
Output high level Timer/Counter device debug information.
Requires also DEBUG. If this option AND DEBUG_VERBOSE are
enabled, then the system will be overwhelmed the timer debug
output. If DEBUG_VERBOSE is disabled, then debug output will
only indicate if/when timer-related errors occur. This
latter mode is completely usable.
config SAMV7_TC_REGDEBUG
bool "TC register level debug"
depends on DEBUG
default n
---help---
Output detailed register-level Timer/Counter device debug
information. Very invasive! Requires also DEBUG.
endmenu # Timer/counter Configuration
endif # SAMV7_HAVE_TC
menu "HSMCI device driver options"
depends on SAMV7_HSMCI

13
arch/arm/src/samv7/Make.defs
View File

@ -160,6 +160,19 @@ ifeq ($(CONFIG_SAMV7_SSC),y)
CHIP_CSRCS += sam_ssc.c
endif
ifeq ($(CONFIG_SAMV7_HAVE_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMV7_ONESHOT),y)
CHIP_CSRCS += sam_oneshot.c
endif
ifeq ($(CONFIG_SAMV7_FREERUN),y)
CHIP_CSRCS += sam_freerun.c
endif
ifeq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_tickless.c
endif
endif
ifeq ($(CONFIG_SAMV7_HSMCI),y)
CHIP_CSRCS += sam_hsmci.c sam_hsmci_clkdiv.c
endif

636
arch/arm/src/samv7/chip/sam_tc.h Normal file
View File

@ -0,0 +1,636 @@
/************************************************************************************
* arch/arm/src/samv7/chip/sam_tc.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H
#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define SAM_TC_NCHANNELS 3 /* Number of channels per TC peripheral */
/* TC Register Offsets **************************************************************/
#define SAM_TC_CHAN_OFFSET(n) ((n) << 6) /* Channel n offset */
#define SAM_TC_CCR_OFFSET 0x0000 /* Channel Control Register */
#define SAM_TC_CMR_OFFSET 0x0004 /* Channel Mode Register */
#define SAM_TC_SMMR_OFFSET 0x0008 /* Stepper Motor Mode Register */
#define SAM_TC_RAB_OFFSET 0x000c /* Register AB */
#define SAM_TC_CV_OFFSET 0x0010 /* Counter Value */
#define SAM_TC_RA_OFFSET 0x0014 /* Register A */
#define SAM_TC_RB_OFFSET 0x0018 /* Register B */
#define SAM_TC_RC_OFFSET 0x001c /* Register C */
#define SAM_TC_SR_OFFSET 0x0020 /* Status Register */
#define SAM_TC_IER_OFFSET 0x0024 /* Interrupt Enable Register */
#define SAM_TC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */
#define SAM_TC_IMR_OFFSET 0x002c /* Interrupt Mask Register */
#define SAM_TC_EMR_OFFSET 0x0030 /* Extended Mode Register */
#define SAM_TCn_CCR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CCR_OFFSET)
#define SAM_TCn_CMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CMR_OFFSET)
#define SAM_TCn_SMMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_SMMR_OFFSET)
#define SAM_TCn_RAB_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RAB_OFFSET)
#define SAM_TCn_CV_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CV_OFFSET)
#define SAM_TCn_RA_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RA_OFFSET)
#define SAM_TCn_RB_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RB_OFFSET)
#define SAM_TCn_RC_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RC_OFFSET)
#define SAM_TCn_SR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_SR_OFFSET)
#define SAM_TCn_IER_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IER_OFFSET)
#define SAM_TCn_IDR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IDR_OFFSET)
#define SAM_TCn_IMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IMR_OFFSET)
#define SAM_TCn_EMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_EMR_OFFSET)
#define SAM_TC0_CCR_OFFSET SAM_TCn_CCR_OFFSET(0)
#define SAM_TC0_CMR_OFFSET SAM_TCn_CMR_OFFSET(0)
#define SAM_TC0_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(0)
#define SAM_TC0_RAB_OFFSET SAM_TCn_RAB_OFFSET(0)
#define SAM_TC0_CV_OFFSET SAM_TCn_CV_OFFSET(0)
#define SAM_TC0_RA_OFFSET SAM_TCn_RA_OFFSET(0)
#define SAM_TC0_RB_OFFSET SAM_TCn_RB_OFFSET(0)
#define SAM_TC0_RC_OFFSET SAM_TCn_RC_OFFSET(0)
#define SAM_TC0_SR_OFFSET SAM_TCn_SR_OFFSET(0)
#define SAM_TC0_IER_OFFSET SAM_TCn_IER_OFFSET(0)
#define SAM_TC0_IDR_OFFSET SAM_TCn_IDR_OFFSET(0)
#define SAM_TC0_IMR_OFFSET SAM_TCn_IMR_OFFSET(0)
#define SAM_TC0_EMR_OFFSET SAM_TCn_EMR_OFFSET(0)
#define SAM_TC1_CCR_OFFSET SAM_TCn_CCR_OFFSET(1)
#define SAM_TC1_CMR_OFFSET SAM_TCn_CMR_OFFSET(1)
#define SAM_TC1_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(1)
#define SAM_TC1_RAB_OFFSET SAM_TCn_RAB_OFFSET(1)
#define SAM_TC1_CV_OFFSET SAM_TCn_CV_OFFSET(1)
#define SAM_TC1_RA_OFFSET SAM_TCn_RA_OFFSET(1)
#define SAM_TC1_RB_OFFSET SAM_TCn_RB_OFFSET(1)
#define SAM_TC1_RC_OFFSET SAM_TCn_RC_OFFSET(1)
#define SAM_TC1_SR_OFFSET SAM_TCn_SR_OFFSET(1)
#define SAM_TC1_IER_OFFSET SAM_TCn_IER_OFFSET(1)
#define SAM_TC1_IDR_OFFSET SAM_TCn_IDR_OFFSET(1)
#define SAM_TC1_IMR_OFFSET SAM_TCn_IMR_OFFSET(1)
#define SAM_TC1_EMR_OFFSET SAM_TCn_EMR_OFFSET(1)
#define SAM_TC2_CCR_OFFSET SAM_TCn_CCR_OFFSET(2)
#define SAM_TC2_CMR_OFFSET SAM_TCn_CMR_OFFSET(2)
#define SAM_TC2_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(2)
#define SAM_TC2_RAB_OFFSET SAM_TCn_RAB_OFFSET(2)
#define SAM_TC2_CV_OFFSET SAM_TCn_CV_OFFSET(2)
#define SAM_TC2_RA_OFFSET SAM_TCn_RA_OFFSET(2)
#define SAM_TC2_RB_OFFSET SAM_TCn_RB_OFFSET(2)
#define SAM_TC2_RC_OFFSET SAM_TCn_RC_OFFSET(2)
#define SAM_TC2_SR_OFFSET SAM_TCn_SR_OFFSET(2)
#define SAM_TC2_IER_OFFSET SAM_TCn_IER_OFFSET(2)
#define SAM_TC2_IDR_OFFSET SAM_TCn_IDR_OFFSET(2)
#define SAM_TC2_IMR_OFFSET SAM_TCn_IMR_OFFSET(2)
#define SAM_TC2_EMR_OFFSET SAM_TCn_EMR_OFFSET(2)
#define SAM_TC_BCR_OFFSET 0x00c0 /* Block Control Register */
#define SAM_TC_BMR_OFFSET 0x00c4 /* Block Mode Register */
#define SAM_TC_QIER_OFFSET 0x00c8 /* QDEC Interrupt Enable Register */
#define SAM_TC_QIDR_OFFSET 0x00cc /* QDEC Interrupt Disable Register */
#define SAM_TC_QIMR_OFFSET 0x00d0 /* QDEC Interrupt Mask Register */
#define SAM_TC_QISR_OFFSET 0x00d4 /* QDEC Interrupt Status Register */
#define SAM_TC_FMR_OFFSET 0x00d8 /* Fault Mode Register */
#define SAM_TC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
/* TC Register Addresses ************************************************************/
#define SAM_TC012_CHAN_BASE(n) (SAM_TC012_BASE+SAM_TC_CHAN_OFFSET(n))
#define SAM_TC012_CCR(n) (SAM_TC012_BASE+SAM_TCn_CCR_OFFSET(n))
#define SAM_TC012_CMR(n) (SAM_TC012_BASE+SAM_TCn_CMR_OFFSET(n))
#define SAM_TC012_SMMR(n) (SAM_TC012_BASE+SAM_TCn_SMMR_OFFSET(n))
#define SAM_TC012_RAB(n) (SAM_TC012_BASE+SAM_TCn_RAB_OFFSET(n))
#define SAM_TC012_CV(n) (SAM_TC012_BASE+SAM_TCn_CV_OFFSET(n))
#define SAM_TC012_RA(n) (SAM_TC012_BASE+SAM_TCn_RA_OFFSET(n))
#define SAM_TC012_RB(n) (SAM_TC012_BASE+SAM_TCn_RB(n))
#define SAM_TC012_RC(n) (SAM_TC012_BASE+SAM_TCn_RC_OFFSET(n))
#define SAM_TC012_SR(n) (SAM_TC012_BASE+SAM_TCn_SR_OFFSET(n))
#define SAM_TC012_IER(n) (SAM_TC012_BASE+SAM_TCn_IER_OFFSET(n))
#define SAM_TC012_IDR(n) (SAM_TC012_BASE+SAM_TCn_IDR_OFFSET(n))
#define SAM_TC012_IMR(n) (SAM_TC012_BASE+SAM_TCn_IMR_OFFSET(n))
#define SAM_TC012_EMR(n) (SAM_TC012_BASE+SAM_TCn_EMR_OFFSET(n))
#define SAM_TC0_CCR SAM_TC012_CCR(0)
#define SAM_TC0_CMR SAM_TC012_CMR(0)
#define SAM_TC0_SMMR SAM_TC012_SMMR(0)
#define SAM_TC0_RAB SAM_TC012_RAB(0)
#define SAM_TC0_CV SAM_TC012_CV(0)
#define SAM_TC0_RA SAM_TC012_RA(0)
#define SAM_TC0_RB SAM_TC012_RB(0)
#define SAM_TC0_RC SAM_TC012_RC(0)
#define SAM_TC0_SR SAM_TC012_SR(0)
#define SAM_TC0_IER SAM_TC012_IER(0)
#define SAM_TC0_IDR SAM_TC012_IDR(0)
#define SAM_TC0_IMR SAM_TC012_IMR(0)
#define SAM_TC0_EMR SAM_TC012_EMR(0)
#define SAM_TC1_CCR SAM_TC012_CCR(1)
#define SAM_TC1_CMR SAM_TC012_CMR(1)
#define SAM_TC1_SMMR SAM_TC012_SMMR(1)
#define SAM_TC1_RAB SAM_TC012_RAB(1)
#define SAM_TC1_CV SAM_TC012_CV(1)
#define SAM_TC1_RA SAM_TC012_RA(1)
#define SAM_TC1_RB SAM_TC012_RB(1)
#define SAM_TC1_RC SAM_TC012_RC(1)
#define SAM_TC1_SR SAM_TC012_SR(1)
#define SAM_TC1_IER SAM_TC012_IER(1)
#define SAM_TC1_IDR SAM_TC012_IDR(1)
#define SAM_TC1_IMR SAM_TC012_IMR(1)
#define SAM_TC1_EMR SAM_TC012_EMR(1)
#define SAM_TC2_CCR SAM_TC012_CCR(2)
#define SAM_TC2_CMR SAM_TC012_CMR(2)
#define SAM_TC2_SMMR SAM_TC012_SMMR(2)
#define SAM_TC2_RAB SAM_TC012_RAB(2)
#define SAM_TC2_CV SAM_TC012_CV(2)
#define SAM_TC2_RA SAM_TC012_RA(2)
#define SAM_TC2_RB SAM_TC012_RB(2)
#define SAM_TC2_RC SAM_TC012_RC(2)
#define SAM_TC2_SR SAM_TC012_SR(2)
#define SAM_TC2_IER SAM_TC012_IER(2)
#define SAM_TC2_IDR SAM_TC012_IDR(2)
#define SAM_TC2_IMR SAM_TC012_IMR(2)
#define SAM_TC2_EMR SAM_TC012_EMR(2)
#define SAM_TC012_BCR (SAM_TC012_BASE+SAM_TC_BCR_OFFSET)
#define SAM_TC012_BMR (SAM_TC012_BASE+SAM_TC_BMR_OFFSET)
#define SAM_TC012_QIER (SAM_TC012_BASE+SAM_TC_QIER_OFFSET)
#define SAM_TC012_QIDR (SAM_TC012_BASE+SAM_TC_QIDR_OFFSET)
#define SAM_TC012_QIMR (SAM_TC012_BASE+SAM_TC_QIMR_OFFSET)
#define SAM_TC012_QISR (SAM_TC012_BASE+SAM_TC_QISR_OFFSET)
#define SAM_TC012_FMR (SAM_TC012_BASE+SAM_TC_FMR_OFFSET)
#define SAM_TC012_WPMR (SAM_TC012_BASE+SAM_TC_WPMR_OFFSET)
#define SAM_TC345_CHAN_BASE(n) (SAM_TC345_BASE+SAM_TC_CHAN_OFFSET((n)-3))
#define SAM_TC345_CCR(n) (SAM_TC345_BASE+SAM_TCn_CCR_OFFSET((n)-3))
#define SAM_TC345_CMR(n) (SAM_TC345_BASE+SAM_TCn_CMR_OFFSET((n)-3))
#define SAM_TC345_SMMR(n) (SAM_TC345_BASE+SAM_TCn_SMMR_OFFSET((n)-3))
#define SAM_TC345_RAB(n) (SAM_TC345_BASE+SAM_TCn_RAB_OFFSET((n)-3))
#define SAM_TC345_CV(n) (SAM_TC345_BASE+SAM_TCn_CV_OFFSET((n)-3))
#define SAM_TC345_RA(n) (SAM_TC345_BASE+SAM_TCn_RA_OFFSET((n)-3))
#define SAM_TC345_RB(n) (SAM_TC345_BASE+SAM_TCn_RB_OFFSET((n)-3))
#define SAM_TC345_RC(n) (SAM_TC345_BASE+SAM_TCn_RC_OFFSET((n)-3))
#define SAM_TC345_SR(n) (SAM_TC345_BASE+SAM_TCn_SR_OFFSET((n)-3))
#define SAM_TC345_IER(n) (SAM_TC345_BASE+SAM_TCn_IER_OFFSET((n)-3))
#define SAM_TC345_IDR(n) (SAM_TC345_BASE+SAM_TCn_IDR_OFFSET((n)-3))
#define SAM_TC345_IMR(n) (SAM_TC345_BASE+SAM_TCn_IMR_OFFSET((n)-3))
#define SAM_TC345_EMR(n) (SAM_TC345_BASE+SAM_TCn_EMR_OFFSET((n)-3))
#define SAM_TC3_CCR SAM_TC345_CCR(3)
#define SAM_TC3_CMR SAM_TC345_CMR(3)
#define SAM_TC3_SMMR SAM_TC345_SMMR(3)
#define SAM_TC3_RAB SAM_TC345_RAB(3)
#define SAM_TC3_CV SAM_TC345_CV(3)
#define SAM_TC3_RA SAM_TC345_RA(3)
#define SAM_TC3_RB SAM_TC345_RB(3)
#define SAM_TC3_RC SAM_TC345_RC(3)
#define SAM_TC3_SR SAM_TC345_SR(3)
#define SAM_TC3_IER SAM_TC345_IER(3)
#define SAM_TC3_IDR SAM_TC345_IDR(3)
#define SAM_TC3_IMR SAM_TC345_IMR(3)
#define SAM_TC3_EMR SAM_TC345_EMR(3)
#define SAM_TC4_CCR SAM_TC345_CCR(4)
#define SAM_TC4_CMR SAM_TC345_CMR(4)
#define SAM_TC4_SMMR SAM_TC345_SMMR(4)
#define SAM_TC4_RAB SAM_TC345_RAB(4)
#define SAM_TC4_CV SAM_TC345_CV(4)
#define SAM_TC4_RA SAM_TC345_RA(4)
#define SAM_TC4_RB SAM_TC345_RB(4)
#define SAM_TC4_RC SAM_TC345_RC(4)
#define SAM_TC4_SR SAM_TC345_SR(4)
#define SAM_TC4_IER SAM_TC345_IER(4)
#define SAM_TC4_IDR SAM_TC345_IDR(4)
#define SAM_TC4_IMR SAM_TC345_IMR(4)
#define SAM_TC4_EMR SAM_TC345_EMR(4)
#define SAM_TC5_CCR SAM_TC345_CCR(5)
#define SAM_TC5_CMR SAM_TC345_CMR(5)
#define SAM_TC5_SMMR SAM_TC345_SMMR(5)
#define SAM_TC5_RAB SAM_TC345_RAB(5)
#define SAM_TC5_CV SAM_TC345_CV(5)
#define SAM_TC5_RA SAM_TC345_RA(5)
#define SAM_TC5_RB SAM_TC345_RB(5)
#define SAM_TC5_RC SAM_TC345_RC(5)
#define SAM_TC5_SR SAM_TC345_SR(5)
#define SAM_TC5_IER SAM_TC345_IER(5)
#define SAM_TC5_IDR SAM_TC345_IDR(5)
#define SAM_TC5_IMR SAM_TC345_IMR(5)
#define SAM_TC5_EMR SAM_345_EMR(5)
#define SAM_TC345_BCR (SAM_TC345_BASE+SAM_TC_BCR_OFFSET)
#define SAM_TC345_BMR (SAM_TC345_BASE+SAM_TC_BMR_OFFSET)
#define SAM_TC345_QIER (SAM_TC345_BASE+SAM_TC_QIER_OFFSET)
#define SAM_TC345_QIDR (SAM_TC345_BASE+SAM_TC_QIDR_OFFSET)
#define SAM_TC345_QIMR (SAM_TC345_BASE+SAM_TC_QIMR_OFFSET)
#define SAM_TC345_QISR (SAM_TC345_BASE+SAM_TC_QISR_OFFSET)
#define SAM_TC345_FMR (SAM_TC345_BASE+SAM_TC_FMR_OFFSET)
#define SAM_TC345_WPMR (SAM_TC345_BASE+SAM_TC_WPMR_OFFSET)
#define SAM_TC678_CHAN_BASE(n) (SAM_TC678_BASE+SAM_TC_CHAN_OFFSET((n)-6))
#define SAM_TC678_CCRn(n) (SAM_TC678_BASE+SAM_TCn_CCR_OFFSET((n)-6))
#define SAM_TC678_CMR(n) (SAM_TC678_BASE+SAM_TCn_CMR_OFFSET((n)-6))
#define SAM_TC678_SMMR(n) (SAM_TC678_BASE+SAM_TCn_SMMR_OFFSET((n)-6))
#define SAM_TC678_RAB(n) (SAM_TC678_BASE+SAM_TCn_RAB_OFFSET((n)-6))
#define SAM_TC678_CV(n) (SAM_TC678_BASE+SAM_TCn_CV_OFFSET((n)-6))
#define SAM_TC678_RA(n) (SAM_TC678_BASE+SAM_TCn_RA_OFFSET((n)-6))
#define SAM_TC678_RB(n) (SAM_TC678_BASE+SAM_TCn_RB((n)-6))
#define SAM_TC678_RC(n) (SAM_TC678_BASE+SAM_TCn_RC_OFFSET((n)-6))
#define SAM_TC678_SR(n) (SAM_TC678_BASE+SAM_TCn_SR_OFFSET((n)-6))
#define SAM_TC678_IER(n) (SAM_TC678_BASE+SAM_TCn_IER_OFFSET((n)-6))
#define SAM_TC678_IDR(n) (SAM_TC678_BASE+SAM_TCn_IDR_OFFSET((n)-6))
#define SAM_TC678_IMR(n) (SAM_TC678_BASE+SAM_TCn_IMR_OFFSET((n)-6))
#define SAM_TC678_EMR(n) (SAM_TC678_BASE+SAM_TCn_EMR_OFFSET((n)-6))
#define SAM_TC6_CCR SAM_TC678_CCR(6)
#define SAM_TC6_CMR SAM_TC678_CMR(6)
#define SAM_TC6_SMMR SAM_TC678_SMMR(6)
#define SAM_TC6_RAB SAM_TC678_RAB(6)
#define SAM_TC6_CV SAM_TC678_CV(6)
#define SAM_TC6_RA SAM_TC678_RA(6)
#define SAM_TC6_RB SAM_TC678_RB(6)
#define SAM_TC6_RC SAM_TC678_RC(6)
#define SAM_TC6_SR SAM_TC678_SR(6)
#define SAM_TC6_IER SAM_TC678_IER(6)
#define SAM_TC6_IDR SAM_TC678_IDR(6)
#define SAM_TC6_IMR SAM_TC678_IMR(6)
#define SAM_TC6_EMR SAM_TC678_EMR(6)
#define SAM_TC7_CCR SAM_TC678_CCR(7)
#define SAM_TC7_CMR SAM_TC678_CMR(7)
#define SAM_TC7_SMMR SAM_TC678_SMMR(7)
#define SAM_TC7_RAB SAM_TC678_RAB(7)
#define SAM_TC7_CV SAM_TC678_CV(7)
#define SAM_TC7_RA SAM_TC678_RA(7)
#define SAM_TC7_RB SAM_TC678_RB(7)
#define SAM_TC7_RC SAM_TC678_RC(7)
#define SAM_TC7_SR SAM_TC678_SR(7)
#define SAM_TC7_IER SAM_TC678_IER(7)
#define SAM_TC7_IDR SAM_TC678_IDR(7)
#define SAM_TC7_IMR SAM_TC678_IMR(7)
#define SAM_TC7_EMR SAM_TC678_EMR(7)
#define SAM_TC8_CCR SAM_TC678_CCR(8)
#define SAM_TC8_CMR SAM_TC678_CMR(8)
#define SAM_TC8_SMMR SAM_TC678_SMMR(8)
#define SAM_TC8_RAB SAM_TC678_RAB(8)
#define SAM_TC8_CV SAM_TC678_CV(8)
#define SAM_TC8_RA SAM_TC678_RA(8)
#define SAM_TC8_RB SAM_TC678_RB(8)
#define SAM_TC8_RC SAM_TC678_RC(8)
#define SAM_TC8_SR SAM_TC678_SR(8)
#define SAM_TC8_IER SAM_TC678_IER(8)
#define SAM_TC8_IDR SAM_TC678_IDR(8)
#define SAM_TC8_IMR SAM_TC678_IMR(8)
#define SAM_TC8_EMR SAM_TC678_EMR(8)
#define SAM_TC678_BCR (SAM_TC678_BASE+SAM_TC_BCR_OFFSET)
#define SAM_TC678_BMR (SAM_TC678_BASE+SAM_TC_BMR_OFFSET)
#define SAM_TC678_QIER (SAM_TC678_BASE+SAM_TC_QIER_OFFSET)
#define SAM_TC678_QIDR (SAM_TC678_BASE+SAM_TC_QIDR_OFFSET)
#define SAM_TC678_QIMR (SAM_TC678_BASE+SAM_TC_QIMR_OFFSET)
#define SAM_TC678_QISR (SAM_TC678_BASE+SAM_TC_QISR_OFFSET)
#define SAM_TC678_FMR (SAM_TC678_BASE+SAM_TC_FMR_OFFSET)
#define SAM_TC678_WPMR (SAM_TC678_BASE+SAM_TC_WPMR_OFFSET)
#define SAM_TC901_CHAN_BASE(n) (SAM_TC901_BASE+SAM_TC_CHAN_OFFSET((n)-9))
#define SAM_TC901_CCRn(n) (SAM_TC901_BASE+SAM_TCn_CCR_OFFSET((n)-9))
#define SAM_TC901_CMR(n) (SAM_TC901_BASE+SAM_TCn_CMR_OFFSET((n)-9))
#define SAM_TC901_SMMR(n) (SAM_TC901_BASE+SAM_TCn_SMMR_OFFSET((n)-9))
#define SAM_TC901_RAB(n) (SAM_TC901_BASE+SAM_TCn_RAB_OFFSET((n)-9))
#define SAM_TC901_CV(n) (SAM_TC901_BASE+SAM_TCn_CV_OFFSET((n)-9))
#define SAM_TC901_RA(n) (SAM_TC901_BASE+SAM_TCn_RA_OFFSET((n)-9))
#define SAM_TC901_RB(n) (SAM_TC901_BASE+SAM_TCn_RB((n)-9))
#define SAM_TC901_RC(n) (SAM_TC901_BASE+SAM_TCn_RC_OFFSET((n)-9))
#define SAM_TC901_SR(n) (SAM_TC901_BASE+SAM_TCn_SR_OFFSET((n)-9))
#define SAM_TC901_IER(n) (SAM_TC901_BASE+SAM_TCn_IER_OFFSET((n)-9))
#define SAM_TC901_IDR(n) (SAM_TC901_BASE+SAM_TCn_IDR_OFFSET((n)-9))
#define SAM_TC901_IMR(n) (SAM_TC901_BASE+SAM_TCn_IMR_OFFSET((n)-9))
#define SAM_TC901_EMR(n) (SAM_TC901_BASE+SAM_TCn_EMR_OFFSET((n)-9))
#define SAM_TC9_CCR SAM_TC901_CCR(9)
#define SAM_TC9_CMR SAM_TC901_CMR(9)
#define SAM_TC9_SMMR SAM_TC901_SMMR(9)
#define SAM_TC9_RAB SAM_TC901_RAB(9)
#define SAM_TC9_CV SAM_TC901_CV(9)
#define SAM_TC9_RA SAM_TC901_RA(9)
#define SAM_TC9_RB SAM_TC901_RB(9)
#define SAM_TC9_RC SAM_TC901_RC(9)
#define SAM_TC9_SR SAM_TC901_SR(9)
#define SAM_TC9_IER SAM_TC901_IER(9)
#define SAM_TC9_IDR SAM_TC901_IDR(9)
#define SAM_TC9_IMR SAM_TC901_IMR(9)
#define SAM_TC9_EMR SAM_TC901_EMR(9)
#define SAM_TC10_CCR SAM_TC901_CCR(10)
#define SAM_TC10_CMR SAM_TC901_CMR(10)
#define SAM_TC10_SMMR SAM_TC901_SMMR(10)
#define SAM_TC10_RAB SAM_TC901_RAB(10)
#define SAM_TC10_CV SAM_TC901_CV(10)
#define SAM_TC10_RA SAM_TC901_RA(10)
#define SAM_TC10_RB SAM_TC901_RB(10)
#define SAM_TC10_RC SAM_TC901_RC(10)
#define SAM_TC10_SR SAM_TC901_SR(10)
#define SAM_TC10_IER SAM_TC901_IER(10)
#define SAM_TC10_IDR SAM_TC901_IDR(10)
#define SAM_TC10_IMR SAM_TC901_IMR(10)
#define SAM_TC10_EMR SAM_TC901_EMR(10)
#define SAM_TC11_CCR SAM_TC901_CCR(11)
#define SAM_TC11_CMR SAM_TC901_CMR(11)
#define SAM_TC11_SMMR SAM_TC901_SMMR(11)
#define SAM_TC11_RAB SAM_TC901_RAB(11)
#define SAM_TC11_CV SAM_TC901_CV(11)
#define SAM_TC11_RA SAM_TC901_RA(11)
#define SAM_TC11_RB SAM_TC901_RB(11)
#define SAM_TC11_RC SAM_TC901_RC(11)
#define SAM_TC11_SR SAM_TC901_SR(11)
#define SAM_TC11_IER SAM_TC901_IER(11)
#define SAM_TC11_IDR SAM_TC901_IDR(11)
#define SAM_TC11_IMR SAM_TC901_IMR(11)
#define SAM_TC11_EMR SAM_TC901_EMR(11)
#define SAM_TC901_BCR (SAM_TC901_BASE+SAM_TC_BCR_OFFSET)
#define SAM_TC901_BMR (SAM_TC901_BASE+SAM_TC_BMR_OFFSET)
#define SAM_TC901_QIER (SAM_TC901_BASE+SAM_TC_QIER_OFFSET)
#define SAM_TC901_QIDR (SAM_TC901_BASE+SAM_TC_QIDR_OFFSET)
#define SAM_TC901_QIMR (SAM_TC901_BASE+SAM_TC_QIMR_OFFSET)
#define SAM_TC901_QISR (SAM_TC901_BASE+SAM_TC_QISR_OFFSET)
#define SAM_TC901_FMR (SAM_TC901_BASE+SAM_TC_FMR_OFFSET)
#define SAM_TC901_WPMR (SAM_TC901_BASE+SAM_TC_WPMR_OFFSET)
/* TC Register Bit Definitions ******************************************************/
/* Channel Control Register */
#define TC_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */
#define TC_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */
#define TC_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */
/* Channel Mode Register -- All modes */
#define TC_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection */
#define TC_CMR_TCCLKS_MASK (7 << TC_CMR_TCCLKS_SHIFT)
# define TC_CMR_TCCLKS(n) ((uint32_t)(n) << TC_CMR_TCCLKS_SHIFT)
# define TC_CMR_TCCLKS_TCLK1 (0 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK1 Clock selected */
# define TC_CMR_TCCLKS_TCLK2 (1 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK2 Clock selected */
# define TC_CMR_TCCLKS_TCLK3 (2 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK3 Clock selected */
# define TC_CMR_TCCLKS_TCLK4 (3 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK4 Clock selected */
# define TC_CMR_TCCLKS_TCLK5 (4 << TC_CMR_TCCLKS_SHIFT) /* TIMER_CLOCK5 Clock selected */
# define TC_CMR_TCCLKS_XC0 (5 << TC_CMR_TCCLKS_SHIFT) /* XC0 Clock selected */
# define TC_CMR_TCCLKS_XC1 (6 << TC_CMR_TCCLKS_SHIFT) /* XC1 Clock selected */
# define TC_CMR_TCCLKS_XC2 (7 << TC_CMR_TCCLKS_SHIFT) /* XC2 Clock selected */
#define TC_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert */
#define TC_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection */
#define TC_CMR_BURST_MASK (3 << TC_CMR_BURST_SHIFT)
# define TC_CMR_BURST_NONE (0 << TC_CMR_BURST_SHIFT) /* Clock not gated by external signal */
# define TC_CMR_BURST_XC0 (1 << TC_CMR_BURST_SHIFT) /* XXC0 ANDed with clock */
# define TC_CMR_BURST_XC1 (2 << TC_CMR_BURST_SHIFT) /* XC1 ANDed with clock */
# define TC_CMR_BURST_XC2 (3 << TC_CMR_BURST_SHIFT) /* XC2 ANDed with clock */
/* Channel Mode Register -- Capture mode */
#define TC_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RB Loading */
#define TC_CMR_LDBDIS (1 << 7) /* Bit 7: Counter Clock Disable with RB Loading */
#define TC_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection */
#define TC_CMR_ETRGEDG_MASK (3 << TC_CMR_ETRGEDG_SHIFT)
# define TC_CMR_ETRGEDG_NONE (0 << TC_CMR_ETRGEDG_SHIFT) /* Clock not gated by external signal */
# define TC_CMR_ETRGEDG_RISING (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */
# define TC_CMR_ETRGEDG_FALLING (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */
# define TC_CMR_ETRGEDG_BOTH (3 << TC_CMR_ETRGEDG_SHIFT) /* EDGE Each edge */
#define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */
#define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */
#define TC_CMR_CAPTURE (0) /* Bit 15: 0=Capture Mode */
#define TC_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Edge Selection */
#define TC_CMR_LDRA_MASK (3 << TC_CMR_LDRA_SHIFT)
# define TC_CMR_LDRA_NONE (0 << TC_CMR_LDRA_SHIFT) /* None */
# define TC_CMR_LDRA_RISING (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */
# define TC_CMR_LDRA_FALLING (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */
# define TC_CMR_LDRA_BOTH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */
#define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Edge Selection */
#define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT)
# define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */
# define TC_CMR_LDRB_RISING (1 << TC_CMR_LDRB_SHIFT) /* Rising edge of TIOA */
# define TC_CMR_LDRB_FALLING (2 << TC_CMR_LDRB_SHIFT) /* Falling edge of TIOA */
# define TC_CMR_LDRB_BOTH (3 << TC_CMR_LDRB_SHIFT) /* Each edge of TIOA */
#define TC_CMR_SBSMPLR_SHIFT (20) /* Bits 20-22: Loading Edge Subsampling Ratio */
#define TC_CMR_SBSMPLR_MASK (7 << TC_CMR_SBSMPLR_SHIFT)
# define TC_CMR_SBSMPLR_ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */
# define TC_CMR_SBSMPLR_HALF (1 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 2 selected edges */
# define TC_CMR_SBSMPLR_4TH (2 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 4 selected edges */
# define TC_CMR_SBSMPLR_8TH (3 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 8 selected edges */
# define TC_CMR_SBSMPLR_16TH (4 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 16 selected edges */
/* Channel Mode Register -- Waveform mode */
#define TC_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare */
#define TC_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare */
#define TC_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection */
#define TC_CMR_EEVTEDG_MASK (3 << TC_CMR_EEVTEDG_SHIFT)
# define TC_CMR_EEVTEDG_NONE (0 << TC_CMR_EEVTEDG_SHIFT) /* None */
# define TC_CMR_EEVTEDG_RISING (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */
# define TC_CMR_EEVTEDG_FALLING (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */
# define TC_CMR_EEVTEDG_BOTH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */
#define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection */
#define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT)
# define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB(1) input */
# define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 output */
# define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 output */
# define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 output */
#define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable */
#define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection */
#define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT)
# define TC_CMR_WAVSEL_UP (0 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/o trigger on RC Compare */
# define TC_CMR_WAVSEL_UPDOWN (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o trigger on RC Compare */
# define TC_CMR_WAVSEL_UPRC (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/ trigger on RC Compare */
# define TC_CMR_WAVSEL_UPDOWNRC (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN w/ with trigger on RC Compare */
#define TC_CMR_WAVE (1 << 15) /* Bit 15: 1=Waveform Mode */
#define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA */
#define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT)
# define TC_CMR_ACPA_NONE (0 << TC_CMR_ACPA_SHIFT) /* None */
# define TC_CMR_ACPA_SET (1 << TC_CMR_ACPA_SHIFT) /* Set */
# define TC_CMR_ACPA_CLEAR (2 << TC_CMR_ACPA_SHIFT) /* Clear */
# define TC_CMR_ACPA_TOGGLE (3 << TC_CMR_ACPA_SHIFT) /* Toggle */
#define TC_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA */
#define TC_CMR_ACPC_MASK (3 << TC_CMR_ACPC_SHIFT)
# define TC_CMR_ACPC_NONE (0 << TC_CMR_ACPC_SHIFT) /* None */
# define TC_CMR_ACPC_SET (1 << TC_CMR_ACPC_SHIFT) /* Set */
# define TC_CMR_ACPC_CLEAR (2 << TC_CMR_ACPC_SHIFT) /* Clear */
# define TC_CMR_ACPC_TOGGLE (3 << TC_CMR_ACPC_SHIFT) /* Toggle */
#define TC_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA */
#define TC_CMR_AEEVT_MASK (3 << TC_CMR_AEEVT_SHIFT)
# define TC_CMR_AEEVT_NONE (0 << TC_CMR_AEEVT_SHIFT) /* None */
# define TC_CMR_AEEVT_SET (1 << TC_CMR_AEEVT_SHIFT) /* Set */
# define TC_CMR_AEEVT_CLEAR (2 << TC_CMR_AEEVT_SHIFT) /* Clear */
# define TC_CMR_AEEVT_TOGGLE (3 << TC_CMR_AEEVT_SHIFT) /* Toggle */
#define TC_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA */
#define TC_CMR_ASWTRG_MASK (3 << TC_CMR_ASWTRG_SHIFT)
# define TC_CMR_ASWTRG_NONE (0 << TC_CMR_ASWTRG_SHIFT) /* None */
# define TC_CMR_ASWTRG_SET (1 << TC_CMR_ASWTRG_SHIFT) /* Set */
# define TC_CMR_ASWTRG_CLEAR (2 << TC_CMR_ASWTRG_SHIFT) /* Clear */
# define TC_CMR_ASWTRG_TOGGLE (3 << TC_CMR_ASWTRG_SHIFT) /* Toggle */
#define TC_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB */
#define TC_CMR_BCPB_MASK (3 << TC_CMR_BCPB_SHIFT)
# define TC_CMR_BCPB_NONE (0 << TC_CMR_BCPB_SHIFT) /* None */
# define TC_CMR_BCPB_SET (1 << TC_CMR_BCPB_SHIFT) /* Set */
# define TC_CMR_BCPB_CLEAR (2 << TC_CMR_BCPB_SHIFT) /* Clear */
# define TC_CMR_BCPB_TOGGLE (3 << TC_CMR_BCPB_SHIFT) /* Toggle */
#define TC_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB */
#define TC_CMR_BCPC_MASK (3 << TC_CMR_BCPC_SHIFT)
# define TC_CMR_BCPC_NONE (0 << TC_CMR_BCPC_SHIFT) /* None */
# define TC_CMR_BCPC_SET (1 << TC_CMR_BCPC_SHIFT) /* Set */
# define TC_CMR_BCPC_CLEAR (2 << TC_CMR_BCPC_SHIFT) /* Clear */
# define TC_CMR_BCPC_TOGGLE (3 << TC_CMR_BCPC_SHIFT) /* Toggle */
#define TC_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB */
#define TC_CMR_BEEVT_MASK (3 << TC_CMR_BEEVT_SHIFT)
# define TC_CMR_BEEVT_NONE (0 << TC_CMR_BEEVT_SHIFT) /* None */
# define TC_CMR_BEEVT_SET (1 << TC_CMR_BEEVT_SHIFT) /* Set */
# define TC_CMR_BEEVT_CLEAR (2 << TC_CMR_BEEVT_SHIFT) /* Clear */
# define TC_CMR_BEEVT_TOGGLE (3 << TC_CMR_BEEVT_SHIFT) /* Toggle */
#define TC_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB */
#define TC_CMR_BSWTRG_MASK (3 << TC_CMR_BSWTRG_SHIFT)
# define TC_CMR_BSWTRG_NONE (0 << TC_CMR_BSWTRG_SHIFT) /* None */
# define TC_CMR_BSWTRG_SET (1 << TC_CMR_BSWTRG_SHIFT) /* Set */
# define TC_CMR_BSWTRG_CLEAR (2 << TC_CMR_BSWTRG_SHIFT) /* Clear */
# define TC_CMR_BSWTRG_TOGGLE (3 << TC_CMR_BSWTRG_SHIFT) /* Toggle */
/* Stepper Motor Mode Register */
#define TC_SMMR_GCEN (1 << 0) /* Bit 0: Gray Count Enable */
#define TC_SMMR_DOWN (1 << 1) /* Bit 1: DOWN Count */
/* Register AB (32-bit capture value) */
/* Counter Value (32-bit counter value) */
/* Register A (32-bit value) */
/* Register B (32-bit value) */
/* Register C (32-bit value) */
/* Status Register, Interrupt Enable Register, Interrupt Disable Register, and
* Interrupt Mask Register
*/
#define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow Status */
#define TC_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun Status */
#define TC_INT_CPAS (1 << 2) /* Bit 2: RA Compare Status */
#define TC_INT_CPBS (1 << 3) /* Bit 3: RB Compare Status */
#define TC_INT_CPCS (1 << 4) /* Bit 4: RC Compare Status */
#define TC_INT_LDRAS (1 << 5) /* Bit 5: RA Loading Status */
#define TC_INT_LDRBS (1 << 6) /* Bit 6: RB Loading Status */
#define TC_INT_ETRGS (1 << 7) /* Bit 7: External Trigger Status */
#define TC_INT_ALL (0xff)
#define TC_SR_CLKSTA (1 << 16) /* Bit 16: Clock Enabling Status */
#define TC_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror */
#define TC_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror */
/* Extended Mode Register */
#define TC_EMR_TRIGSRCA_SHIFT (0) /* Bits 0-1: Trigger source for input A */
#define TC_EMR_TRIGSRCA_MASK (3 << TC_EMR_TRIGSRCA_SHIFT)
# define TC_EMR_TRIGSRCA_TIOA (0 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by TIOAx */
# define TC_EMR_TRIGSRCA_PWM (1 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by PWMx */
#define TC_EMR_TRIGSRCB_SHIFT (4) /* Bits 4-5: Trigger source for input B */
#define TC_EMR_TRIGSRCB_MASK (3 << TC_EMR_TRIGSRCB_SHIFT)
# define TC_EMR_TRIGSRCB_TIOB (0 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven by TIOBx */
# define TC_EMR_TRIGSRCB_PWM (1 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven PWMx */
#define TC_EMR_NODIVCLK (1 << 8) /* Bit 8: No divided clock */
/* Block Control Register */
#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command */
/* Block Mode Register */
#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */
#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT)
# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) /* TCLK0 Signal to XC0 */
# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) /* TIOA1 Signal to XC0 */
# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) /* TIOA2 Signal to XC0 */
#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */
#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_SHIFT)
# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) /* TCLK1 Signal to XC1 */
# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) /* TIOA0 Signal to XC1 */
# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) /* TIOA2 Signal to XC1 */
#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */
#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) /* TCLK2 Signal to XC2 */
# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) /* TIOA0 Signal to XC2 */
# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) /* TIOA1 Signal to XC2 */
#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder ENabled */
#define TC_BMR_POSEN (1 << 9) /* Bit 9: POSition ENabled */
#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: SPEED ENabled */
#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding TRANSparent */
#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: EDGe on PHA count mode */
#define TC_BMR_INVA (1 << 13) /* Bit 13: INVerted phA */
#define TC_BMR_INVB (1 << 14) /* Bit 14: INVerted phB */
#define TC_BMR_INVIDX (1 << 15) /* Bit 15: INVerted InDeX */
#define TC_BMR_SWAP (1 << 16) /* Bit 16: SWAP PHA and PHB */
#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: InDeX pin is PHB pin */
#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: MAXimum FILTer */
#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT)
# define TC_BMR_MAXFILT(n) ((uint32_t)(n) << TC_BMR_MAXFILT_SHIFT)
/* QDEC Interrupt Enable Register, QDEC Interrupt Disable Register, QDEC Interrupt Mask Register, and QDEC Interrupt Status Register.
*/
#define TC_QINT_IDX (1 << 0) /* Bit 0: Index */
#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction change */
#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature ERRor */
#define TC_QISR_DIRR (1 << 8) /* Bit 8: Direction */
/* Fault Mode Register */
#define TC_FMR_ENCF0 (1 << 0) /* Bit 0: ENable Compare Fault Channel 0 */
#define TC_FMR_ENCF1 (1 << 1) /* Bit 1: ENable Compare Fault Channel 1 */
/* Write Protect Mode Register */
#define TC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define TC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define TC_WPMR_WPKEY_MASK (0xffffff << TC_WPMR_WPKEY_SHIFT)
# define TC_WPMR_WPKEY (0x54494d << TC_WPMR_WPKEY_SHIFT) /* "TIM" in ASCII */
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H */

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/****************************************************************************
* arch/arm/src/samv7/sam_tc.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_TC_H
#define __ARCH_ARM_SRC_SAMV7_SAM_TC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include "chip.h"
#include "chip/sam_tc.h"
#if defined(CONFIG_SAMV7_TC0) || defined(CONFIG_SAMV7_TC1) || \
defined(CONFIG_SAMV7_TC2) || defined(CONFIG_SAMV7_TC3)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The timer/counter and channel arguments to sam_tc_allocate() */
#define TC_CHAN0 0 /* TC0 */
#define TC_CHAN1 1
#define TC_CHAN2 2
#define TC_CHAN3 3 /* TC1 */
#define TC_CHAN4 4
#define TC_CHAN5 5
#define TC_CHAN6 6 /* TC2 */
#define TC_CHAN7 7
#define TC_CHAN8 8
/* Register identifier used with sam_tc_setregister */
#define TC_REGA 0
#define TC_REGB 1
#define TC_REGC 2
/* Timer debug is enabled if any timer client is enabled */
#ifndef CONFIG_DEBUG
# undef CONFIG_DEBUG_ANALOG
# undef CONFIG_SAMV7_TC_REGDEBUG
#endif
#if !defined(CONFIG_SAMV7_TC_DEBUG) && defined(CONFIG_SAMV7_ADC) && defined(CONFIG_DEBUG_ANALOG)
# define CONFIG_SAMV7_TC_DEBUG 1
#endif
/* Timer/counter debug output */
#ifdef CONFIG_SAMV7_TC_DEBUG
# define tcdbg dbg
# define tcvdbg vdbg
# define tclldbg lldbg
# define tcllvdbg llvdbg
#else
# define tcdbg(x...)
# define tcvdbg(x...)
# define tclldbg(x...)
# define tcllvdbg(x...)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/* An opaque handle used to represent a timer channel */
typedef void *TC_HANDLE;
/* Timer interrupt callback. When a timer interrupt expires, the client will
* receive:
*
* tch - The handle that represents the timer state
* arg - An opaque argument provided when the interrupt was registered
* sr - The value of the timer interrupt status register at the time
* that the interrupt occurred.
*/
typedef void (*tc_handler_t)(TC_HANDLE tch, void *arg, uint32_t sr);
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_tc_allocate
*
* Description:
* Configures a Timer Counter to operate in the given mode. The timer is
* stopped after configuration and must be restarted with sam_tc_start().
* All the interrupts of the timer are also disabled.
*
* Input Parameters:
* channel TC channel number (see TC_CHANx definitions)
* mode Operating mode (TC_CMR value).
*
* Returned Value:
* On success, a non-NULL handle value is returned. This handle may be
* used with subsequent timer/counter interfaces to manage the timer. A
* NULL handle value is returned on a failure.
*
****************************************************************************/
TC_HANDLE sam_tc_allocate(int channel, int mode);
/****************************************************************************
* Name: sam_tc_free
*
* Description:
* Release the handle previously allocated by sam_tc_allocate().
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
* None
*
****************************************************************************/
void sam_tc_free(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_start
*
* Description:
* Reset and Start the TC Channel. Enables the timer clock and performs a
* software reset to start the counting.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
*
****************************************************************************/
void sam_tc_start(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_stop
*
* Description:
* Stop TC Channel. Disables the timer clock, stopping the counting.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
*
****************************************************************************/
void sam_tc_stop(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_attach/sam_tc_detach
*
* Description:
* Attach or detach an interrupt handler to the timer interrupt. The
* interrupt is detached if the handler argument is NULL.
*
* Input Parameters:
* handle The handle that represents the timer state
* handler The interrupt handler that will be invoked when the interrupt
* condition occurs
* arg An opaque argument that will be provided when the interrupt
* handler callback is executed. Ignored if handler is NULL.
* mask The value of the timer interrupt mask register that defines
* which interrupts should be disabled. Ignored if handler is
* NULL.
*
* Returned Value:
* The address of the previous handler, if any.
*
****************************************************************************/
tc_handler_t sam_tc_attach(TC_HANDLE handle, tc_handler_t handler,
void *arg, uint32_t mask);
#define sam_tc_detach(h) sam_tc_attach(h, NULL, NULL, 0)
/****************************************************************************
* Name: sam_tc_getpending
*
* Description:
* Return the current contents of the interrutp status register, clearing
* all pending interrupts.
*
* Input Parameters:
* handle The handle that represents the timer state
*
* Returned Value:
* The value of the channel interrupt status register.
*
****************************************************************************/
uint32_t sam_tc_getpending(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_setregister
*
* Description:
* Set TC_REGA, TC_REGB, or TC_REGC register.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
* regid One of {TC_REGA, TC_REGB, or TC_REGC}
* regval Then value to set in the register
*
* Returned Value:
* None
*
****************************************************************************/
void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval);
/****************************************************************************
* Name: sam_tc_getregister
*
* Description:
* Get the current value of the TC_REGA, TC_REGB, or TC_REGC register.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
* regid One of {TC_REGA, TC_REGB, or TC_REGC}
*
* Returned Value:
* The value of the specified register.
*
****************************************************************************/
uint32_t sam_tc_getregister(TC_HANDLE handle, int regid);
/****************************************************************************
* Name: sam_tc_getcounter
*
* Description:
* Return the current value of the timer counter register
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
* The current value of the timer counter register for this channel.
*
****************************************************************************/
uint32_t sam_tc_getcounter(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_infreq
*
* Description:
* Return the timer input frequency, that is, the MCK frequency divided
* down so that the timer/counter is driven within its maximum frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* The timer input frequency.
*
****************************************************************************/
uint32_t sam_tc_infreq(void);
/****************************************************************************
* Name: sam_tc_divfreq
*
* Description:
* Return the divided timer input frequency that is currently driving the
* the timer counter.
*
* Input Parameters:
* handle Channel handle previously allocated by sam_tc_allocate()
*
* Returned Value:
* The timer counter frequency.
*
****************************************************************************/
uint32_t sam_tc_divfreq(TC_HANDLE handle);
/****************************************************************************
* Name: sam_tc_divisor
*
* Description:
* Finds the best MCK divisor given the timer frequency and MCK. The
* result is guaranteed to satisfy the following equation:
*
* (Ftcin / (div * 65536)) <= freq <= (Ftcin / div)
*
* where:
* freq - the desired frequency
* Ftcin - The timer/counter input frequency
* div - With DIV being the highest possible value.
*
* Input Parameters:
* frequency Desired timer frequency.
* div Divisor value.
* tcclks TCCLKS field value for divisor.
*
* Returned Value:
* Zero (OK) if a proper divisor has been found, otherwise a negated errno
* value indicating the nature of the failure.
*
****************************************************************************/
int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_SAMV7_TC0 || CONFIG_SAMV7_TC1 || CONFIG_SAMV7_TC2 || CONFIG_SAMV7_TC3 */
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_TC_H */