From be594b8932fc9da7f2781c7fa4b59e4982352e05 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Mar 2016 15:44:54 -0600 Subject: [PATCH] i.MX6 Add more IOMUX logic --- arch/arm/src/imx6/chip/imx_iomuxc.h | 43 +++++++++--- arch/arm/src/imx6/imx_gpio.c | 4 +- arch/arm/src/imx6/imx_gpio.h | 103 +++++++--------------------- arch/arm/src/imx6/imx_iomuxc.c | 69 ++++++++++++++++++- arch/arm/src/imx6/imx_iomuxc.h | 82 ++++++++++++++++++++++ 5 files changed, 207 insertions(+), 94 deletions(-) diff --git a/arch/arm/src/imx6/chip/imx_iomuxc.h b/arch/arm/src/imx6/chip/imx_iomuxc.h index 17f392db9f..709ea9369c 100644 --- a/arch/arm/src/imx6/chip/imx_iomuxc.h +++ b/arch/arm/src/imx6/chip/imx_iomuxc.h @@ -1756,27 +1756,48 @@ /* Pad Control Registers */ +#define DRIVE_HIZ (0) /* HI-Z */ +#define DRIVE_260OHM (1) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +#define DRIVE_130OHM (2) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +#define DRIVE_90OHM (3) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +#define DRIVE_60OHM (4) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +#define DRIVE_50OHM (5) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +#define DRIVE_40OHM (6) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +#define DRIVE_33OHM (7) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ + +#define SPEED_LOW (0) /* Low frequency (50 MHz) */ +#define SPEED_MEDIUM (1) /* Medium frequency (100, 150 MHz) */ +#define SPEED_MAX (3) /* Maximum frequency (100, 150, 200 MHz) */ + +#define PULL_DOWN_100K (0) /* 100K Ohm Pull Down */ +#define PULL_UP_47K (1) /* 47K Ohm Pull Up */ +#define PULL_UP_100K (2) /* 100K Ohm Pull Up */ +#define PULL_UP_22K (3) /* 22K Ohm Pull Up */ + #define PADCTL_SRE (1 << 0) /* Bit 0: Slew Rate Field */ -#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */ +#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */ #define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT) -# define PADCTL_DS_HIZ (0 << PADCTL_DS_SHIFT) /* HI-Z */ -# define PADCTL_DS_260OHM (1 << PADCTL_DS_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ -# define PADCTL_DS_130OHM (2 << PADCTL_DS_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ -# define PADCTL_DS_90OHM (3 << PADCTL_DS_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ -# define PADCTL_DS_60OHM (4 << PADCTL_DS_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ -# define PADCTL_DS_50OHM (5 << PADCTL_DS_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ -# define PADCTL_DS_40OHM (6 << PADCTL_DS_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ -# define PADCTL_DS_33OHM (7 << PADCTL_DS_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ -#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */ +# define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */ +# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */ +# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ +#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */ #define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT) +# define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */ # define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */ # define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ # define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ #define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */ #define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */ #define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */ -#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */ +#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */ #define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT) +# define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */ # define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */ # define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */ # define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */ diff --git a/arch/arm/src/imx6/imx_gpio.c b/arch/arm/src/imx6/imx_gpio.c index fe4c7b513b..09f7efca3f 100644 --- a/arch/arm/src/imx6/imx_gpio.c +++ b/arch/arm/src/imx6/imx_gpio.c @@ -413,6 +413,7 @@ static inline bool imx_gpio_getinput(int port, int pin) static inline int imx_gpio_configinput(gpio_pinset_t pinset, int port, int pin) { FAR const uint8_t *table; + iomux_pinset_t ioset; uintptr_t regaddr; unsigned int index; @@ -447,7 +448,8 @@ static inline int imx_gpio_configinput(gpio_pinset_t pinset, int port, int pin) } regaddr = IMX_PADCTL_ADDRESS(index); - return imx_iomux_configure(regaddr, pinset); + ioset = (iomux_pinset_t)((pinset & GPIO_IOMUX_MASK) >> GPIO_IOMUX_SHIFT); + return imx_iomux_configure(regaddr, ioset); } /**************************************************************************** diff --git a/arch/arm/src/imx6/imx_gpio.h b/arch/arm/src/imx6/imx_gpio.h index 2eb2dc11b6..0caf7378ab 100644 --- a/arch/arm/src/imx6/imx_gpio.h +++ b/arch/arm/src/imx6/imx_gpio.h @@ -50,100 +50,35 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Encoding: +/* 28-bit Encoding: * - * ENCODING ...I RRRO DDDL SSVT GGGP PPPP - * GPIO INPUT ...0 .... .... ...T GGGP PPPP - * GPIO OUTPUT ...1 RRRO DDDL SSV. GGGP PPPP + * ENCODING ..IV GGGP PPPP MMMM MMMM MMMM MMMM + * GPIO INPUT ..0. GGGP PPPP MMMM MMMM MMMM MMMM + * GPIO OUTPUT ..1V GGGP PPPP MMMM MMMM MMMM MMMM */ /* Input/Output Selection: * - * ENCODING ...I .... .... .... .... .... + * ENCODING ..I. .... .... .... .... .... .... */ -#define GPIO_INPUT (0) /* Bit 20: 0=input */ -#define GPIO_OUTPUT (1 << 19) /* Bit 20: 1=output */ - -/* Output Pull Up/Down: - * - * GPIO OUTPUT ...1 RRR. .... .... .... .... - */ - -#define GPIO_PULL_SHIFT (17) /* Bits 17-19: Pull up/down selection */ -#define GPIO_PULL_MASK (7 << GPIO_PULL_SHIFT) -# define GPIO_PULL_NONE (0 << GPIO_PULL_SHIFT) /* Pull/keeper disabled */ -# define GPIO_PULL_KEEP (1 << GPIO_PULL_SHIFT) /* Output determined by keeper */ -# define GPIO_PULL_UP_22K (2 << GPIO_PULL_SHIFT) /* Pull up with 22 KOhm resister */ -# define GPIO_PULL_UP_47K (3 << GPIO_PULL_SHIFT) /* Pull up with 47 KOhm resister */ -# define GPIO_PULL_UP_100K (4 << GPIO_PULL_SHIFT) /* Pull up with 100 KOhm resister */ -# define GPIO_PULL_DOWN_100K (5 << GPIO_PULL_SHIFT) /* Pull down with 100 KOhm resister */ - -/* Open Drain Output: - * - * GPIO OUTPUT ...1 ...O .... .... .... .... - */ - -#define GPIO_CMOS_OUTPUT (1 << 16) /* Bit 16: 0=CMOS output */ -#define GPIO_OPENDRAIN (1 << 16) /* Bit 16: 1=Enable open-drain output */ - -/* Output Drive Strength: - * - * GPIO OUTPUT ...1 .... DDD. .... .... .... - */ - -#define GPIO_DRIVE_SHIFT (13) /* Bits 13-15: Output Drive Strength */ -#define GPIO_DRIVE_MASK (7 << GPIO_DRIVE_SHIFT) -# define GPIO_DRIVE_HIZ (0 << GPIO_DRIVE_SHIFT) /* HI-Z */ -# define GPIO_DRIVE_260OHM (1 << GPIO_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ -# define GPIO_DRIVE_130OHM (2 << GPIO_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ -# define GPIO_DRIVE_90OHM (3 << GPIO_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ -# define GPIO_DRIVE_60OHM (4 << GPIO_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ -# define GPIO_DRIVE_50OHM (5 << GPIO_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ -# define GPIO_DRIVE_40OHM (6 << GPIO_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ -# define GPIO_DRIVE_33OHM (7 << GPIO_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ - -/* Output Slew Rate: - * - * GPIO OUTPUT ...1 .... ...L .... .... .... - */ - -#define GPIO_SLEW_SLOW (0) /* Bit 12: 0=Slow Slew Rate */ -#define GPIO_SLEW_FAST (1 << 12) /* Bit 12: 1=Fast Slew Rate */ - -/* Output Speed: - * - * GPIO OUTPUT ...1 .... .... SS.. .... .... - */ - -#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: Speed */ -#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) -# define GPIO_SPEED_LOW (0 << GPIO_SPEED_SHIFT) /* Low frequency (50 MHz) */ -# define GPIO_SPEED_MEDIUM (1 << GPIO_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ -# define GPIO_SPEED_MAX (3 << GPIO_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ +#define GPIO_INPUT (0) /* Bit 25: 0=input */ +#define GPIO_OUTPUT (1 << 25) /* Bit 25: 1=output */ /* Initial Ouptut Value: * - * GPIO OUTPUT ...1 .... .... ..V. .... .... + * GPIO OUTPUT ..1V .... .... .... .... .... .... */ -#define GPIO_OUTPUT_ZERO (0) /* Bit 9: 0=Initial output is low */ -#define GPIO_OUTPUT_ONE (1 << 9) /* Bit 9: 1=Initial output is high */ - -/* Input Schmitt Trigger: - * - * GPIO INPUT ...0 .... .... ...T .... .... - */ - -#define GPIO_CMOS_INPUT (0) /* Bit 8: 0=CMOS input */ -#define GPIO_SCHMITT_TRIGGER (1 << 8) /* Bit 8: 1=Enable Schmitt trigger if input */ +#define GPIO_OUTPUT_ZERO (0) /* Bit 24: 0=Initial output is low */ +#define GPIO_OUTPUT_ONE (1 << 24) /* Bit 24: 1=Initial output is high */ /* GPIO Port Number * - * ENCODING .... .... .... .... GGG. .... + * ENCODING .... GGG. .... .... .... .... .... */ -#define GPIO_PORT_SHIFT (5) /* Bits 5-7: Speed */ +#define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */ #define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) # define GPIO_PORT1 (0 << GPIO_PORT_SHIFT) /* GPIO1 */ # define GPIO_PORT2 (1 << GPIO_PORT_SHIFT) /* GPIO2 */ @@ -155,10 +90,10 @@ /* GPIO Pin Number: * - * ENCODING .... .... .... .... ...P PPPP + * ENCODING .... ...P PPPP .... .... .... .... */ -#define GPIO_PIN_SHIFT (5) /* Bits 0-4: Speed */ +#define GPIO_PIN_SHIFT (16) /* Bits 16-20: GPIO pin number */ #define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) # define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */ # define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */ @@ -193,6 +128,16 @@ # define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */ # define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */ +/* IOMUX Pin Configuration: + * + * ENCODING .... .... .... MMMM MMMM MMMM MMMM + * + * See imx_iomuxc.h for detailed content. + */ + +#define GPIO_IOMUX_SHIFT (0) /* Bits 9-15: IOMUX pin configuration */ +#define GPIO_IOMUX_MASK (0xffff << GPIO_IOMUX_SHIFT) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/imx6/imx_iomuxc.c b/arch/arm/src/imx6/imx_iomuxc.c index e5ccc2361a..e56a6faed5 100644 --- a/arch/arm/src/imx6/imx_iomuxc.c +++ b/arch/arm/src/imx6/imx_iomuxc.c @@ -43,6 +43,7 @@ #include #include +#include "up_arch.h" #include "imx_iomuxc.h" /**************************************************************************** @@ -53,7 +54,9 @@ * * REVISIT: This could be greatly simplified: The Pad Control registers * map 1-to-1 with the Pad Mux registers except for two regions where - * there are no corresponding Pad Mux registers. + * there are no corresponding Pad Mux registers. The entire table could be + * replaced to two range checks and the appropriate offset added to the Pad + * Mux Register index. */ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] = @@ -360,6 +363,66 @@ unsigned int imx_padmux_map(unsigned int padmux) int imx_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset) { -#warning Missing logic - return -ENOSYS; + uint32_t regval = 0; + uint32_t value; + + /* Select CMOS input or Schmitt Trigger input */ + + if ((ioset & IOMUX_SCHMITT_TRIGGER) != 0) + { + regval |= PADCTL_SRE; + } + + /* Select drive strength */ + + value = (ioset & PADCTL_DSE_MASK) >> PADCTL_DSE_SHIFT; + regval |= PADCTL_DSE(value); + + /* Select spped */ + + value = (ioset & IOMUX_SPEED_MASK) >> IOMUX_SPEED_SHIFT; + regval |= PADCTL_SPEED(value); + + /* Select CMOS output or Open Drain outpout */ + + if ((ioset & IOMUX_OPENDRAIN) != 0) + { + regval |= PADCTL_ODE; + } + + /* Handle pull/keep selection */ + + switch (ioset & _IOMUX_PULLTYPE_MASK) + { + default: + case _IOMUX_PULL_NONE: + break; + + case _IOMUX_PULL_KEEP: + { + regval |= PADCTL_PKE; + } + break; + + case _IOMUX_PULL_ENABLE: + { + regval |= (PADCTL_PKE | PADCTL_PUE); + + value = (ioset & _IOMUX_PULLDESC_MASK) >> _IOMUX_PULLDESC_SHIFT; + regval |= PADCTL_PUS(value); + } + break; + } + + /* Select slow/fast slew rate */ + + if ((ioset & IOMUX_SLEW_FAST) != 0) + { + regval |= PADCTL_HYS; + } + + /* Write the result to the specified Pad Control register */ + + putreg32(regval, padctl); + return OK; } diff --git a/arch/arm/src/imx6/imx_iomuxc.h b/arch/arm/src/imx6/imx_iomuxc.h index 06a256b095..79cecec4c6 100644 --- a/arch/arm/src/imx6/imx_iomuxc.h +++ b/arch/arm/src/imx6/imx_iomuxc.h @@ -49,6 +49,88 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* 16-bit Encoding: + * + * .... RRRR ODDD LSST + */ + +/* Output Pull Up/Down: + * + * .... RRRR .... .... + */ + +#define _IOMUX_PULLTYPE_SHIFT (8) /* Bits 8-9: Pull up/down type */ +#define _IOMUX_PULLTYPE_MASK (3 << _IOMUX_PULLTYPE_SHIFT) +# define _IOMUX_PULL_NONE (0 << _IOMUX_PULLTYPE_SHIFT) /* Pull/keeper disabled */ +# define _IOMUX_PULL_KEEP (1 << _IOMUX_PULLTYPE_SHIFT) /* Output determined by keeper */ +# define _IOMUX_PULL_ENABLE (2 << _IOMUX_PULLTYPE_SHIFT) /* Output pulled up or down */ + +#define _IOMUX_PULLDESC_SHIFT (10) /* Bits 10-11: Pull up/down description */ +#define _IOMUX_PULLDESC_MASK (3 << _IOMUX_PULLDESC_SHIFT) +# define _IOMUX_PULL_UP_22K (PULL_UP_22K << _IOMUX_PULLDESC_SHIFT) /* Pull up with 22 KOhm resister */ +# define _IOMUX_PULL_UP_47K (PULL_UP_47K << _IOMUX_PULLDESC_SHIFT) /* Pull up with 47 KOhm resister */ +# define _IOMUX_PULL_UP_100K (PULL_UP_100K << _IOMUX_PULLDESC_SHIFT) /* Pull up with 100 KOhm resister */ +# define _IOMUX_PULL_DOWN_100K (PULL_DOWN_100K << _IOMUX_PULLDESC_SHIFT) /* Pull down with 100 KOhm resister */ + +#define IOMUX_PULL_SHIFT (8) /* Bits 8-11: Pull up/down selection */ +#define IOMUX_PULL_MASK (15 << IOMUX_PULL_SHIFT) +# define IOMUX_PULL_NONE _IOMUX_PULL_NONE +# define IOMUX_PULL_KEEP _IOMUX_PULL_KEEP +# define IOMUX_PULL_UP_22K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_22K) +# define IOMUX_PULL_UP_47K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_47K) +# define IOMUX_PULL_UP_100K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_UP_100K) +# define IOMUX_PULL_DOWN_100K (_IOMUX_PULL_ENABLE | _IOMUX_PULL_DOWN_100K) + +/* Open Drain Output: + * + * .... .... O... .... + */ + +#define IOMUX_CMOS_OUTPUT (1 << 7) /* Bit 7: 0=CMOS output */ +#define IOMUX_OPENDRAIN (1 << 7) /* Bit 7: 1=Enable open-drain output */ + +/* Output Drive Strength: + * + * .... .... .DDD .... + */ + +#define IOMUX_DRIVE_SHIFT (4) /* Bits 4-6: Output Drive Strength */ +#define IOMUX_DRIVE_MASK (7 << IOMUX_DRIVE_SHIFT) +# define IOMUX_DRIVE_HIZ (DRIVE_HIZ << IOMUX_DRIVE_SHIFT) /* HI-Z */ +# define IOMUX_DRIVE_260OHM (DRIVE_260OHM << IOMUX_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +# define IOMUX_DRIVE_130OHM (DRIVE_130OHM << IOMUX_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +# define IOMUX_DRIVE_90OHM (DRIVE_90OHM << IOMUX_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +# define IOMUX_DRIVE_60OHM (DRIVE_60OHM << IOMUX_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +# define IOMUX_DRIVE_50OHM (DRIVE_50OHM << IOMUX_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +# define IOMUX_DRIVE_40OHM (DRIVE_40OHM << IOMUX_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +# define IOMUX_DRIVE_33OHM (DRIVE_33OHM << IOMUX_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ + +/* Output Slew Rate: + * + * .... .... .... L... + */ + +#define IOMUX_SLEW_SLOW (0) /* Bit 3: 0=Slow Slew Rate */ +#define IOMUX_SLEW_FAST (1 << 3) /* Bit 3: 1=Fast Slew Rate */ + +/* Output Speed: + * + * .... .... .... .SS. + */ + +#define IOMUX_SPEED_SHIFT (2) /* Bits 2-3: Speed */ +#define IOMUX_SPEED_MASK (3 << IOMUX_SPEED_SHIFT) +# define IOMUX_SPEED_LOW (SPEED_LOW << IOMUX_SPEED_SHIFT) /* Low frequency (50 MHz) */ +# define IOMUX_SPEED_MEDIUM (SPEED_MEDIUM << IOMUX_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ +# define IOMUX_SPEED_MAX (SPEED_MAX << IOMUX_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ + +/* Input Schmitt Trigger: + * + * .... .... .... ...T + */ + +#define IOMUX_CMOS_INPUT (0) /* Bit 0: 0=CMOS input */ +#define IOMUX_SCHMITT_TRIGGER (1 << 0) /* Bit 0: 1=Enable Schmitt trigger if input */ /**************************************************************************** * Public Types