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Yet more spacing issues

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This commit is contained in:
Gregory Nutt 2015-10-07 20:24:19 -06:00
parent a92842906f
commit beb060d422
11 changed files with 23 additions and 22 deletions
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4
arch/arm/src/kinetis/kinetis_irq.c
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@ -401,10 +401,10 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(KINETIS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(KINETIS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
kinetis_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
kinetis_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management

10
arch/arm/src/lpc2378/lpc23xx_io.c
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@ -53,11 +53,11 @@
****************************************************************************/
/****************************************************************************
* Name: IO_Init()
*
* Descriptions: Initialize the target board before running the main()
*
************************************************************************/
* Name: IO_Init()
*
* Descriptions: Initialize the target board before running the main()
*
****************************************************************************/
void IO_Init(void)
{

2
arch/arm/src/lpc31xx/lpc31_spi.c
View File

@ -606,7 +606,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
uint16_t setbits;
uint16_t clrbits;
/* Has the mode changed? */
/* Has the mode changed? */
if (mode != priv->mode)
{

3
arch/arm/src/lpc43xx/lpc43_ethernet.c
View File

@ -2975,7 +2975,8 @@ static int lpc43_ioctl(struct net_driver_s *dev, int cmd, long arg)
* Function: lpc43_phyintenable
*
* Description:
* Enable link up/down PHY interrupts. The interrupt protocol is like this:
* Enable link up/down PHY interrupts. The interrupt protocol is like
* this:
*
* - Interrupt status is cleared when the interrupt is enabled.
* - Interrupt occurs. Interrupt is disabled (at the processor level) when

4
arch/arm/src/lpc43xx/lpc43_irq.c
View File

@ -376,10 +376,10 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
lpc43_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
lpc43_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management

4
arch/arm/src/sam34/sam_irq.c
View File

@ -437,10 +437,10 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
sam_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
sam_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management

4
arch/arm/src/samv7/sam_irq.c
View File

@ -437,10 +437,10 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
sam_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
sam_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management

4
arch/arm/src/stm32/stm32_irq.c
View File

@ -384,10 +384,10 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management

4
arch/arm/src/stm32f7/stm32_irq.c
View File

@ -471,10 +471,10 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management

2
arch/arm/src/tiva/tiva_gpio.c
View File

@ -461,7 +461,7 @@ static inline void tiva_gpiopadstrength(uint32_t base, uint32_t pin,
modifyreg32(base + TIVA_GPIO_SLR_OFFSET, slrclr, slrset);
#ifdef CONFIG_ARCH_CHIP_TM4C129
/* TODO: Add TM4C129 registers (TIVA_GPIO_DR12R) */
/* TODO: Add TM4C129 registers (TIVA_GPIO_DR12R) */
# if 0
/* Set the 12-mA drive select register. This register only appears in
* TM4E111 and later device classes, but is a harmless write on older

4
arch/arm/src/tiva/tiva_irq.c
View File

@ -455,10 +455,10 @@ void up_irqinitialize(void)
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(TIVA_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(TIVA_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
tiva_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
tiva_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management