Merged in raiden00/nuttx_pe (pull request #758)
stm32/stm32_adc: major refator stm32/stm32_adc: use STM32 ADC IP core version and ADC available functions instead of chip family names in conditional compilation stm32/chip: replace family specific ADC headers with STM32 ADC IP core version headers stm32/stm32_adc: configurable sample time supported for all chips, not only L1 stm32/stm32_adc: enable/disable interrupts supported for all chips, not only L1 stm32/stm32_adc: resolution configuration stm32/stm32f33xxx_adc: remove wrong assertion configs/nucleo-f303ze: support for ADC and ADC example configs/stm32f429i-disco: support for ADC and ADC example Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
GregoryN
parent
1a754deaa0
commit
becb667f56
@ -1381,6 +1381,8 @@ config STM32_STM32L15XX
|
||||
select STM32_HAVE_TIM3
|
||||
select STM32_HAVE_TIM4
|
||||
select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
|
||||
config STM32_ENERGYLITE
|
||||
bool
|
||||
@ -1401,6 +1403,8 @@ config STM32_STM32F10XX
|
||||
select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY
|
||||
select STM32_HAVE_RTC_COUNTER
|
||||
select STM32_HAVE_TIM3
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1_BASIC
|
||||
|
||||
config STM32_VALUELINE
|
||||
bool
|
||||
@ -1511,6 +1515,8 @@ config STM32_STM32F20XX
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_IOCOMPENSATION
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
|
||||
config STM32_STM32F205
|
||||
bool
|
||||
@ -1593,6 +1599,7 @@ config STM32_STM32F30XX
|
||||
select STM32_HAVE_TIM16
|
||||
select STM32_HAVE_TIM17
|
||||
select STM32_HAVE_IP_TIMERS_V2
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
|
||||
config STM32_STM32F302
|
||||
bool
|
||||
@ -1632,6 +1639,7 @@ config STM32_STM32F33XX
|
||||
select STM32_HAVE_DAC2
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_IP_TIMERS_V2
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
|
||||
config STM32_STM32F37XX
|
||||
bool
|
||||
@ -1655,6 +1663,8 @@ config STM32_STM32F37XX
|
||||
select STM32_HAVE_SPI2
|
||||
select STM32_HAVE_SPI3
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1_BASIC
|
||||
|
||||
config STM32_STM32F4XXX
|
||||
bool
|
||||
@ -1662,6 +1672,8 @@ config STM32_STM32F4XXX
|
||||
select STM32_HAVE_SPI2
|
||||
select STM32_HAVE_I2C2
|
||||
select STM32_HAVE_IOCOMPENSATION
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
|
||||
config STM32_STM32F401xBC
|
||||
bool
|
||||
@ -2027,6 +2039,10 @@ config STM32_HAVE_UART8
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_TIMERS_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_TIMERS_V2
|
||||
bool
|
||||
default n
|
||||
@ -2099,6 +2115,24 @@ config STM32_HAVE_TIM17
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V1
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V1_BASIC
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_IP_ADC_V1
|
||||
|
||||
config STM32_HAVE_IP_ADC_V2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_HAVE_IP_ADC_V2_BASIC
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
|
||||
config STM32_HAVE_ADC2
|
||||
bool
|
||||
default n
|
||||
@ -7484,6 +7518,38 @@ endmenu # "HRTIM Configuration"
|
||||
menu "ADC Configuration"
|
||||
depends on STM32_ADC
|
||||
|
||||
config STM32_ADC1_RESOLUTION
|
||||
int "ADC1 resolution"
|
||||
depends on STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
|
||||
|
||||
config STM32_ADC2_RESOLUTION
|
||||
int "ADC2 resolution"
|
||||
depends on STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
|
||||
|
||||
config STM32_ADC3_RESOLUTION
|
||||
int "ADC3 resolution"
|
||||
depends on STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
|
||||
|
||||
config STM32_ADC4_RESOLUTION
|
||||
int "ADC4 resolution"
|
||||
depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
|
||||
|
||||
config STM32_ADC_NO_STARTUP_CONV
|
||||
bool "Do not start conversion when opening ADC device"
|
||||
default n
|
||||
@ -7498,6 +7564,12 @@ config STM32_ADC_NOIRQ
|
||||
Do not use default ADC interrupts handlers.
|
||||
Only for STM32_STM32F33XX at this moment.
|
||||
|
||||
config STM32_ADC_CHANGE_SAMPLETIME
|
||||
bool "ADC sample time configuration"
|
||||
default n
|
||||
---help---
|
||||
Enable ADC sample time configuration (SMPRx registers).
|
||||
|
||||
config STM32_ADC1_DMA
|
||||
bool "ADC1 DMA"
|
||||
depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_adc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -44,847 +44,28 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
/* There are 2 main types of ADC IP cores among STM32 chips:
|
||||
* 1. STM32 ADC IPv1:
|
||||
* a) basic version for F1 and F37x
|
||||
* b) extended version for F2, F4, F7, L1:
|
||||
* 2. STM32 ADC IPv2:
|
||||
* a) basic version for F0 and L0
|
||||
* b) extended version for F3 (without F37x), H7, L4, L4+
|
||||
*
|
||||
* We also distinguish the modified STM32 ADC IPv1 core for the L1 family,
|
||||
* which differs too much to keep it in the same file as ADC IPv1.
|
||||
*/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
|
||||
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
|
||||
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
|
||||
#ifndef CONFIG_STM32_STM32L15XX
|
||||
# define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
|
||||
# define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
|
||||
# define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
|
||||
# define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
|
||||
# define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
|
||||
# define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
|
||||
# define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
|
||||
# define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
|
||||
# define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
|
||||
# define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
|
||||
# define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
|
||||
#else
|
||||
# define STM32_ADC_SMPR3_OFFSET 0x0014 /* ADC sample time register 3 (32-bit) */
|
||||
# define STM32_ADC_JOFR1_OFFSET 0x0018 /* ADC injected channel data offset register 1 (32-bit) */
|
||||
# define STM32_ADC_JOFR2_OFFSET 0x001c /* ADC injected channel data offset register 2 (32-bit) */
|
||||
# define STM32_ADC_JOFR3_OFFSET 0x0020 /* ADC injected channel data offset register 3 (32-bit) */
|
||||
# define STM32_ADC_JOFR4_OFFSET 0x0024 /* ADC injected channel data offset register 4 (32-bit) */
|
||||
# define STM32_ADC_HTR_OFFSET 0x0028 /* ADC watchdog high threshold register (32-bit) */
|
||||
# define STM32_ADC_LTR_OFFSET 0x002c /* ADC watchdog low threshold register (32-bit) */
|
||||
# define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 (32-bit) */
|
||||
# define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 (32-bit) */
|
||||
# define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 (32-bit) */
|
||||
# define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 (32-bit) */
|
||||
# define STM32_ADC_SQR5_OFFSET 0x0040 /* ADC regular sequence register 5 (32-bit) */
|
||||
# define STM32_ADC_JSQR_OFFSET 0x0044 /* ADC injected sequence register (32-bit) */
|
||||
# define STM32_ADC_JDR1_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_JDR2_OFFSET 0x004c /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_JDR3_OFFSET 0x0050 /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_JDR4_OFFSET 0x0054 /* ADC injected data register 1 (32-bit) */
|
||||
# define STM32_ADC_DR_OFFSET 0x0058 /* ADC regular data register (32-bit) */
|
||||
# define STM32_ADC_SMPR0_OFFSET 0X005c /* ADC sample time register 3 (32-bit) */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
|
||||
# ifndef CONFIG_STM32_STM32L15XX
|
||||
# define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define STM32_ADC1_BASE STM32_ADC_BASE
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 0
|
||||
# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# ifdef CONFIG_STM32_STM32L15XX
|
||||
# define STM32_ADC1_SMPR3 (STM32_ADC1_BASE+STM32_ADC_SMPR3_OFFSET)
|
||||
# endif
|
||||
# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# ifdef CONFIG_STM32_STM32L15XX
|
||||
# define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
# define STM32_ADC1_SQR5 (STM32_ADC1_BASE+STM32_ADC_SQR5_OFFSET)
|
||||
# endif
|
||||
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
# ifdef CONFIG_STM32_STM32L15XX
|
||||
# define STM32_ADC1_SMPR0 (STM32_ADC1_BASE+STM32_ADC_SMPR0_OFFSET)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 1
|
||||
# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 2
|
||||
# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
# define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
# define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
# ifndef CONFIG_STM32_STM32L15XX
|
||||
# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* ADC status register */
|
||||
|
||||
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
|
||||
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
|
||||
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
|
||||
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
|
||||
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32L15XX)
|
||||
# define ADC_SR_ADONS (1 << 6) /* Bit 6 : ADC ON status. Set and cleared by HW */
|
||||
# define ADC_SR_RCNR (1 << 8) /* Bit 8 : Regular channel not ready. Set and cleared by HW */
|
||||
# define ADC_SR_JCNR (1 << 9) /* Bit 9 : Injected channel not ready. Set and cleared by HW */
|
||||
#endif
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
|
||||
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
|
||||
|
||||
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
|
||||
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
|
||||
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
|
||||
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
|
||||
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
|
||||
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
|
||||
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
|
||||
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
|
||||
|
||||
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
|
||||
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX)
|
||||
# define ADC_CR1_PDD (1 << 16) /* Bit 16 : Power down during the delay phase. This bit must be written only when ADON=0 */
|
||||
# define ADC_CR1_PDI (1 << 17) /* Bit 17 : Power down during the idle phase. This bit must
|
||||
* be written only when ADON=0 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F10XX
|
||||
# define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */
|
||||
# define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT)
|
||||
# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */
|
||||
# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */
|
||||
# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */
|
||||
# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */
|
||||
# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */
|
||||
# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */
|
||||
# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */
|
||||
# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */
|
||||
#endif
|
||||
|
||||
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
|
||||
# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
|
||||
# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
|
||||
# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
|
||||
# define ADC_CR1_RESERVED (0xfb3f0000)
|
||||
#endif
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
|
||||
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F10XX
|
||||
# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
|
||||
#elif defined(CONFIG_STM32_STM32L15XX)
|
||||
# define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no
|
||||
* conversion is on going. This bit is available in high and medium+
|
||||
* density devices only.
|
||||
*/
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_CR2_DELS_SHIFT (4) /* Bits 2-0: Delay selection */
|
||||
# define ADC_CR2_DELS_MASK (0x07 << ADC_CR2_DELS_SHIFT)
|
||||
#
|
||||
# define ADC_CR2_DELS_NODEL (0x0 << ADC_CR2_DELS_SHIFT) /* No delay */
|
||||
# define ADC_CR2_DELS_TILLRD (0x01 << ADC_CR2_DELS_SHIFT) /* Until the converted data have been read */
|
||||
# define ADC_CR2_DELS_APB7 (0x02 << ADC_CR2_DELS_SHIFT) /* 7 APB clock cycles after the end of conversion */
|
||||
# define ADC_CR2_DELS_APB15 (0x03 << ADC_CR2_DELS_SHIFT) /* 15 APB clock cycles after the end of conversion */
|
||||
# define ADC_CR2_DELS_APB31 (0x04 << ADC_CR2_DELS_SHIFT) /* 31 APB clock cycles after the end of conversion */
|
||||
# define ADC_CR2_DELS_APB63 (0x05 << ADC_CR2_DELS_SHIFT) /* 63 APB clock cycles after the end of conversion */
|
||||
# define ADC_CR2_DELS_APB127 (0x06 << ADC_CR2_DELS_SHIFT) /* 127 APB clock cycles after the end of conversion */
|
||||
# define ADC_CR2_DELS_APB255 (0x07 << ADC_CR2_DELS_SHIFT) /* 255 APB clock cycles after the end of conversion */
|
||||
#endif
|
||||
|
||||
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
|
||||
# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
|
||||
#endif
|
||||
|
||||
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
/* Bits 12-15: Reserved */
|
||||
# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
|
||||
# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/
|
||||
# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
|
||||
# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1)
|
||||
# if defined(CONFIG_STM32_STM32L15XX)
|
||||
# include "stm32_adc_v1l1.h" /* Special case for L1 */
|
||||
# else
|
||||
# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
|
||||
# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */
|
||||
# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */
|
||||
# include "stm32_adc_v1.h"
|
||||
# endif
|
||||
|
||||
# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
|
||||
# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
|
||||
# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
|
||||
# define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
|
||||
/* Bit 23: Reserved, must be kept at reset value. */
|
||||
# define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
|
||||
# define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
|
||||
# ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
|
||||
# else
|
||||
# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
|
||||
# endif
|
||||
|
||||
# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
|
||||
# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
|
||||
# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
|
||||
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
|
||||
# define ADC_CR2_RESERVED (0x8080f0fc)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
# include "stm32_adc_v2.h"
|
||||
#else
|
||||
# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */
|
||||
# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_T1TRGO (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T2TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */
|
||||
# define ADC_CR2_JEXTSEL_SWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */
|
||||
|
||||
# define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */
|
||||
# define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */
|
||||
# define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */
|
||||
# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */
|
||||
|
||||
# define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */
|
||||
# define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */
|
||||
# define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */
|
||||
# define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */
|
||||
# error "STM32 ADC IP version not specified"
|
||||
#endif
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
|
||||
# define ADC_SMPR_3 0 /* 000: 3 cycles */
|
||||
# define ADC_SMPR_15 1 /* 001: 15 cycles */
|
||||
# define ADC_SMPR_28 2 /* 010: 28 cycles */
|
||||
# define ADC_SMPR_56 3 /* 011: 56 cycles */
|
||||
# define ADC_SMPR_84 4 /* 100: 84 cycles */
|
||||
# define ADC_SMPR_112 5 /* 101: 112 cycles */
|
||||
# define ADC_SMPR_144 6 /* 110: 144 cycles */
|
||||
# define ADC_SMPR_480 7 /* 111: 480 cycles */
|
||||
|
||||
#elif !defined(CONFIG_STM32_STM32L15XX) && !defined(CONFIG_STM32_STM32F20XX) && !defined(CONFIG_STM32_STM32F4XXX)
|
||||
|
||||
# define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
|
||||
# define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */
|
||||
# define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */
|
||||
# define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */
|
||||
# define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */
|
||||
# define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */
|
||||
# define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */
|
||||
# define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32L15XX)
|
||||
|
||||
# define ADC_SMPR_4 0 /* 000: 3 cycles */
|
||||
# define ADC_SMPR_9 1 /* 001: 9 cycles */
|
||||
# define ADC_SMPR_16 2 /* 010: 16 cycles */
|
||||
# define ADC_SMPR_24 3 /* 011: 24 cycles */
|
||||
# define ADC_SMPR_48 4 /* 100: 48 cycles */
|
||||
# define ADC_SMPR_96 5 /* 101: 96 cycles */
|
||||
# define ADC_SMPR_192 6 /* 110: 192 cycles */
|
||||
# define ADC_SMPR_384 7 /* 111: 384 cycles */
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
# define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
|
||||
# define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
# define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
|
||||
# define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
# define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
|
||||
# define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
# define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
|
||||
# define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
# define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
|
||||
# define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
# define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
|
||||
# define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
# define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
|
||||
# define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
# define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT)
|
||||
# endif
|
||||
#else
|
||||
# define ADC_SMPR1_SMP20_SHIFT (0) /* Bits 0-2: Channel 20 Sample time selection */
|
||||
# define ADC_SMPR1_SMP20_MASK (7 << ADC_SMPR1_SMP20_SHIFT)
|
||||
# define ADC_SMPR1_SMP21_SHIFT (3) /* Bits 3-5: Channel 21 Sample time selection */
|
||||
# define ADC_SMPR1_SMP21_MASK (7 << ADC_SMPR1_SMP21_SHIFT)
|
||||
# define ADC_SMPR1_SMP22_SHIFT (6) /* Bits 6-8: Channel 22 Sample time selection */
|
||||
# define ADC_SMPR1_SMP22_MASK (7 << ADC_SMPR1_SMP22_SHIFT)
|
||||
# define ADC_SMPR1_SMP23_SHIFT (9) /* Bits 9-11: Channel 23 Sample time selection */
|
||||
# define ADC_SMPR1_SMP23_MASK (7 << ADC_SMPR1_SMP23_SHIFT)
|
||||
# define ADC_SMPR1_SMP24_SHIFT (12) /* Bits 12-14: Channel 24 Sample time selection */
|
||||
# define ADC_SMPR1_SMP24_MASK (7 << ADC_SMPR1_SMP24_SHIFT)
|
||||
# define ADC_SMPR1_SMP25_SHIFT (15) /* Bits 15-17: Channel 25 Sample time selection */
|
||||
# define ADC_SMPR1_SMP25_MASK (7 << ADC_SMPR1_SMP25_SHIFT)
|
||||
# define ADC_SMPR1_SMP26_SHIFT (18) /* Bits 18-20: Channel 26 Sample time selection */
|
||||
# define ADC_SMPR1_SMP26_MASK (7 << ADC_SMPR1_SMP26_SHIFT)
|
||||
# define ADC_SMPR1_SMP27_SHIFT (21) /* Bits 21-23: Channel 27 Sample time selection */
|
||||
# define ADC_SMPR1_SMP27_MASK (7 << ADC_SMPR1_SMP27_SHIFT)
|
||||
# define ADC_SMPR1_SMP28_SHIFT (24) /* Bits 24-26: Channel 28 Sample time selection */
|
||||
# define ADC_SMPR1_SMP28_MASK (7 << ADC_SMPR1_SMP28_SHIFT)
|
||||
# define ADC_SMPR1_SMP29_SHIFT (27) /* Bits 27-29: Channel 29 Sample time selection */
|
||||
# define ADC_SMPR1_SMP29_MASK (7 << ADC_SMPR1_SMP29_SHIFT)
|
||||
#endif
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#ifndef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
# define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
|
||||
# define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
# define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
|
||||
# define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
# define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
|
||||
# define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
# define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
|
||||
# define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
# define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
|
||||
# define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
# define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
|
||||
# define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
# define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
|
||||
# define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
# define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
|
||||
# define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
# define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
|
||||
# define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
# define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
|
||||
#else
|
||||
# define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
# define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT)
|
||||
# define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
# define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT)
|
||||
# define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
# define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT)
|
||||
# define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
# define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT)
|
||||
# define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
# define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT)
|
||||
# define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
# define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT)
|
||||
# define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
# define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT)
|
||||
# define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
# define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
|
||||
# define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
# define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT)
|
||||
# define ADC_SMPR2_SMP19_SHIFT (27) /* Bits 27-29: Channel 18 Sample time selection */
|
||||
# define ADC_SMPR2_SMP19_MASK (7 << ADC_SMPR2_SMP19_SHIFT)
|
||||
#endif
|
||||
|
||||
/* ADC sample time register 3 */
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SMPR3_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
# define ADC_SMPR3_SMP0_MASK (7 << ADC_SMPR3_SMP0_SHIFT)
|
||||
# define ADC_SMPR3_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
# define ADC_SMPR3_SMP1_MASK (7 << ADC_SMPR3_SMP1_SHIFT)
|
||||
# define ADC_SMPR3_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
# define ADC_SMPR3_SMP2_MASK (7 << ADC_SMPR3_SMP2_SHIFT)
|
||||
# define ADC_SMPR3_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
# define ADC_SMPR3_SMP3_MASK (7 << ADC_SMPR3_SMP3_SHIFT)
|
||||
# define ADC_SMPR3_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
# define ADC_SMPR3_SMP4_MASK (7 << ADC_SMPR3_SMP4_SHIFT)
|
||||
# define ADC_SMPR3_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
# define ADC_SMPR3_SMP5_MASK (7 << ADC_SMPR3_SMP5_SHIFT)
|
||||
# define ADC_SMPR3_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
# define ADC_SMPR3_SMP6_MASK (7 << ADC_SMPR3_SMP6_SHIFT)
|
||||
# define ADC_SMPR3_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
# define ADC_SMPR3_SMP7_MASK (7 << ADC_SMPR3_SMP7_SHIFT)
|
||||
# define ADC_SMPR3_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
# define ADC_SMPR3_SMP8_MASK (7 << ADC_SMPR3_SMP8_SHIFT)
|
||||
# define ADC_SMPR3_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
# define ADC_SMPR3_SMP9_MASK (7 << ADC_SMPR3_SMP9_SHIFT)
|
||||
#endif
|
||||
|
||||
/* ADC sample time register 0 */
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SMPR3_SMP30_SHIFT (0) /* Bits 2-0: Channel 30 Sample time selection */
|
||||
# define ADC_SMPR3_SMP30_MASK (7 << ADC_SMPR3_SMP30_SHIFT)
|
||||
# define ADC_SMPR3_SMP31_SHIFT (3) /* Bits 5-3: Channel 31 Sample time selection */
|
||||
# define ADC_SMPR3_SMP31_MASK (7 << ADC_SMPR3_SMP31_SHIFT)
|
||||
#endif
|
||||
/* ADC injected channel data offset register 1-4 */
|
||||
|
||||
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
|
||||
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
|
||||
|
||||
/* ADC watchdog high threshold register */
|
||||
|
||||
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
|
||||
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
|
||||
|
||||
/* ADC watchdog low threshold register */
|
||||
|
||||
#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */
|
||||
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#ifndef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
|
||||
# define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
|
||||
# define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
|
||||
# define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
|
||||
# define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
|
||||
# define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
|
||||
# define ADC_SQR1_RESERVED (0xff000000)
|
||||
# define ADC_SQR1_FIRST (13)
|
||||
# define ADC_SQR1_LAST (16)
|
||||
# define ADC_SQR1_SQ_OFFSET (0)
|
||||
#else
|
||||
# define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT)
|
||||
# define ADC_SQR1_SQ26_SHIFT (5) /* Bits 9-5: 26th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ26_MASK (0x1f << ADC_SQR1_SQ26_SHIFT)
|
||||
# define ADC_SQR1_SQ27_SHIFT (10) /* Bits 14-10: 27th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ27_MASK (0x1f << ADC_SQR1_SQ27_SHIFT)
|
||||
# define ADC_SQR1_SQ28_SHIFT (15) /* Bits 19-15: 28th conversion in regular sequence */
|
||||
# define ADC_SQR1_SQ28_MASK (0x1f << ADC_SQR1_SQ28_SHIFT)
|
||||
# define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */
|
||||
# define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT)
|
||||
# define ADC_SQR1_RESERVED (0xff000000)
|
||||
# define ADC_SQR1_FIRST (25)
|
||||
# define ADC_SQR1_LAST (28)
|
||||
# define ADC_SQR1_SQ_OFFSET (0)
|
||||
#endif
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#ifndef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
# define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
# define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
# define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
|
||||
# define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
|
||||
# define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
|
||||
# define ADC_SQR2_RESERVED (0xc0000000)
|
||||
# define ADC_SQR2_FIRST (7)
|
||||
# define ADC_SQR2_LAST (12)
|
||||
# define ADC_SQR2_SQ_OFFSET (0)
|
||||
#else
|
||||
# define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT)
|
||||
# define ADC_SQR2_SQ20_SHIFT (5) /* Bits 9-5: 20th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ20_MASK (0x1f << ADC_SQR2_SQ20_SHIFT)
|
||||
# define ADC_SQR2_SQ21_SHIFT (10) /* Bits 14-10: 21th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ21_MASK (0x1f << ADC_SQR2_SQ21_SHIFT)
|
||||
# define ADC_SQR2_SQ22_SHIFT (15) /* Bits 19-15: 22th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ22_MASK (0x1f << ADC_SQR2_SQ22_SHIFT)
|
||||
# define ADC_SQR2_SQ23_SHIFT (20) /* Bits 24-20: 23th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ23_MASK (0x1f << ADC_SQR2_SQ23_SHIFT )
|
||||
# define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */
|
||||
# define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT)
|
||||
# define ADC_SQR2_RESERVED (0xc0000000)
|
||||
# define ADC_SQR2_FIRST (19)
|
||||
# define ADC_SQR2_LAST (24)
|
||||
# define ADC_SQR2_SQ_OFFSET (0)
|
||||
#endif
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#ifndef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
|
||||
# define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
|
||||
# define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
|
||||
# define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
|
||||
# define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
|
||||
# define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
|
||||
# define ADC_SQR3_RESERVED (0xc0000000)
|
||||
# define ADC_SQR3_FIRST (1)
|
||||
# define ADC_SQR3_LAST (6)
|
||||
# define ADC_SQR3_SQ_OFFSET (0)
|
||||
#else
|
||||
# define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT)
|
||||
# define ADC_SQR3_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT)
|
||||
# define ADC_SQR3_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ15_MASK (0x1f << ADC_SQR3_SQ15_SHIFT)
|
||||
# define ADC_SQR3_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ16_MASK (0x1f << ADC_SQR3_SQ16_SHIFT)
|
||||
# define ADC_SQR3_SQ17_SHIFT (20) /* Bits 24-20: 17th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ17_MASK (0x1f << ADC_SQR3_SQ17_SHIFT )
|
||||
# define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */
|
||||
# define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT)
|
||||
# define ADC_SQR3_RESERVED (0xc0000000)
|
||||
# define ADC_SQR3_FIRST (13)
|
||||
# define ADC_SQR3_LAST (18)
|
||||
# define ADC_SQR3_SQ_OFFSET (0)
|
||||
#endif
|
||||
|
||||
/* ADC regular sequence register 4 */
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SQR4_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
# define ADC_SQR4_SQ7_MASK (0x1f << ADC_SQR4_SQ7_SHIFT)
|
||||
# define ADC_SQR4_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
# define ADC_SQR4_SQ8_MASK (0x1f << ADC_SQR4_SQ8_SHIFT)
|
||||
# define ADC_SQR4_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
# define ADC_SQR4_SQ9_MASK (0x1f << ADC_SQR4_SQ9_SHIFT)
|
||||
# define ADC_SQR4_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
# define ADC_SQR4_SQ10_MASK (0x1f << ADC_SQR4_SQ10_SHIFT)
|
||||
# define ADC_SQR4_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
|
||||
# define ADC_SQR4_SQ11_MASK (0x1f << ADC_SQR4_SQ11_SHIFT )
|
||||
# define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
|
||||
# define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT)
|
||||
# define ADC_SQR4_RESERVED (0xc0000000)
|
||||
# define ADC_SQR4_FIRST (7)
|
||||
# define ADC_SQR4_LAST (12)
|
||||
# define ADC_SQR4_SQ_OFFSET (0)
|
||||
#endif
|
||||
|
||||
/* ADC regular sequence register 5 */
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_SQR5_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
# define ADC_SQR5_SQ1_MASK (0x1f << ADC_SQR5_SQ1_SHIFT)
|
||||
# define ADC_SQR5_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
# define ADC_SQR5_SQ2_MASK (0x1f << ADC_SQR5_SQ2_SHIFT)
|
||||
# define ADC_SQR5_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
# define ADC_SQR5_SQ3_MASK (0x1f << ADC_SQR5_SQ3_SHIFT)
|
||||
# define ADC_SQR5_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
# define ADC_SQR5_SQ4_MASK (0x1f << ADC_SQR5_SQ4_SHIFT)
|
||||
# define ADC_SQR5_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
|
||||
# define ADC_SQR5_SQ5_MASK (0x1f << ADC_SQR5_SQ5_SHIFT )
|
||||
# define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
|
||||
# define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT)
|
||||
# define ADC_SQR5_RESERVED (0xc0000000)
|
||||
# define ADC_SQR5_FIRST (1)
|
||||
# define ADC_SQR5_LAST (6)
|
||||
# define ADC_SQR5_SQ_OFFSET (0)
|
||||
#endif
|
||||
|
||||
/* Offset between SQ bits */
|
||||
|
||||
#define ADC_SQ_OFFSET (5)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
|
||||
/* ADC injected data register 1-4 */
|
||||
|
||||
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
|
||||
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
|
||||
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F10XX
|
||||
# define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */
|
||||
# define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Common status register */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
#
|
||||
# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
|
||||
# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
|
||||
# define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
|
||||
# define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
|
||||
# define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
|
||||
# define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
|
||||
# /* Bits 6-7: Reserved, must be kept at reset value. */
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_CSR_ADONS1 (1 << 6) /* Bit 6: ADON Status of ADC1. This bit is a copy of the ADONS bit in the ADC_SR register. */
|
||||
#endif
|
||||
#
|
||||
# ifndef CONFIG_STM32_STM32L15XX
|
||||
# define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
|
||||
# define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
|
||||
# define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
|
||||
# define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
|
||||
# define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
|
||||
# define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
|
||||
# /* Bits 14-15: Reserved, must be kept at reset value. */
|
||||
# define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
|
||||
# define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
|
||||
# define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
|
||||
# define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
|
||||
# define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
|
||||
# define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
|
||||
# /* Bits 22-31: Reserved, must be kept at reset value. */
|
||||
# endif
|
||||
#
|
||||
#endif
|
||||
|
||||
/* Common control register */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
|
||||
# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
|
||||
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */
|
||||
/* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
|
||||
# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */
|
||||
/* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
|
||||
# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
|
||||
/* Bits 5-7: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
|
||||
# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
|
||||
# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
|
||||
/* Bit 12 Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
|
||||
|
||||
# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */
|
||||
# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT)
|
||||
# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
|
||||
# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
|
||||
# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
|
||||
# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
|
||||
|
||||
# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
|
||||
# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
|
||||
# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
|
||||
# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
|
||||
# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
|
||||
# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
|
||||
/* Bits 18-21: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */
|
||||
# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
|
||||
/* Bits 24-31 Reserved, must be kept at reset value. */
|
||||
#elif defined(CONFIG_STM32_STM32L15XX)
|
||||
/* Bits 15-0: Reserved, must be kept at reset value */
|
||||
# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
|
||||
# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
|
||||
# define ADC_CCR_ADCPRE_DIV1 (0 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 1 */
|
||||
# define ADC_CCR_ADCPRE_DIV2 (1 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 2 */
|
||||
# define ADC_CCR_ADCPRE_DIV4 (2 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 4 */
|
||||
/* 11: Reserved */
|
||||
/* Bits 22-18: Reserved, must be kept at reset value */
|
||||
# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
|
||||
/* Bits 31-24: Reserved, must be kept at reset value */
|
||||
#endif
|
||||
|
||||
/* Data register for dual and triple modes (32-bit data with no named fields) */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_H */
|
||||
|
||||
627
arch/arm/src/stm32/chip/stm32_adc_v1.h
Normal file
627
arch/arm/src/stm32/chip/stm32_adc_v1.h
Normal file
@ -0,0 +1,627 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_adc_ipv1.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* This is implementation for STM32 ADC IPv1 - F1, F2, F37x, F4, F7.
|
||||
* NOTE: L1 use modified IPv1 (look at chip/stm32_adc_v1l1.h).
|
||||
*/
|
||||
|
||||
#define HAVE_IP_ADC_V1
|
||||
#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */
|
||||
#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */
|
||||
#undef HAVE_ADC_POWERDOWN /* No ADC power down */
|
||||
|
||||
/* F1 and F37x have basic version of ADC hardware
|
||||
* - no common ADC registers
|
||||
* - ADCs are not coupled in single ADC block (no common ADC base address)
|
||||
* - no configurable resolution
|
||||
* - no overrun
|
||||
* - ...
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1_BASIC)
|
||||
# define HAVE_BASIC_ADC
|
||||
#else
|
||||
# undef HAVE_BASIC_ADC
|
||||
#endif
|
||||
|
||||
/* VBAT channel support only if no basic ADC */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define HAVE_ADC_VBAT
|
||||
#else
|
||||
# undef HAVE_ADC_VBAT
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* For the basic ADC IPv1, the ADCx_BASE definitions are defined in chip/stm32xxx_memorymap.h files */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define STM32_ADC1_OFFSET 0x0000
|
||||
# define STM32_ADC2_OFFSET 0x0100
|
||||
# define STM32_ADC3_OFFSET 0x0200
|
||||
# define STM32_ADC_CMN_OFFSET 0x0300
|
||||
|
||||
# define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC_BASE) /* ADC1 ADC */
|
||||
# define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC_BASE) /* ADC2 ADC */
|
||||
# define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC_BASE) /* ADC3 ADC */
|
||||
# define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET+STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */
|
||||
#endif
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
|
||||
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
|
||||
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
|
||||
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
|
||||
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
|
||||
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
|
||||
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
|
||||
# define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#if STM32_NADC > 0
|
||||
# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 1
|
||||
# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 2
|
||||
# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
# define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* ADC status register */
|
||||
|
||||
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
|
||||
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
|
||||
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
|
||||
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
|
||||
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
|
||||
#endif
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
|
||||
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
|
||||
|
||||
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
|
||||
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
|
||||
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
|
||||
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
|
||||
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
|
||||
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
|
||||
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
|
||||
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
|
||||
|
||||
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
|
||||
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
|
||||
|
||||
#ifdef HAVE_BASIC_ADC
|
||||
# define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */
|
||||
# define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT)
|
||||
# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */
|
||||
# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */
|
||||
# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */
|
||||
# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */
|
||||
# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */
|
||||
# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */
|
||||
# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */
|
||||
# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */
|
||||
#endif
|
||||
|
||||
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
|
||||
# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
|
||||
# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */
|
||||
# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
|
||||
# define ADC_CR1_RESERVED (0xfb3f0000)
|
||||
#endif
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
|
||||
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
|
||||
#ifdef HAVE_BASIC_ADC
|
||||
# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
|
||||
# define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */
|
||||
#endif
|
||||
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
|
||||
# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
|
||||
#endif
|
||||
|
||||
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
/* Bits 12-15: Reserved */
|
||||
# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
|
||||
# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
|
||||
# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */
|
||||
# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */
|
||||
# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
|
||||
# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
|
||||
# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
|
||||
# define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
|
||||
/* Bit 23: Reserved, must be kept at reset value. */
|
||||
# define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
|
||||
# define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
|
||||
# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
|
||||
# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
|
||||
# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
|
||||
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
|
||||
# define ADC_CR2_RESERVED (0x8080f0fc)
|
||||
#else /* HAVE_BASIC_ADC */
|
||||
# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */
|
||||
# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# if defined(CONFIG_STM32_STM32F37XX)
|
||||
# define ADC_CR2_JEXTSEL_T19CC1 (0 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_T19CC2 (1 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# else
|
||||
# define ADC_CR2_JEXTSEL_T1TRGO (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */
|
||||
# endif
|
||||
# define ADC_CR2_JEXTSEL_T2TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */
|
||||
# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */
|
||||
# define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */
|
||||
# define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */
|
||||
# define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# if defined(CONFIG_STM32_STM32F37XX)
|
||||
# define ADC_CR2_EXTSEL_T19TRGO (0 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_T19CC3 (1 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_T19CC4 (2 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# else
|
||||
# define ADC_CR2_EXTSEL_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */
|
||||
# endif
|
||||
# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */
|
||||
# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */
|
||||
# define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */
|
||||
# define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */
|
||||
# define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */
|
||||
# define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */
|
||||
#endif
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define ADC_SMPR_3 0 /* 000: 3 cycles */
|
||||
# define ADC_SMPR_15 1 /* 001: 15 cycles */
|
||||
# define ADC_SMPR_28 2 /* 010: 28 cycles */
|
||||
# define ADC_SMPR_56 3 /* 011: 56 cycles */
|
||||
# define ADC_SMPR_84 4 /* 100: 84 cycles */
|
||||
# define ADC_SMPR_112 5 /* 101: 112 cycles */
|
||||
# define ADC_SMPR_144 6 /* 110: 144 cycles */
|
||||
# define ADC_SMPR_480 7 /* 111: 480 cycles */
|
||||
#else
|
||||
# define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
|
||||
# define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */
|
||||
# define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */
|
||||
# define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */
|
||||
# define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */
|
||||
# define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */
|
||||
# define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */
|
||||
# define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */
|
||||
#endif
|
||||
|
||||
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
|
||||
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
|
||||
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
|
||||
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
|
||||
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
|
||||
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
|
||||
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
|
||||
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT)
|
||||
#endif
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
|
||||
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
|
||||
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
|
||||
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
|
||||
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
|
||||
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
|
||||
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
|
||||
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
|
||||
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
|
||||
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
|
||||
|
||||
/* ADC injected channel data offset register 1-4 */
|
||||
|
||||
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
|
||||
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
|
||||
|
||||
/* ADC watchdog high threshold register */
|
||||
|
||||
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
|
||||
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
|
||||
|
||||
/* ADC watchdog low threshold register */
|
||||
|
||||
#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */
|
||||
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
|
||||
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
|
||||
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
|
||||
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
|
||||
#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
|
||||
#define ADC_SQR1_RESERVED (0xff000000)
|
||||
#define ADC_SQR1_FIRST (13)
|
||||
#define ADC_SQR1_LAST (16)
|
||||
#define ADC_SQR1_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
|
||||
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
|
||||
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
|
||||
#define ADC_SQR2_RESERVED (0xc0000000)
|
||||
#define ADC_SQR2_FIRST (7)
|
||||
#define ADC_SQR2_LAST (12)
|
||||
#define ADC_SQR2_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
|
||||
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
|
||||
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
|
||||
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
|
||||
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
|
||||
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
|
||||
#define ADC_SQR3_RESERVED (0xc0000000)
|
||||
#define ADC_SQR3_FIRST (1)
|
||||
#define ADC_SQR3_LAST (6)
|
||||
#define ADC_SQR3_SQ_OFFSET (0)
|
||||
|
||||
/* Offset between SQ bits */
|
||||
|
||||
#define ADC_SQ_OFFSET (5)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
|
||||
/* ADC injected data register 1-4 */
|
||||
|
||||
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
|
||||
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
|
||||
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
|
||||
#ifdef HAVE_BASIC_ADC
|
||||
# define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */
|
||||
# define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Common status register */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
|
||||
# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
|
||||
# define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
|
||||
# define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
|
||||
# define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
|
||||
# define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
|
||||
/* Bits 6-7: Reserved, must be kept at reset value. */
|
||||
|
||||
# define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
|
||||
# define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
|
||||
# define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
|
||||
# define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
|
||||
# define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
|
||||
# define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
|
||||
/* Bits 14-15: Reserved, must be kept at reset value. */
|
||||
# define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
|
||||
# define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
|
||||
# define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
|
||||
# define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
|
||||
# define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
|
||||
# define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
|
||||
/* Bits 22-31: Reserved, must be kept at reset value. */
|
||||
#endif
|
||||
|
||||
/* Common control register */
|
||||
|
||||
#ifndef HAVE_BASIC_ADC
|
||||
# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
|
||||
# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
|
||||
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */
|
||||
/* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
|
||||
# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */
|
||||
/* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
|
||||
# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
|
||||
/* Bits 5-7: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
|
||||
# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
|
||||
# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
|
||||
/* Bit 12 Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
|
||||
|
||||
# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */
|
||||
# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT)
|
||||
# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
|
||||
# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
|
||||
# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
|
||||
# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
|
||||
|
||||
# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
|
||||
# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
|
||||
# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
|
||||
# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
|
||||
# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
|
||||
# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
|
||||
/* Bits 18-21: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_VBATEN (1 << 22) /* Bit 22: VBAT enable */
|
||||
# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
|
||||
/* Bits 24-31 Reserved, must be kept at reset value. */
|
||||
#endif
|
||||
|
||||
/* Data register for dual and triple modes (32-bit data with no named fields) */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1_H */
|
||||
563
arch/arm/src/stm32/chip/stm32_adc_v1l1.h
Normal file
563
arch/arm/src/stm32/chip/stm32_adc_v1l1.h
Normal file
@ -0,0 +1,563 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_adc_ipv1l1.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1L1_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1L1_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* This is implementation for STM32 ADC IPv1 modified for L1 */
|
||||
|
||||
#define HAVE_IP_ADC_V1
|
||||
#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */
|
||||
#undef HAVE_BASIC_ADC /* No basic ADC */
|
||||
#undef HAVE_ADC_VBAT /* No VBAT channel */
|
||||
|
||||
/* Some families use HSI as clock-source for the ADC (L0, L1).
|
||||
* NOTE: F0 use dedicated HSI14 clock which does not belong here.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define HAVE_ADC_CLOCK_HSI
|
||||
#endif
|
||||
|
||||
/* Power down functions for ADC (L1) */
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
# define HAVE_ADC_POWERDOWN
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
#define STM32_ADC1_OFFSET 0x0000
|
||||
#define STM32_ADC2_OFFSET 0x0100
|
||||
#define STM32_ADC3_OFFSET 0x0200
|
||||
#define STM32_ADC_CMN_OFFSET 0x0300
|
||||
|
||||
#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC_BASE) /* ADC1 ADC */
|
||||
#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC_BASE) /* ADC2 ADC */
|
||||
#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC_BASE) /* ADC3 ADC */
|
||||
#define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET+STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
|
||||
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
|
||||
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
|
||||
#define STM32_ADC_SMPR3_OFFSET 0x0014 /* ADC sample time register 3 (32-bit) */
|
||||
#define STM32_ADC_JOFR1_OFFSET 0x0018 /* ADC injected channel data offset register 1 (32-bit) */
|
||||
#define STM32_ADC_JOFR2_OFFSET 0x001c /* ADC injected channel data offset register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR3_OFFSET 0x0020 /* ADC injected channel data offset register 3 (32-bit) */
|
||||
#define STM32_ADC_JOFR4_OFFSET 0x0024 /* ADC injected channel data offset register 4 (32-bit) */
|
||||
#define STM32_ADC_HTR_OFFSET 0x0028 /* ADC watchdog high threshold register (32-bit) */
|
||||
#define STM32_ADC_LTR_OFFSET 0x002c /* ADC watchdog low threshold register (32-bit) */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 (32-bit) */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 (32-bit) */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 (32-bit) */
|
||||
#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 (32-bit) */
|
||||
#define STM32_ADC_SQR5_OFFSET 0x0040 /* ADC regular sequence register 5 (32-bit) */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x0044 /* ADC injected sequence register (32-bit) */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x004c /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0050 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x0054 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_DR_OFFSET 0x0058 /* ADC regular data register (32-bit) */
|
||||
#define STM32_ADC_SMPR0_OFFSET 0X005c /* ADC sample time register 3 (32-bit) */
|
||||
|
||||
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#if STM32_NADC > 0
|
||||
# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC1_SMPR3 (STM32_ADC1_BASE+STM32_ADC_SMPR3_OFFSET)
|
||||
# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
# define STM32_ADC1_SQR5 (STM32_ADC1_BASE+STM32_ADC_SQR5_OFFSET)
|
||||
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
# define STM32_ADC1_SMPR0 (STM32_ADC1_BASE+STM32_ADC_SMPR0_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 1
|
||||
# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 2
|
||||
# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* ADC status register */
|
||||
|
||||
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
|
||||
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
|
||||
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
|
||||
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
|
||||
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
|
||||
#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
|
||||
#define ADC_SR_ADONS (1 << 6) /* Bit 6 : ADC ON status. Set and cleared by HW */
|
||||
#define ADC_SR_RCNR (1 << 8) /* Bit 8 : Regular channel not ready. Set and cleared by HW */
|
||||
#define ADC_SR_JCNR (1 << 9) /* Bit 9 : Injected channel not ready. Set and cleared by HW */
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
|
||||
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
|
||||
|
||||
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
|
||||
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
|
||||
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
|
||||
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
|
||||
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
|
||||
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
|
||||
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
|
||||
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
|
||||
|
||||
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
|
||||
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
|
||||
|
||||
#define ADC_CR1_PDD (1 << 16) /* Bit 16 : Power down during the delay phase. This bit must be written only when ADON=0 */
|
||||
#define ADC_CR1_PDI (1 << 17) /* Bit 17 : Power down during the idle phase. This bit must
|
||||
* be written only when ADON=0 */
|
||||
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
|
||||
|
||||
#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
|
||||
#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
|
||||
# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 12 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */
|
||||
# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 7 ADCCLK cycles */
|
||||
#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
|
||||
#define ADC_CR1_RESERVED (0xfb3f0000)
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
|
||||
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
|
||||
#define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no
|
||||
* conversion is on going. This bit is available in high and medium+
|
||||
* density devices only.
|
||||
*/
|
||||
#define ADC_CR2_DELS_SHIFT (4) /* Bits 2-0: Delay selection */
|
||||
#define ADC_CR2_DELS_MASK (0x07 << ADC_CR2_DELS_SHIFT)
|
||||
#define ADC_CR2_DELS_NODEL (0x0 << ADC_CR2_DELS_SHIFT) /* No delay */
|
||||
#define ADC_CR2_DELS_TILLRD (0x01 << ADC_CR2_DELS_SHIFT) /* Until the converted data have been read */
|
||||
#define ADC_CR2_DELS_APB7 (0x02 << ADC_CR2_DELS_SHIFT) /* 7 APB clock cycles after the end of conversion */
|
||||
#define ADC_CR2_DELS_APB15 (0x03 << ADC_CR2_DELS_SHIFT) /* 15 APB clock cycles after the end of conversion */
|
||||
#define ADC_CR2_DELS_APB31 (0x04 << ADC_CR2_DELS_SHIFT) /* 31 APB clock cycles after the end of conversion */
|
||||
#define ADC_CR2_DELS_APB63 (0x05 << ADC_CR2_DELS_SHIFT) /* 63 APB clock cycles after the end of conversion */
|
||||
#define ADC_CR2_DELS_APB127 (0x06 << ADC_CR2_DELS_SHIFT) /* 127 APB clock cycles after the end of conversion */
|
||||
#define ADC_CR2_DELS_APB255 (0x07 << ADC_CR2_DELS_SHIFT) /* 255 APB clock cycles after the end of conversion */
|
||||
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
|
||||
#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
|
||||
#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
|
||||
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
|
||||
/* Bits 12-15: Reserved */
|
||||
#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
|
||||
#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/
|
||||
# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
|
||||
# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
|
||||
# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */
|
||||
#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
|
||||
#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
|
||||
# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
|
||||
/* Bit 23: Reserved, must be kept at reset value. */
|
||||
#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
|
||||
#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
|
||||
#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
|
||||
#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
|
||||
# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
#define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
|
||||
#define ADC_CR2_RESERVED (0x8080f0fc)
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#define ADC_SMPR_4 0 /* 000: 3 cycles */
|
||||
#define ADC_SMPR_9 1 /* 001: 9 cycles */
|
||||
#define ADC_SMPR_16 2 /* 010: 16 cycles */
|
||||
#define ADC_SMPR_24 3 /* 011: 24 cycles */
|
||||
#define ADC_SMPR_48 4 /* 100: 48 cycles */
|
||||
#define ADC_SMPR_96 5 /* 101: 96 cycles */
|
||||
#define ADC_SMPR_192 6 /* 110: 192 cycles */
|
||||
#define ADC_SMPR_384 7 /* 111: 384 cycles */
|
||||
|
||||
#define ADC_SMPR1_SMP20_SHIFT (0) /* Bits 0-2: Channel 20 Sample time selection */
|
||||
#define ADC_SMPR1_SMP20_MASK (7 << ADC_SMPR1_SMP20_SHIFT)
|
||||
#define ADC_SMPR1_SMP21_SHIFT (3) /* Bits 3-5: Channel 21 Sample time selection */
|
||||
#define ADC_SMPR1_SMP21_MASK (7 << ADC_SMPR1_SMP21_SHIFT)
|
||||
#define ADC_SMPR1_SMP22_SHIFT (6) /* Bits 6-8: Channel 22 Sample time selection */
|
||||
#define ADC_SMPR1_SMP22_MASK (7 << ADC_SMPR1_SMP22_SHIFT)
|
||||
#define ADC_SMPR1_SMP23_SHIFT (9) /* Bits 9-11: Channel 23 Sample time selection */
|
||||
#define ADC_SMPR1_SMP23_MASK (7 << ADC_SMPR1_SMP23_SHIFT)
|
||||
#define ADC_SMPR1_SMP24_SHIFT (12) /* Bits 12-14: Channel 24 Sample time selection */
|
||||
#define ADC_SMPR1_SMP24_MASK (7 << ADC_SMPR1_SMP24_SHIFT)
|
||||
#define ADC_SMPR1_SMP25_SHIFT (15) /* Bits 15-17: Channel 25 Sample time selection */
|
||||
#define ADC_SMPR1_SMP25_MASK (7 << ADC_SMPR1_SMP25_SHIFT)
|
||||
#define ADC_SMPR1_SMP26_SHIFT (18) /* Bits 18-20: Channel 26 Sample time selection */
|
||||
#define ADC_SMPR1_SMP26_MASK (7 << ADC_SMPR1_SMP26_SHIFT)
|
||||
#define ADC_SMPR1_SMP27_SHIFT (21) /* Bits 21-23: Channel 27 Sample time selection */
|
||||
#define ADC_SMPR1_SMP27_MASK (7 << ADC_SMPR1_SMP27_SHIFT)
|
||||
#define ADC_SMPR1_SMP28_SHIFT (24) /* Bits 24-26: Channel 28 Sample time selection */
|
||||
#define ADC_SMPR1_SMP28_MASK (7 << ADC_SMPR1_SMP28_SHIFT)
|
||||
#define ADC_SMPR1_SMP29_SHIFT (27) /* Bits 27-29: Channel 29 Sample time selection */
|
||||
#define ADC_SMPR1_SMP29_MASK (7 << ADC_SMPR1_SMP29_SHIFT)
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT)
|
||||
#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT)
|
||||
#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT)
|
||||
#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT)
|
||||
#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT)
|
||||
#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT)
|
||||
#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT)
|
||||
#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
|
||||
#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT)
|
||||
#define ADC_SMPR2_SMP19_SHIFT (27) /* Bits 27-29: Channel 18 Sample time selection */
|
||||
#define ADC_SMPR2_SMP19_MASK (7 << ADC_SMPR2_SMP19_SHIFT)
|
||||
|
||||
/* ADC sample time register 3 */
|
||||
|
||||
#define ADC_SMPR3_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
#define ADC_SMPR3_SMP0_MASK (7 << ADC_SMPR3_SMP0_SHIFT)
|
||||
#define ADC_SMPR3_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR3_SMP1_MASK (7 << ADC_SMPR3_SMP1_SHIFT)
|
||||
#define ADC_SMPR3_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR3_SMP2_MASK (7 << ADC_SMPR3_SMP2_SHIFT)
|
||||
#define ADC_SMPR3_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR3_SMP3_MASK (7 << ADC_SMPR3_SMP3_SHIFT)
|
||||
#define ADC_SMPR3_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR3_SMP4_MASK (7 << ADC_SMPR3_SMP4_SHIFT)
|
||||
#define ADC_SMPR3_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR3_SMP5_MASK (7 << ADC_SMPR3_SMP5_SHIFT)
|
||||
#define ADC_SMPR3_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR3_SMP6_MASK (7 << ADC_SMPR3_SMP6_SHIFT)
|
||||
#define ADC_SMPR3_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR3_SMP7_MASK (7 << ADC_SMPR3_SMP7_SHIFT)
|
||||
#define ADC_SMPR3_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR3_SMP8_MASK (7 << ADC_SMPR3_SMP8_SHIFT)
|
||||
#define ADC_SMPR3_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR3_SMP9_MASK (7 << ADC_SMPR3_SMP9_SHIFT)
|
||||
|
||||
/* ADC sample time register 0 */
|
||||
|
||||
#define ADC_SMPR0_SMP30_SHIFT (0) /* Bits 2-0: Channel 30 Sample time selection */
|
||||
#define ADC_SMPR0_SMP30_MASK (7 << ADC_SMPR3_SMP30_SHIFT)
|
||||
#define ADC_SMPR0_SMP31_SHIFT (3) /* Bits 5-3: Channel 31 Sample time selection */
|
||||
#define ADC_SMPR0_SMP31_MASK (7 << ADC_SMPR3_SMP31_SHIFT)
|
||||
|
||||
/* ADC injected channel data offset register 1-4 */
|
||||
|
||||
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
|
||||
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
|
||||
|
||||
/* ADC watchdog high threshold register */
|
||||
|
||||
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
|
||||
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
|
||||
|
||||
/* ADC watchdog low threshold register */
|
||||
|
||||
#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */
|
||||
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT)
|
||||
#define ADC_SQR1_SQ26_SHIFT (5) /* Bits 9-5: 26th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ26_MASK (0x1f << ADC_SQR1_SQ26_SHIFT)
|
||||
#define ADC_SQR1_SQ27_SHIFT (10) /* Bits 14-10: 27th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ27_MASK (0x1f << ADC_SQR1_SQ27_SHIFT)
|
||||
#define ADC_SQR1_SQ28_SHIFT (15) /* Bits 19-15: 28th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ28_MASK (0x1f << ADC_SQR1_SQ28_SHIFT)
|
||||
#define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT)
|
||||
#define ADC_SQR1_RESERVED (0xff000000)
|
||||
#define ADC_SQR1_FIRST (25)
|
||||
#define ADC_SQR1_LAST (28)
|
||||
#define ADC_SQR1_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT)
|
||||
#define ADC_SQR2_SQ20_SHIFT (5) /* Bits 9-5: 20th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ20_MASK (0x1f << ADC_SQR2_SQ20_SHIFT)
|
||||
#define ADC_SQR2_SQ21_SHIFT (10) /* Bits 14-10: 21th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ21_MASK (0x1f << ADC_SQR2_SQ21_SHIFT)
|
||||
#define ADC_SQR2_SQ22_SHIFT (15) /* Bits 19-15: 22th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ22_MASK (0x1f << ADC_SQR2_SQ22_SHIFT)
|
||||
#define ADC_SQR2_SQ23_SHIFT (20) /* Bits 24-20: 23th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ23_MASK (0x1f << ADC_SQR2_SQ23_SHIFT )
|
||||
#define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT)
|
||||
#define ADC_SQR2_RESERVED (0xc0000000)
|
||||
#define ADC_SQR2_FIRST (19)
|
||||
#define ADC_SQR2_LAST (24)
|
||||
#define ADC_SQR2_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT)
|
||||
#define ADC_SQR3_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT)
|
||||
#define ADC_SQR3_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ15_MASK (0x1f << ADC_SQR3_SQ15_SHIFT)
|
||||
#define ADC_SQR3_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ16_MASK (0x1f << ADC_SQR3_SQ16_SHIFT)
|
||||
#define ADC_SQR3_SQ17_SHIFT (20) /* Bits 24-20: 17th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ17_MASK (0x1f << ADC_SQR3_SQ17_SHIFT )
|
||||
#define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT)
|
||||
#define ADC_SQR3_RESERVED (0xc0000000)
|
||||
#define ADC_SQR3_FIRST (13)
|
||||
#define ADC_SQR3_LAST (18)
|
||||
#define ADC_SQR3_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 4 */
|
||||
|
||||
#define ADC_SQR4_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ7_MASK (0x1f << ADC_SQR4_SQ7_SHIFT)
|
||||
#define ADC_SQR4_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ8_MASK (0x1f << ADC_SQR4_SQ8_SHIFT)
|
||||
#define ADC_SQR4_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ9_MASK (0x1f << ADC_SQR4_SQ9_SHIFT)
|
||||
#define ADC_SQR4_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ10_MASK (0x1f << ADC_SQR4_SQ10_SHIFT)
|
||||
#define ADC_SQR4_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ11_MASK (0x1f << ADC_SQR4_SQ11_SHIFT )
|
||||
#define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT)
|
||||
#define ADC_SQR4_RESERVED (0xc0000000)
|
||||
#define ADC_SQR4_FIRST (7)
|
||||
#define ADC_SQR4_LAST (12)
|
||||
#define ADC_SQR4_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 5 */
|
||||
|
||||
#define ADC_SQR5_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
#define ADC_SQR5_SQ1_MASK (0x1f << ADC_SQR5_SQ1_SHIFT)
|
||||
#define ADC_SQR5_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR5_SQ2_MASK (0x1f << ADC_SQR5_SQ2_SHIFT)
|
||||
#define ADC_SQR5_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR5_SQ3_MASK (0x1f << ADC_SQR5_SQ3_SHIFT)
|
||||
#define ADC_SQR5_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
#define ADC_SQR5_SQ4_MASK (0x1f << ADC_SQR5_SQ4_SHIFT)
|
||||
#define ADC_SQR5_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
|
||||
#define ADC_SQR5_SQ5_MASK (0x1f << ADC_SQR5_SQ5_SHIFT )
|
||||
#define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
|
||||
#define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT)
|
||||
#define ADC_SQR5_RESERVED (0xc0000000)
|
||||
#define ADC_SQR5_FIRST (1)
|
||||
#define ADC_SQR5_LAST (6)
|
||||
#define ADC_SQR5_SQ_OFFSET (0)
|
||||
|
||||
/* Offset between SQ bits */
|
||||
|
||||
#define ADC_SQ_OFFSET (5)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
|
||||
/* ADC injected data register 1-4 */
|
||||
|
||||
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
|
||||
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
|
||||
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
|
||||
|
||||
/* Common status register */
|
||||
|
||||
#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
|
||||
#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
|
||||
#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
|
||||
#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
|
||||
#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
|
||||
#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
|
||||
/* Bits 6-7: Reserved, must be kept at reset value. */
|
||||
#define ADC_CSR_ADONS1 (1 << 6) /* Bit 6: ADON Status of ADC1. This bit is a copy of the ADONS bit in the ADC_SR register. */
|
||||
|
||||
/* Common control register */
|
||||
|
||||
/* Bits 15-0: Reserved, must be kept at reset value */
|
||||
#define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
|
||||
#define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
|
||||
# define ADC_CCR_ADCPRE_DIV1 (0 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 1 */
|
||||
# define ADC_CCR_ADCPRE_DIV2 (1 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 2 */
|
||||
# define ADC_CCR_ADCPRE_DIV4 (2 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 4 */
|
||||
/* 11: Reserved */
|
||||
/* Bits 22-18: Reserved, must be kept at reset value */
|
||||
#define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
|
||||
/* Bits 31-24: Reserved, must be kept at reset value */
|
||||
|
||||
/* Data register for dual and triple modes (32-bit data with no named fields) */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1L1_H */
|
||||
@ -1,9 +1,9 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f33xxx_adc.h
|
||||
* arch/arm/src/stm32/chip/stm32_adc_ipv2.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -34,8 +34,8 @@
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_ADC_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_ADC_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV2_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV2_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
@ -45,24 +45,65 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), H7, L0, L4, L4+ */
|
||||
|
||||
#define HAVE_IP_ADC_V2
|
||||
#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */
|
||||
#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */
|
||||
#undef HAVE_ADC_POWERDOWN /* No ADC power down */
|
||||
#define HAVE_ADC_VBAT /* VBAT channel support */
|
||||
|
||||
/* F0 and L0 have basic version of ADC hardware (not present here for now):
|
||||
* - channel selection register (CHSELR)
|
||||
* - sampling time configuration common for all channels
|
||||
* - one TR register
|
||||
* - no SQR registers
|
||||
* - ...
|
||||
*
|
||||
* TODO: definitions for basic STM32 ADC IPv2 (F0, L0)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_V2_BASIC
|
||||
# define HAVE_BASIC_ADC
|
||||
# error TODO
|
||||
#else
|
||||
# undef HAVE_BASIC_ADC
|
||||
#endif
|
||||
|
||||
/* F30X and F33x dont have CFGR2 register */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
# undef HAVE_ADC_CFGR2
|
||||
#else
|
||||
# define HAVE_ADC_CFGR2
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
#define STM32_ADC1_OFFSET 0x0000
|
||||
#define STM32_ADC2_OFFSET 0x0100
|
||||
#define STM32_ADC12_CMN_OFFSET 0x0300
|
||||
#define STM32_ADC3_OFFSET 0x0000
|
||||
#define STM32_ADC4_OFFSET 0x0100
|
||||
#define STM32_ADCCMN_OFFSET 0x0300
|
||||
|
||||
#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
|
||||
#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
|
||||
#define STM32_ADC12_CMN_BASE (STM32_ADC12_CMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
|
||||
#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */
|
||||
#define STM32_ADC4_BASE (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */
|
||||
#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
|
||||
#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
|
||||
#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
|
||||
#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */
|
||||
#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */
|
||||
#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */
|
||||
#ifdef HAVE_ADC_CFGR2
|
||||
# define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
|
||||
#endif
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */
|
||||
#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */
|
||||
@ -95,65 +136,149 @@
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
#if STM32_NADC > 0
|
||||
# define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET)
|
||||
# define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET)
|
||||
# define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET)
|
||||
# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE+STM32_ADC_CFGR1_OFFSET)
|
||||
# ifdef HAVE_ADC_CFGR2
|
||||
# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
# endif
|
||||
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET)
|
||||
# define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET)
|
||||
# define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET)
|
||||
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
# define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
# define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
# define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
# define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
#if STM32_NADC > 1
|
||||
# define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET)
|
||||
# define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET)
|
||||
# define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET)
|
||||
# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE+STM32_ADC_CFGR1_OFFSET)
|
||||
# ifdef HAVE_ADC_CFGR2
|
||||
# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
# endif
|
||||
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET)
|
||||
# define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET)
|
||||
# define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET)
|
||||
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
# define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
# define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
# define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
# define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_ADC12_CSR (STM32_ADC12_CMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
#define STM32_ADC12_CCR (STM32_ADC12_CMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
#define STM32_ADC12_CDR (STM32_ADC12_CMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
#if STM32_NADC > 2
|
||||
# define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET)
|
||||
# define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET)
|
||||
# define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET)
|
||||
# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE+STM32_ADC_CFGR1_OFFSET)
|
||||
# ifdef HAVE_ADC_CFGR2
|
||||
# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
# endif
|
||||
# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET)
|
||||
# define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET)
|
||||
# define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET)
|
||||
# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
# define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
# define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
# define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
# define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 3
|
||||
# define STM32_ADC4_ISR (STM32_ADC4_BASE+STM32_ADC_ISR_OFFSET)
|
||||
# define STM32_ADC4_IER (STM32_ADC4_BASE+STM32_ADC_IER_OFFSET)
|
||||
# define STM32_ADC4_CR (STM32_ADC4_BASE+STM32_ADC_CR_OFFSET)
|
||||
# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE+STM32_ADC_CFGR1_OFFSET)
|
||||
# ifdef HAVE_ADC_CFGR2
|
||||
# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
# endif
|
||||
# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC4_TR1 (STM32_ADC4_BASE+STM32_ADC_TR1_OFFSET)
|
||||
# define STM32_ADC4_TR2 (STM32_ADC4_BASE+STM32_ADC_TR2_OFFSET)
|
||||
# define STM32_ADC4_TR3 (STM32_ADC4_BASE+STM32_ADC_TR3_OFFSET)
|
||||
# define STM32_ADC4_SQR1 (STM32_ADC4_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC4_SQR2 (STM32_ADC4_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC4_SQR3 (STM32_ADC4_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC4_SQR4 (STM32_ADC4_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
# define STM32_ADC4_DR (STM32_ADC4_BASE+STM32_ADC_DR_OFFSET)
|
||||
# define STM32_ADC4_JSQR (STM32_ADC4_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC4_OFR1 (STM32_ADC4_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
# define STM32_ADC4_OFR2 (STM32_ADC4_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
# define STM32_ADC4_OFR3 (STM32_ADC4_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
# define STM32_ADC4_OFR4 (STM32_ADC4_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
# define STM32_ADC4_JDR1 (STM32_ADC4_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC4_JDR2 (STM32_ADC4_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC4_JDR3 (STM32_ADC4_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC4_JDR4 (STM32_ADC4_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
# define STM32_ADC4_CALFACT (STM32_ADC4_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 0
|
||||
# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 2
|
||||
# define STM32_ADC34_CSR (STM32_ADC34CMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
# define STM32_ADC34_CCR (STM32_ADC34CMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
|
||||
@ -186,57 +311,92 @@
|
||||
#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */
|
||||
#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */
|
||||
|
||||
/* ADC configuration register */
|
||||
/* ADC configuration register 1 */
|
||||
|
||||
#define ADC_CFGR_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */
|
||||
#define ADC_CFGR_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */
|
||||
#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */
|
||||
#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT)
|
||||
# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK cycles */
|
||||
# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 13 ADCCLK cycles */
|
||||
# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 11 ADCCLK cycles */
|
||||
# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 9 ADCCLK cycles */
|
||||
#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */
|
||||
#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
|
||||
#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1CC1 (0 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1CC2 (1 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T2CC2 (3 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T3TRGO (4 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
/* 0101: Reserved */
|
||||
# define ADC12_CFGR_EXTSEL_EXTI11 (6 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */
|
||||
# define ADC12_CFGR_EXTSEL_HRT1TRG1 (7 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: HRTIM1 ADCTRG1 event */
|
||||
# define ADC12_CFGR_EXTSEL_HRT1TRG3 (8 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: HRTIM1 ADCTRG3 event */
|
||||
# define ADC12_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1TRGO2 (10 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T2TRGO (11 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */
|
||||
#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */
|
||||
#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */
|
||||
#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT)
|
||||
# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK cycles */
|
||||
# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK cycles */
|
||||
# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK cycles */
|
||||
# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK cycles */
|
||||
#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */
|
||||
#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
|
||||
#define ADC_CFGR1_EXTSEL_MASK (15 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
#if defined(CONFIG_STM32_STM32F33XX)
|
||||
# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
/* 0101: Reserved */
|
||||
# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) /* 0110: EXTI line 11 */
|
||||
# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (7 << ADC_CFGR1_EXTSEL_SHIFT) /* 0111: HRTIM1 ADCTRG1 event */
|
||||
# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (8 << ADC_CFGR1_EXTSEL_SHIFT) /* 1000: HRTIM1 ADCTRG3 event */
|
||||
# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
/* 1100: Reserved */
|
||||
# define ADC12_CFGR_EXTSEL_T6TRGO (13 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T3CC4 (15 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
|
||||
#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT)
|
||||
# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
|
||||
# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */
|
||||
# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */
|
||||
# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */
|
||||
#define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
|
||||
#define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
|
||||
#define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */
|
||||
#define ADC_CFGR_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
|
||||
#define ADC_CFGR_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */
|
||||
#define ADC_CFGR_DISCNUM_MASK (7 << ADC_CFGR_DISCNUM_SHIFT)
|
||||
# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT) /* n = 1..8 channels */
|
||||
#define ADC_CFGR_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */
|
||||
#define ADC_CFGR_JQM (1 << 21) /* Bit 21: JSQR queue mode */
|
||||
#define ADC_CFGR_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
|
||||
#define ADC_CFGR_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */
|
||||
#define ADC_CFGR_JAWD1EN (1 << 22) /* Bit 22: Analog watchdog enable 1 injected channels */
|
||||
#define ADC_CFGR_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */
|
||||
#define ADC_CFGR_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */
|
||||
#define ADC_CFGR_AWD1CH_MASK (31 << ADC_CFGR_AWD1CH_SHIFT)
|
||||
# define ADC_CFGR_AWD1CH_DISABLED (0 << ADC_CFGR_AWD1CH_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T8TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T20TRGO (5 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T2TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T3TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T7TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT)
|
||||
#else
|
||||
# error TODO EXTSEL
|
||||
#endif
|
||||
#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
|
||||
#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT)
|
||||
# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */
|
||||
# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */
|
||||
# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */
|
||||
# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */
|
||||
#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
|
||||
#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
|
||||
#define ADC_CFGR1_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */
|
||||
#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
|
||||
#define ADC_CFGR1_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */
|
||||
#define ADC_CFGR1_DISCNUM_MASK (7 << ADC_CFGR1_DISCNUM_SHIFT)
|
||||
# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << ADC_CFGR1_DISCNUM_SHIFT) /* n = 1..8 channels */
|
||||
#define ADC_CFGR1_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */
|
||||
#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */
|
||||
#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
|
||||
#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */
|
||||
#define ADC_CFGR1_JAWD1EN (1 << 22) /* Bit 22: Analog watchdog enable 1 injected channels */
|
||||
#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */
|
||||
#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */
|
||||
#define ADC_CFGR1_AWD1CH_MASK (31 << ADC_CFGR1_AWD1CH_SHIFT)
|
||||
# define ADC_CFGR1_AWD1CH_DISABLED (0 << ADC_CFGR1_AWD1CH_SHIFT)
|
||||
|
||||
/* TODO: ADC configuration register 2 */
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
@ -388,6 +548,7 @@
|
||||
# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */
|
||||
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */
|
||||
#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
#if defined(CONFIG_STM32_STM32F33XX)
|
||||
# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
@ -404,6 +565,38 @@
|
||||
# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
#else
|
||||
# error TODO JEXTSEL
|
||||
#endif
|
||||
# define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */
|
||||
# define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT)
|
||||
# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
@ -539,4 +732,4 @@
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_ADC_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV2_H */
|
||||
@ -59,8 +59,12 @@
|
||||
- 4-bit SMS in SMCR register
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_TIMERS_V2
|
||||
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2)
|
||||
# define HAVE_IP_TIMERS_V2
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1)
|
||||
# define HAVE_IP_TIMERS_V1
|
||||
#else
|
||||
# error "STM32 TIMER IP version not specified"
|
||||
#endif
|
||||
|
||||
/* TIM16 has OR register (F3/L4) */
|
||||
|
||||
@ -156,10 +156,6 @@
|
||||
#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */
|
||||
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */
|
||||
#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1-3 */
|
||||
# define STM32_ADC1_BASE 0x40012000 /* ADC1 */
|
||||
# define STM32_ADC2_BASE 0x40012100 /* ADC2 */
|
||||
# define STM32_ADC3_BASE 0x40012200 /* ADC3 */
|
||||
# define STM32_ADCCMN_BASE 0x40012300 /* Common */
|
||||
#define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDIO */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
|
||||
#define STM32_SYSCFG_BASE 0x40013800 /* 0x40013800-0x40013bff: SYSCFG */
|
||||
|
||||
@ -1,620 +0,0 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f30xxx_adc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_ADC_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_ADC_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
/* Register Offsets for Each ADC (ADC1, 2, 3, and 4). At offset 0x0000 for master and offset 0x0100
|
||||
* for slave.
|
||||
*/
|
||||
|
||||
#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
|
||||
#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
|
||||
#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */
|
||||
#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */
|
||||
#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */
|
||||
#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */
|
||||
#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */
|
||||
#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */
|
||||
#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */
|
||||
#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */
|
||||
#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */
|
||||
#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */
|
||||
#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC data offset register 4 */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */
|
||||
#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */
|
||||
#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */
|
||||
#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */
|
||||
#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */
|
||||
|
||||
/* Master and Slave ADC Common Registers */
|
||||
|
||||
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
|
||||
#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32_ADC12_CSR (STM32_ADC12_BASE+STM32_ADC_CSR_OFFSET)
|
||||
#define STM32_ADC12_CCR (STM32_ADC12_BASE+STM32_ADC_CCR_OFFSET)
|
||||
#define STM32_ADC12_CDR (STM32_ADC12_BASE+STM32_ADC_CDR_OFFSET)
|
||||
|
||||
#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32_ADC4_ISR (STM32_ADC4_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC4_IER (STM32_ADC4_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC4_CR (STM32_ADC4_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC4_CFGR (STM32_ADC4_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC4_SMPR1 (STM32_ADC4_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC4_SMPR2 (STM32_ADC4_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC4_TR1 (STM32_ADC4_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC4_TR2 (STM32_ADC4_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC4_TR3 (STM32_ADC4_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC4_SQR1 (STM32_ADC4_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC4_SQR2 (STM32_ADC4_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC4_SQR3 (STM32_ADC4_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC4_SQR4 (STM32_ADC4_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC4_DR (STM32_ADC4_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC4_JSQR (STM32_ADC4_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC4_OFR1 (STM32_ADC4_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC4_OFR2 (STM32_ADC4_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC4_OFR3 (STM32_ADC4_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC4_OFR4 (STM32_ADC4_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC4_JDR1 (STM32_ADC4_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC4_JDR2 (STM32_ADC4_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC4_JDR3 (STM32_ADC4_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC4_JDR4 (STM32_ADC4_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC4_AWD2CR (STM32_ADC4_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC4_AWD3CR (STM32_ADC4_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC4_DIFSEL (STM32_ADC4_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC4_CALFACT (STM32_ADC4_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32_ADC34_CSR (STM32_ADC34_BASE+STM32_ADC_CSR_OFFSET)
|
||||
#define STM32_ADC34_CCR (STM32_ADC34_BASE+STM32_ADC_CCR_OFFSET)
|
||||
#define STM32_ADC34_CDR (STM32_ADC34_BASE+STM32_ADC_CDR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
|
||||
|
||||
#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
|
||||
#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */
|
||||
#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */
|
||||
#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */
|
||||
#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */
|
||||
#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */
|
||||
#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */
|
||||
#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */
|
||||
#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */
|
||||
#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */
|
||||
#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */
|
||||
|
||||
/* ADC control register */
|
||||
|
||||
#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */
|
||||
#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */
|
||||
#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */
|
||||
#define ADC_CR_JADSTART (1 << 3) /* Bit 3: ADC start of injected conversion */
|
||||
#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */
|
||||
#define ADC_CR_JADSTP (1 << 5) /* Bit 5: ADC stop of injected conversion command */
|
||||
#define ADC_CR_ADVREGEN_SHIFT (28) /* Bits 28-29: ADC voltage regulator enable */
|
||||
#define ADC_CR_ADVREGEN_MASK (3 << ADC_CR_ADVREGEN_SHIFT)
|
||||
# define ADC_CR_ADVREGEN_INTER (0 << ADC_CR_ADVREGEN_SHIFT) /* Intermediate state */
|
||||
# define ADC_CR_ADVREGEN_ENABLED (1 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator enabled */
|
||||
# define ADC_CR_ADVREGEN_DISABLED (2 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator disabled */
|
||||
#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */
|
||||
#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */
|
||||
|
||||
/* ADC configuration register */
|
||||
|
||||
#define ADC_CFGR_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */
|
||||
#define ADC_CFGR_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */
|
||||
#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */
|
||||
#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT)
|
||||
# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */
|
||||
# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 13 ADCCLK clyes */
|
||||
# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 11 ADCCLK clyes */
|
||||
# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 9 ADCCLK clyes */
|
||||
#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */
|
||||
#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
|
||||
#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1CC1 (0 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1CC2 (1 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T2CC2 (3 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T3TRGO (4 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T4CC4 (5 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_EXTI11 (6 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */
|
||||
# define ADC12_CFGR_EXTSEL_T8TRGO (7 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T2TRGO (11 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T6TRGO (13 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC12_CFGR_EXTSEL_T3CC4 (15 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T3CC1 (0 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T2CC3 (1 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T8CC1 (3 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T8TRGO (4 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T20TRGO (5 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T4CC1 (6 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T2TRGO (7 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T3TRGO (11 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T7TRGO (13 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC34_CFGR_EXTSEL_T2CC1 (15 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
|
||||
#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT)
|
||||
# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
|
||||
# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */
|
||||
# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */
|
||||
# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */
|
||||
#define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
|
||||
#define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
|
||||
#define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */
|
||||
#define ADC_CFGR_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
|
||||
#define ADC_CFGR_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */
|
||||
#define ADC_CFGR_DISCNUM_MASK (7 << ADC_CFGR_DISCNUM_SHIFT)
|
||||
# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT) /* n = 1..8 channels */
|
||||
#define ADC_CFGR_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */
|
||||
#define ADC_CFGR_JQM (1 << 21) /* Bit 21: JSQR queue mode */
|
||||
#define ADC_CFGR_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
|
||||
#define ADC_CFGR_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */
|
||||
#define ADC_CFGR_JAWD1EN (1 << 22) /* Bit 22: Analog watchdog enable 1 injected channels */
|
||||
#define ADC_CFGR_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */
|
||||
#define ADC_CFGR_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */
|
||||
#define ADC_CFGR_AWD1CH_MASK (31 << ADC_CFGR_AWD1CH_SHIFT)
|
||||
# define ADC_CFGR_AWD1CH_DISABLED (0 << ADC_CFGR_AWD1CH_SHIFT)
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
|
||||
#define ADC_SMPR_2p5 1 /* 001: 2.5 cycles */
|
||||
#define ADC_SMPR_4p5 2 /* 010: 4.5 cycles */
|
||||
#define ADC_SMPR_7p5 3 /* 011: 7.5 cycles */
|
||||
#define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */
|
||||
#define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */
|
||||
#define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */
|
||||
#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */
|
||||
|
||||
#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT)
|
||||
#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR1_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT)
|
||||
#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR1_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT)
|
||||
#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR1_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT)
|
||||
#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR1_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT)
|
||||
#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR1_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT)
|
||||
#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR1_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT)
|
||||
#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR1_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT)
|
||||
#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR1_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT)
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT)
|
||||
#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT)
|
||||
#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT)
|
||||
#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT)
|
||||
#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT)
|
||||
#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT)
|
||||
#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT)
|
||||
#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT)
|
||||
#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT)
|
||||
|
||||
/* ADC watchdog threshold register 1 */
|
||||
|
||||
#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */
|
||||
#define ADC_TR1_LT_MASK (0x0fff << ADC_TR1_LT_SHIFT)
|
||||
#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */
|
||||
#define ADC_TR1_HT_MASK (0x0fff << ADC_TR1_HT_SHIFT)
|
||||
|
||||
/* ADC watchdog threshold register 2 */
|
||||
|
||||
#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */
|
||||
#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT)
|
||||
#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */
|
||||
#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT)
|
||||
|
||||
/* ADC watchdog threshold register 3 */
|
||||
|
||||
#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */
|
||||
#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT)
|
||||
#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */
|
||||
#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT)
|
||||
|
||||
/* Offset between SQ bits */
|
||||
|
||||
#define ADC_SQ_OFFSET (6)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
|
||||
#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 13th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT)
|
||||
#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT)
|
||||
#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT)
|
||||
#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT)
|
||||
#define ADC_SQR1_RESERVED (0xe0820830)
|
||||
#define ADC_SQR1_FIRST (1)
|
||||
#define ADC_SQR1_LAST (4)
|
||||
#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET)
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 4-0: 5th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT)
|
||||
#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT)
|
||||
#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
#define ADC_SQR2_RESERVED (0xe0820820)
|
||||
#define ADC_SQR2_FIRST (5)
|
||||
#define ADC_SQR2_LAST (9)
|
||||
#define ADC_SQR2_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 4-0: 10th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT)
|
||||
#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT)
|
||||
#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT)
|
||||
#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT)
|
||||
#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT)
|
||||
#define ADC_SQR3_RESERVED (0xe0820820)
|
||||
#define ADC_SQR3_FIRST (10)
|
||||
#define ADC_SQR3_LAST (14)
|
||||
#define ADC_SQR3_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 4 */
|
||||
|
||||
#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT)
|
||||
#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */
|
||||
#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT)
|
||||
#define ADC_SQR4_RESERVED (0xfffff820)
|
||||
#define ADC_SQR4_FIRST (15)
|
||||
#define ADC_SQR4_LAST (16)
|
||||
#define ADC_SQR4_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_RDATA_SHIFT (0)
|
||||
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */
|
||||
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */
|
||||
#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */
|
||||
# define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT)
|
||||
# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_JSQR_JEXTEN_RISING (1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_JSQR_JEXTEN_FALLING (2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_JSQR_JEXTEN_BOTH (3 << ADC_JSQR_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
#define ADC_JSQR_JSQ1_SHIFT (8) /* Bits 8-12: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK)
|
||||
# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_MASK) /* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ4_SHIFT (26) /* Bits 26-30: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT) /* Channel number 1..18 */
|
||||
|
||||
/* ADC offset register 1, 2, 3, and 4 */
|
||||
|
||||
#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */
|
||||
#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT)
|
||||
# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT)
|
||||
#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */
|
||||
#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT)
|
||||
# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT)
|
||||
#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */
|
||||
|
||||
/* ADC injected data register 1, 2, 3, and 4 */
|
||||
|
||||
#define ADC_JDR_JDATA_SHIFT (0)
|
||||
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
|
||||
|
||||
/* ADC analog watchdog 2 configuration register */
|
||||
|
||||
#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
|
||||
#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT)
|
||||
# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */
|
||||
|
||||
/* ADC analog watchdog 3 configuration register */
|
||||
|
||||
#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
|
||||
#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT)
|
||||
# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */
|
||||
|
||||
/* ADC differential mode selection register 2 */
|
||||
#define ADC_DIFSEL_
|
||||
|
||||
#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */
|
||||
#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT)
|
||||
# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */
|
||||
|
||||
/* ADC calibration factors */
|
||||
|
||||
#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */
|
||||
#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT)
|
||||
#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */
|
||||
#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT)
|
||||
|
||||
/* Common status register */
|
||||
|
||||
#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */
|
||||
#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */
|
||||
#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */
|
||||
#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */
|
||||
#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */
|
||||
#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */
|
||||
#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */
|
||||
#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */
|
||||
#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */
|
||||
#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */
|
||||
#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */
|
||||
#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */
|
||||
#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */
|
||||
#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */
|
||||
#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */
|
||||
#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */
|
||||
#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */
|
||||
#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */
|
||||
#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */
|
||||
#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */
|
||||
#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */
|
||||
#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */
|
||||
|
||||
/* Common control register */
|
||||
|
||||
#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */
|
||||
#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT)
|
||||
# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */
|
||||
# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */
|
||||
# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */
|
||||
# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */
|
||||
# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */
|
||||
# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */
|
||||
# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */
|
||||
# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */
|
||||
#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
|
||||
#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
|
||||
# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */
|
||||
#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */
|
||||
#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
|
||||
#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT)
|
||||
# define ADC_CCR_MDMA_DISABLED (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */
|
||||
# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */
|
||||
# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */
|
||||
#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */
|
||||
#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT)
|
||||
# define ADC_CCR_CKMODE_ASYNCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */
|
||||
# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */
|
||||
# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */
|
||||
# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */
|
||||
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
|
||||
#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
|
||||
#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */
|
||||
|
||||
/* Common regular data register for dual mode */
|
||||
|
||||
#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */
|
||||
#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT)
|
||||
#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */
|
||||
#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_ADC_H */
|
||||
@ -145,12 +145,8 @@
|
||||
|
||||
/* AHB3 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_ADC1_BASE 0x50000000 /* 0x5000004c-0x5000004c: Master ADC1 */
|
||||
#define STM32_ADC2_BASE 0x50000100 /* 0x5000014c-0x500001ff: Slave ADC2 */
|
||||
#define STM32_ADC12_BASE 0x50000300 /* 0x50000300-0x50000308: ADC12 Common */
|
||||
#define STM32_ADC3_BASE 0x50000400 /* 0x5000044c-0x5000044c: Master ADC3 */
|
||||
#define STM32_ADC4_BASE 0x50000500 /* 0x5000054c-0x500005ff: Slave ADC4 */
|
||||
#define STM32_ADC34_BASE 0x50000700 /* 0x50000700-0x50000708: ADC34 Common */
|
||||
#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 Base */
|
||||
#define STM32_ADC34_BASE 0x50000400 /* 0x50000400-0x500007ff: ADC34 Base */
|
||||
|
||||
/* Cortex-M4 Base Addresses *********************************************************/
|
||||
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
|
||||
|
||||
@ -137,7 +137,7 @@
|
||||
|
||||
/* AHB3 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 */
|
||||
#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 Base */
|
||||
|
||||
/* Cortex-M4 Base Addresses *********************************************************/
|
||||
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
|
||||
|
||||
@ -1,321 +0,0 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f30xxx_adc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Studelec SA. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Marc Rechté <mrechte@studelec-sa.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register */
|
||||
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 */
|
||||
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 */
|
||||
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 */
|
||||
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 */
|
||||
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 */
|
||||
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 */
|
||||
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register */
|
||||
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 2 */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 3 */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 4 */
|
||||
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_ADC_SR (STM32_ADC_BASE+STM32_ADC_SR_OFFSET)
|
||||
#define STM32_ADC_CR1 (STM32_ADC_BASE+STM32_ADC_CR1_OFFSET)
|
||||
#define STM32_ADC_CR2 (STM32_ADC_BASE+STM32_ADC_CR2_OFFSET)
|
||||
#define STM32_ADC_SMPR1 (STM32_ADC_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC_SMPR2 (STM32_ADC_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC_JOFR1 (STM32_ADC_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
#define STM32_ADC_JOFR2 (STM32_ADC_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
#define STM32_ADC_JOFR3 (STM32_ADC_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
#define STM32_ADC_JOFR4 (STM32_ADC_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
#define STM32_ADC_HTR (STM32_ADC_BASE+STM32_ADC_HTR_OFFSET)
|
||||
#define STM32_ADC_LTR (STM32_ADC_BASE+STM32_ADC_LTR_OFFSET)
|
||||
#define STM32_ADC_SQR1 (STM32_ADC_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC_SQR2 (STM32_ADC_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC_SQR3 (STM32_ADC_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC_JSQR (STM32_ADC_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC_JDR1 (STM32_ADC_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC_JDR2 (STM32_ADC_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC_JDR3 (STM32_ADC_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC_JDR4 (STM32_ADC_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC_DR (STM32_ADC_BASE+STM32_ADC_DR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
/* ADC status register (SR) */
|
||||
|
||||
#define ADC_SR_AWD (1 << 0) /* Bit 0: Analog wtchdog flag */
|
||||
#define ADC_SR_EOC (1 << 1) /* Bit 1: End of conversion */
|
||||
#define ADC_SR_JEOC (1 << 2) /* Bit 2: Injected channel end of conversion */
|
||||
#define ADC_SR_JSTRT (1 << 3) /* Bit 3: Injected channel start flag */
|
||||
#define ADC_SR_RSTRT (1 << 4) /* Bit 4: Regular channel start flag */
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 0-4: Analog watchdog channel select bits */
|
||||
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
|
||||
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable EOC */
|
||||
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog watchdog interrupt enable */
|
||||
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
|
||||
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
|
||||
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
|
||||
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
|
||||
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
|
||||
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
|
||||
#define ADC_CR1_DISNUM_SHIFT (13) /* Bit 13-15: Discontinuous mode channel count */
|
||||
#define ADC_CR1_DISNUM_MASK (0x7 << ADC_CR1_DISNUM_SHIFT)
|
||||
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D converter ON / OFF */
|
||||
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous conversion */
|
||||
#define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
|
||||
#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset calibration */
|
||||
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct memory access mode */
|
||||
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data alignment */
|
||||
#define ADC_CR2_JEXTSEL_SHIFT (12) /* Bit 12-14: External event select for injected group */
|
||||
#define ADC_CR2_JEXTSEL_MASK (0x7 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_TIM19_CC1 (0 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_TIM19_CC2 (1 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_TIM2_TRGO (2 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_TIM2_CC1 (3 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_TIM3_CC4 (4 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_TIM4_TRGO (5 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
#define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External trigger conversion mode for injected channels */
|
||||
#define ADC_CR2_EXTSEL_SHIFT (17) /* Bit 17-19: External event select for regular group */
|
||||
#define ADC_CR2_EXTSEL_MASK (0x7 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_TIM19_TRGO (0 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_TIM19_CC3 (1 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_TIM19_CC4 (2 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_TIM2_CC2 (3 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_TIM3_TRGO (4 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_TIM4_CC4 (5 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT)
|
||||
#define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External trigger conversion mode for regular channels */
|
||||
#define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start conversion of injected channels */
|
||||
#define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start conversion of regular channels */
|
||||
#define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and V REFINT enable */
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
|
||||
#define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */
|
||||
#define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */
|
||||
#define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */
|
||||
#define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */
|
||||
#define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */
|
||||
#define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */
|
||||
#define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */
|
||||
|
||||
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
|
||||
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
|
||||
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
|
||||
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
|
||||
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
|
||||
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
|
||||
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
|
||||
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT)
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
|
||||
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
|
||||
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
|
||||
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
|
||||
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
|
||||
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
|
||||
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
|
||||
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
|
||||
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
|
||||
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
|
||||
|
||||
/* ADC injected channel data offset register 1, 2, 3, and 4 */
|
||||
|
||||
#define ADC_JOFR_OFFSETX_SHIFT (0) /* Bits 0-11: Data offset for injected channel x */
|
||||
#define ADC_JOFR_OFFSETX_MASK (0x0fff << ADC_JOFR_OFFSETX_SHIFT)
|
||||
|
||||
/* ADC watchdog high threshold register */
|
||||
|
||||
#define ADC_HTR_HT_SHIFT (0) /* Bits 0-11: Analog watchdog high threshold */
|
||||
#define ADC_HTR_HT_MASK (0xfff << ADC_HTR_HT_SHIFT)
|
||||
|
||||
/* ADC watchdog low threshold register */
|
||||
|
||||
#define ADC_LTR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog low threshold */
|
||||
#define ADC_LTR_LT_MASK (0xfff << ADC_LTR_LT_SHIFT)
|
||||
|
||||
/* Offset between SQ bits */
|
||||
|
||||
#define ADC_SQ_OFFSET (5)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 0-4: 13th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
|
||||
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 5-9: 14th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
|
||||
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 10-14: 15th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
|
||||
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 15-19: 16th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
|
||||
#define ADC_SQR1_L_SHIFT (20) /* Bits 20-23: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0xf << ADC_SQR1_L_SHIFT)
|
||||
#define ADC_SQR1_RESERVED (0xff000000)
|
||||
#define ADC_SQR1_FIRST (13)
|
||||
#define ADC_SQR1_LAST (16)
|
||||
#define ADC_SQR1_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 0-4: 7th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 5-9: 8th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 10-14: 9th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 15-19: 10th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
|
||||
#define ADC_SQR2_SQ11_SHIFT (15) /* Bits 20-24: 11th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT)
|
||||
#define ADC_SQR2_SQ12_SHIFT (15) /* Bits 25-29: 12th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
|
||||
#define ADC_SQR2_RESERVED (0xc0000000)
|
||||
#define ADC_SQR2_FIRST (7)
|
||||
#define ADC_SQR2_LAST (12)
|
||||
#define ADC_SQR2_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
|
||||
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
|
||||
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
|
||||
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 15-19: 4th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
|
||||
#define ADC_SQR3_SQ5_SHIFT (15) /* Bits 20-24: 5th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT)
|
||||
#define ADC_SQR3_SQ6_SHIFT (15) /* Bits 25-29: 6th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
|
||||
#define ADC_SQR3_RESERVED (0xc0000000)
|
||||
#define ADC_SQR3_FIRST (1)
|
||||
#define ADC_SQR3_LAST (6)
|
||||
#define ADC_SQR3_SQ_OFFSET (0)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 15-19: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 20-21: Injected sequence length */
|
||||
#define ADC_JSQR_JL_MASK (0x3 << ADC_JSQR_JL_SHIFT)
|
||||
|
||||
/* ADC injected data register 1, 2, 3, and 4 */
|
||||
|
||||
#define ADC_JDR_JDATA_SHIFT (0)
|
||||
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_RDATA_SHIFT (0)
|
||||
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H */
|
||||
@ -117,7 +117,7 @@
|
||||
|
||||
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */
|
||||
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */
|
||||
#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
|
||||
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
|
||||
#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
|
||||
@ -128,8 +128,6 @@
|
||||
#define STM32_SDADC2_BASE 0x40016400 /* 0x40016000-0x400167ff SDADC2 */
|
||||
#define STM32_SDADC3_BASE 0x40016800 /* 0x40016000-0x40016bff SDADC3 */
|
||||
|
||||
#define STM32_ADC1_BASE STM32_ADC_BASE
|
||||
|
||||
/* AHB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
|
||||
|
||||
@ -206,6 +206,7 @@
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers reset */
|
||||
#define RCC_APB2RSTR_ADCRST (1 << 9) /* Bit 9: ADC reset */
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 9) /* for compatibility with ADC driver */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
|
||||
#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */
|
||||
|
||||
@ -158,10 +158,6 @@
|
||||
#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */
|
||||
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */
|
||||
#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1-3 */
|
||||
# define STM32_ADC1_BASE 0x40012000 /* ADC1 */
|
||||
# define STM32_ADC2_BASE 0x40012100 /* ADC2 */
|
||||
# define STM32_ADC3_BASE 0x40012200 /* ADC3 */
|
||||
# define STM32_ADCCMN_BASE 0x40012300 /* Common */
|
||||
#define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDIO */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
|
||||
#define STM32_SPI4_BASE 0x40013400 /* 0x40013000-0x400137ff: SPI4 */
|
||||
|
||||
@ -113,7 +113,6 @@
|
||||
#define STM32_TIM10_BASE 0x40010c00 /* 0x40010c00-0x40010fff TIM10 */
|
||||
#define STM32_TIM11_BASE 0x40011000 /* 0x40011000-0x400113ff TIM11 */
|
||||
#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
|
||||
#define STM32_ADCCMN_BASE (STM32_ADC_BASE+0x300) /* ADC Common */
|
||||
#define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff SDIO */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
|
||||
|
||||
@ -258,6 +258,7 @@
|
||||
#define RCC_APB2RSTR_TIM11RST (1 << 4) /* Bit 4: TIM11 timer reset */
|
||||
/* Bits 5-8: Reserved */
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC1 interface reset */
|
||||
#define RCC_APB2RSTR_ADCRST (1 << 9) /* for compatibility with ADC driver */
|
||||
/* Bit 10: Reserved */
|
||||
#define RCC_APB2RSTR_SDIORST (1 << 11) /* Bit 11: SDIO reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_adc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
@ -46,15 +46,7 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f30xxx_adc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "chip/stm32f33xxx_adc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_adc.h"
|
||||
#else
|
||||
# include "chip/stm32_adc.h"
|
||||
#endif
|
||||
#include "chip/stm32_adc.h"
|
||||
|
||||
#include <nuttx/analog/adc.h>
|
||||
|
||||
@ -564,250 +556,250 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
# define ADC1_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1
|
||||
# define ADC1_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2
|
||||
# define ADC1_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3
|
||||
# define ADC1_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4
|
||||
# define ADC1_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO
|
||||
# define ADC2_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1
|
||||
# define ADC2_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2
|
||||
# define ADC2_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3
|
||||
# define ADC2_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4
|
||||
# define ADC2_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO
|
||||
# define ADC3_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1
|
||||
# define ADC3_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2
|
||||
# define ADC3_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3
|
||||
# define ADC3_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4
|
||||
# define ADC3_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO
|
||||
# define ADC4_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1
|
||||
# define ADC4_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2
|
||||
# define ADC4_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3
|
||||
# define ADC4_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4
|
||||
# define ADC4_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO
|
||||
# define ADC1_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1
|
||||
# define ADC1_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2
|
||||
# define ADC1_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3
|
||||
# define ADC1_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4
|
||||
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO
|
||||
# define ADC2_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1
|
||||
# define ADC2_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2
|
||||
# define ADC2_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3
|
||||
# define ADC2_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4
|
||||
# define ADC2_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO
|
||||
# define ADC3_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1
|
||||
# define ADC3_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2
|
||||
# define ADC3_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3
|
||||
# define ADC3_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4
|
||||
# define ADC3_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO
|
||||
# define ADC4_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1
|
||||
# define ADC4_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2
|
||||
# define ADC4_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3
|
||||
# define ADC4_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4
|
||||
# define ADC4_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO
|
||||
# define ADC1_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1
|
||||
# define ADC1_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2
|
||||
# define ADC1_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3
|
||||
# define ADC1_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4
|
||||
# define ADC1_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO
|
||||
# define ADC2_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1
|
||||
# define ADC2_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2
|
||||
# define ADC2_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3
|
||||
# define ADC2_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4
|
||||
# define ADC2_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO
|
||||
# define ADC3_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1
|
||||
# define ADC3_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2
|
||||
# define ADC3_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3
|
||||
# define ADC3_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4
|
||||
# define ADC3_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO
|
||||
# define ADC4_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1
|
||||
# define ADC4_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2
|
||||
# define ADC4_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3
|
||||
# define ADC4_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4
|
||||
# define ADC4_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO
|
||||
# define ADC1_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1
|
||||
# define ADC1_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2
|
||||
# define ADC1_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3
|
||||
# define ADC1_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4
|
||||
# define ADC1_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO
|
||||
# define ADC2_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1
|
||||
# define ADC2_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2
|
||||
# define ADC2_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3
|
||||
# define ADC2_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4
|
||||
# define ADC2_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO
|
||||
# define ADC3_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1
|
||||
# define ADC3_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2
|
||||
# define ADC3_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3
|
||||
# define ADC3_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4
|
||||
# define ADC3_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO
|
||||
# define ADC4_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1
|
||||
# define ADC4_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2
|
||||
# define ADC4_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3
|
||||
# define ADC4_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4
|
||||
# define ADC4_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO
|
||||
# define ADC1_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1
|
||||
# define ADC1_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2
|
||||
# define ADC1_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3
|
||||
# define ADC1_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4
|
||||
# define ADC1_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO
|
||||
# define ADC2_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1
|
||||
# define ADC2_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2
|
||||
# define ADC2_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3
|
||||
# define ADC2_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4
|
||||
# define ADC2_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO
|
||||
# define ADC3_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1
|
||||
# define ADC3_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2
|
||||
# define ADC3_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3
|
||||
# define ADC3_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4
|
||||
# define ADC3_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO
|
||||
# define ADC4_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1
|
||||
# define ADC4_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2
|
||||
# define ADC4_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3
|
||||
# define ADC4_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4
|
||||
# define ADC4_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO
|
||||
# define ADC1_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1
|
||||
# define ADC1_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2
|
||||
# define ADC1_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3
|
||||
# define ADC1_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4
|
||||
# define ADC1_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO
|
||||
# define ADC2_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1
|
||||
# define ADC2_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2
|
||||
# define ADC2_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3
|
||||
# define ADC2_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4
|
||||
# define ADC2_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO
|
||||
# define ADC3_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1
|
||||
# define ADC3_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2
|
||||
# define ADC3_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3
|
||||
# define ADC3_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4
|
||||
# define ADC3_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO
|
||||
# define ADC4_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1
|
||||
# define ADC4_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2
|
||||
# define ADC4_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3
|
||||
# define ADC4_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4
|
||||
# define ADC4_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO
|
||||
# define ADC1_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1
|
||||
# define ADC1_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2
|
||||
# define ADC1_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3
|
||||
# define ADC1_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4
|
||||
# define ADC1_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO
|
||||
# define ADC2_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1
|
||||
# define ADC2_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2
|
||||
# define ADC2_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3
|
||||
# define ADC2_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4
|
||||
# define ADC2_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO
|
||||
# define ADC3_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1
|
||||
# define ADC3_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2
|
||||
# define ADC3_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3
|
||||
# define ADC3_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4
|
||||
# define ADC3_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO
|
||||
# define ADC4_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1
|
||||
# define ADC4_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2
|
||||
# define ADC4_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3
|
||||
# define ADC4_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4
|
||||
# define ADC4_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO
|
||||
# define ADC1_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1
|
||||
# define ADC1_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2
|
||||
# define ADC1_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3
|
||||
# define ADC1_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4
|
||||
# define ADC1_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO
|
||||
# define ADC2_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1
|
||||
# define ADC2_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2
|
||||
# define ADC2_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3
|
||||
# define ADC2_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4
|
||||
# define ADC2_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO
|
||||
# define ADC3_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1
|
||||
# define ADC3_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2
|
||||
# define ADC3_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3
|
||||
# define ADC3_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4
|
||||
# define ADC3_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO
|
||||
# define ADC4_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1
|
||||
# define ADC4_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2
|
||||
# define ADC4_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3
|
||||
# define ADC4_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4
|
||||
# define ADC4_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO
|
||||
# define ADC1_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1
|
||||
# define ADC1_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2
|
||||
# define ADC1_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3
|
||||
# define ADC1_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4
|
||||
# define ADC1_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO
|
||||
# define ADC2_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1
|
||||
# define ADC2_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2
|
||||
# define ADC2_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3
|
||||
# define ADC2_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4
|
||||
# define ADC2_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO
|
||||
# define ADC3_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1
|
||||
# define ADC3_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2
|
||||
# define ADC3_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3
|
||||
# define ADC3_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4
|
||||
# define ADC3_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO
|
||||
# define ADC4_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1
|
||||
# define ADC4_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2
|
||||
# define ADC4_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3
|
||||
# define ADC4_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4
|
||||
# define ADC4_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO
|
||||
# define ADC1_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1
|
||||
# define ADC1_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2
|
||||
# define ADC1_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3
|
||||
# define ADC1_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4
|
||||
# define ADC1_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO
|
||||
# define ADC2_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1
|
||||
# define ADC2_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2
|
||||
# define ADC2_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3
|
||||
# define ADC2_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4
|
||||
# define ADC2_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO
|
||||
# define ADC3_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1
|
||||
# define ADC3_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2
|
||||
# define ADC3_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3
|
||||
# define ADC3_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4
|
||||
# define ADC3_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO
|
||||
# define ADC4_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1
|
||||
# define ADC4_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2
|
||||
# define ADC4_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3
|
||||
# define ADC4_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4
|
||||
# define ADC4_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO
|
||||
# define ADC1_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1
|
||||
# define ADC1_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2
|
||||
# define ADC1_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3
|
||||
# define ADC1_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4
|
||||
# define ADC1_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO
|
||||
# define ADC2_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1
|
||||
# define ADC2_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2
|
||||
# define ADC2_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3
|
||||
# define ADC2_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4
|
||||
# define ADC2_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO
|
||||
# define ADC3_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1
|
||||
# define ADC3_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2
|
||||
# define ADC3_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3
|
||||
# define ADC3_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4
|
||||
# define ADC3_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO
|
||||
# define ADC4_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1
|
||||
# define ADC4_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2
|
||||
# define ADC4_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3
|
||||
# define ADC4_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4
|
||||
# define ADC4_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO
|
||||
# define ADC1_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1
|
||||
# define ADC1_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2
|
||||
# define ADC1_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3
|
||||
# define ADC1_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4
|
||||
# define ADC1_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO
|
||||
# define ADC2_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1
|
||||
# define ADC2_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2
|
||||
# define ADC2_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3
|
||||
# define ADC2_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4
|
||||
# define ADC2_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO
|
||||
# define ADC3_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1
|
||||
# define ADC3_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2
|
||||
# define ADC3_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3
|
||||
# define ADC3_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4
|
||||
# define ADC3_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO
|
||||
# define ADC4_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1
|
||||
# define ADC4_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2
|
||||
# define ADC4_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3
|
||||
# define ADC4_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4
|
||||
# define ADC4_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO
|
||||
# define ADC1_EXTSEL_HRTTRG1 ADC12_CFGR_EXTSEL_HRT1TRG1
|
||||
# define ADC1_EXTSEL_HRTTRG3 ADC12_CFGR_EXTSEL_HRT1TRG3
|
||||
# define ADC2_EXTSEL_HRTTRG1 ADC12_CFGR_EXTSEL_HRT1TRG1
|
||||
# define ADC2_EXTSEL_HRTTRG3 ADC12_CFGR_EXTSEL_HRT1TRG3
|
||||
# define ADC1_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1
|
||||
# define ADC1_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2
|
||||
# define ADC1_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3
|
||||
# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4
|
||||
# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO
|
||||
# define ADC2_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1
|
||||
# define ADC2_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2
|
||||
# define ADC2_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3
|
||||
# define ADC2_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4
|
||||
# define ADC2_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO
|
||||
# define ADC3_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1
|
||||
# define ADC3_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2
|
||||
# define ADC3_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3
|
||||
# define ADC3_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4
|
||||
# define ADC3_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO
|
||||
# define ADC4_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1
|
||||
# define ADC4_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2
|
||||
# define ADC4_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3
|
||||
# define ADC4_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4
|
||||
# define ADC4_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO
|
||||
# define ADC1_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1
|
||||
# define ADC1_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2
|
||||
# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3
|
||||
# define ADC1_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4
|
||||
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO
|
||||
# define ADC2_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1
|
||||
# define ADC2_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2
|
||||
# define ADC2_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3
|
||||
# define ADC2_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4
|
||||
# define ADC2_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO
|
||||
# define ADC3_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1
|
||||
# define ADC3_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2
|
||||
# define ADC3_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3
|
||||
# define ADC3_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4
|
||||
# define ADC3_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO
|
||||
# define ADC4_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1
|
||||
# define ADC4_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2
|
||||
# define ADC4_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3
|
||||
# define ADC4_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4
|
||||
# define ADC4_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO
|
||||
# define ADC1_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1
|
||||
# define ADC1_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2
|
||||
# define ADC1_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3
|
||||
# define ADC1_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4
|
||||
# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO
|
||||
# define ADC2_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1
|
||||
# define ADC2_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2
|
||||
# define ADC2_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3
|
||||
# define ADC2_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4
|
||||
# define ADC2_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO
|
||||
# define ADC3_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1
|
||||
# define ADC3_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2
|
||||
# define ADC3_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3
|
||||
# define ADC3_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4
|
||||
# define ADC3_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO
|
||||
# define ADC4_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1
|
||||
# define ADC4_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2
|
||||
# define ADC4_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3
|
||||
# define ADC4_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4
|
||||
# define ADC4_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO
|
||||
# define ADC1_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1
|
||||
# define ADC1_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2
|
||||
# define ADC1_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3
|
||||
# define ADC1_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4
|
||||
# define ADC1_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO
|
||||
# define ADC2_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1
|
||||
# define ADC2_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2
|
||||
# define ADC2_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3
|
||||
# define ADC2_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4
|
||||
# define ADC2_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO
|
||||
# define ADC3_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1
|
||||
# define ADC3_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2
|
||||
# define ADC3_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3
|
||||
# define ADC3_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4
|
||||
# define ADC3_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO
|
||||
# define ADC4_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1
|
||||
# define ADC4_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2
|
||||
# define ADC4_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3
|
||||
# define ADC4_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4
|
||||
# define ADC4_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO
|
||||
# define ADC1_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1
|
||||
# define ADC1_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2
|
||||
# define ADC1_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3
|
||||
# define ADC1_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4
|
||||
# define ADC1_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO
|
||||
# define ADC2_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1
|
||||
# define ADC2_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2
|
||||
# define ADC2_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3
|
||||
# define ADC2_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4
|
||||
# define ADC2_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO
|
||||
# define ADC3_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1
|
||||
# define ADC3_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2
|
||||
# define ADC3_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3
|
||||
# define ADC3_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4
|
||||
# define ADC3_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO
|
||||
# define ADC4_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1
|
||||
# define ADC4_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2
|
||||
# define ADC4_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3
|
||||
# define ADC4_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4
|
||||
# define ADC4_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO
|
||||
# define ADC1_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1
|
||||
# define ADC1_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2
|
||||
# define ADC1_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3
|
||||
# define ADC1_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4
|
||||
# define ADC1_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO
|
||||
# define ADC2_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1
|
||||
# define ADC2_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2
|
||||
# define ADC2_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3
|
||||
# define ADC2_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4
|
||||
# define ADC2_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO
|
||||
# define ADC3_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1
|
||||
# define ADC3_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2
|
||||
# define ADC3_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3
|
||||
# define ADC3_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4
|
||||
# define ADC3_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO
|
||||
# define ADC4_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1
|
||||
# define ADC4_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2
|
||||
# define ADC4_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3
|
||||
# define ADC4_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4
|
||||
# define ADC4_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO
|
||||
# define ADC1_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1
|
||||
# define ADC1_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2
|
||||
# define ADC1_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3
|
||||
# define ADC1_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4
|
||||
# define ADC1_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO
|
||||
# define ADC2_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1
|
||||
# define ADC2_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2
|
||||
# define ADC2_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3
|
||||
# define ADC2_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4
|
||||
# define ADC2_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO
|
||||
# define ADC3_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1
|
||||
# define ADC3_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2
|
||||
# define ADC3_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3
|
||||
# define ADC3_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4
|
||||
# define ADC3_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO
|
||||
# define ADC4_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1
|
||||
# define ADC4_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2
|
||||
# define ADC4_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3
|
||||
# define ADC4_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4
|
||||
# define ADC4_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO
|
||||
# define ADC1_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1
|
||||
# define ADC1_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2
|
||||
# define ADC1_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3
|
||||
# define ADC1_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4
|
||||
# define ADC1_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO
|
||||
# define ADC2_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1
|
||||
# define ADC2_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2
|
||||
# define ADC2_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3
|
||||
# define ADC2_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4
|
||||
# define ADC2_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO
|
||||
# define ADC3_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1
|
||||
# define ADC3_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2
|
||||
# define ADC3_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3
|
||||
# define ADC3_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4
|
||||
# define ADC3_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO
|
||||
# define ADC4_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1
|
||||
# define ADC4_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2
|
||||
# define ADC4_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3
|
||||
# define ADC4_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4
|
||||
# define ADC4_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO
|
||||
# define ADC1_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1
|
||||
# define ADC1_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2
|
||||
# define ADC1_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3
|
||||
# define ADC1_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4
|
||||
# define ADC1_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO
|
||||
# define ADC2_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1
|
||||
# define ADC2_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2
|
||||
# define ADC2_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3
|
||||
# define ADC2_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4
|
||||
# define ADC2_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO
|
||||
# define ADC3_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1
|
||||
# define ADC3_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2
|
||||
# define ADC3_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3
|
||||
# define ADC3_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4
|
||||
# define ADC3_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO
|
||||
# define ADC4_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1
|
||||
# define ADC4_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2
|
||||
# define ADC4_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3
|
||||
# define ADC4_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4
|
||||
# define ADC4_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO
|
||||
# define ADC1_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1
|
||||
# define ADC1_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2
|
||||
# define ADC1_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3
|
||||
# define ADC1_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4
|
||||
# define ADC1_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO
|
||||
# define ADC2_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1
|
||||
# define ADC2_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2
|
||||
# define ADC2_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3
|
||||
# define ADC2_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4
|
||||
# define ADC2_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO
|
||||
# define ADC3_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1
|
||||
# define ADC3_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2
|
||||
# define ADC3_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3
|
||||
# define ADC3_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4
|
||||
# define ADC3_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO
|
||||
# define ADC4_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1
|
||||
# define ADC4_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2
|
||||
# define ADC4_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3
|
||||
# define ADC4_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4
|
||||
# define ADC4_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO
|
||||
# define ADC1_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1
|
||||
# define ADC1_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2
|
||||
# define ADC1_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3
|
||||
# define ADC1_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4
|
||||
# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO
|
||||
# define ADC2_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1
|
||||
# define ADC2_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2
|
||||
# define ADC2_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3
|
||||
# define ADC2_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4
|
||||
# define ADC2_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO
|
||||
# define ADC3_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1
|
||||
# define ADC3_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2
|
||||
# define ADC3_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3
|
||||
# define ADC3_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4
|
||||
# define ADC3_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO
|
||||
# define ADC4_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1
|
||||
# define ADC4_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2
|
||||
# define ADC4_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3
|
||||
# define ADC4_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4
|
||||
# define ADC4_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO
|
||||
# define ADC1_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1
|
||||
# define ADC1_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2
|
||||
# define ADC1_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3
|
||||
# define ADC1_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4
|
||||
# define ADC1_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO
|
||||
# define ADC2_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1
|
||||
# define ADC2_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2
|
||||
# define ADC2_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3
|
||||
# define ADC2_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4
|
||||
# define ADC2_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO
|
||||
# define ADC3_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1
|
||||
# define ADC3_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2
|
||||
# define ADC3_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3
|
||||
# define ADC3_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4
|
||||
# define ADC3_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO
|
||||
# define ADC4_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1
|
||||
# define ADC4_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2
|
||||
# define ADC4_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3
|
||||
# define ADC4_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4
|
||||
# define ADC4_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO
|
||||
# define ADC1_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1
|
||||
# define ADC1_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3
|
||||
# define ADC2_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1
|
||||
# define ADC2_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3
|
||||
#else
|
||||
# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
|
||||
# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
|
||||
@ -1856,13 +1848,6 @@
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
enum adc_io_cmds_e
|
||||
{
|
||||
IO_ENABLE_TEMPER_VOLT_CH = 0,
|
||||
};
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are connected
|
||||
* to the same ADC internal channel (ADC1_IN18). Only one conversion, either
|
||||
* temperature sensor or VBAT, must be selected at a time. When both conversion are
|
||||
@ -1871,27 +1856,39 @@ enum adc_io_cmds_e
|
||||
|
||||
enum adc_io_cmds_e
|
||||
{
|
||||
IO_ENABLE_TEMPER_VOLT_CH = 0,
|
||||
#if defined(HAVE_IP_ADC_V1)
|
||||
IO_ENABLE_TEMPER_VOLT_CH,
|
||||
#endif
|
||||
#ifdef HAVE_ADC_VBAT
|
||||
IO_ENABLE_DISABLE_VBAT_CH,
|
||||
};
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32L15XX)
|
||||
enum adc_io_cmds_e
|
||||
{
|
||||
IO_ENABLE_TEMPER_VOLT_CH = 0,
|
||||
IO_ENABLE_DISABLE_PDI,
|
||||
IO_ENABLE_DISABLE_PDD,
|
||||
IO_ENABLE_DISABLE_PDD_PDI,
|
||||
#endif
|
||||
IO_ENABLE_DISABLE_AWDIE,
|
||||
IO_ENABLE_DISABLE_EOCIE,
|
||||
IO_ENABLE_DISABLE_JEOCIE,
|
||||
IO_ENABLE_DISABLE_OVRIE = 7,
|
||||
IO_ENABLE_DISABLE_OVRIE,
|
||||
IO_ENABLE_DISABLE_ALL_INTS,
|
||||
IO_START_CONV,
|
||||
IO_STOP_ADC,
|
||||
IO_START_ADC,
|
||||
IO_START_CONV,
|
||||
#ifdef HAVE_ADC_POWERDOWN
|
||||
IO_ENABLE_DISABLE_PDI,
|
||||
IO_ENABLE_DISABLE_PDD,
|
||||
IO_ENABLE_DISABLE_PDD_PDI
|
||||
#endif
|
||||
};
|
||||
|
||||
/* ADC resolution can be reduced in order to perform faster conversion */
|
||||
|
||||
enum stm32_adc_resoluton_e
|
||||
{
|
||||
ADC_RESOLUTION_12BIT = 0, /* 12 bit */
|
||||
ADC_RESOLUTION_10BIT = 1, /* 10 bit */
|
||||
ADC_RESOLUTION_8BIT = 2, /* 8 bit */
|
||||
ADC_RESOLUTION_6BIT = 3 /* 6 bit */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
|
||||
|
||||
/* Channel and sample time pair */
|
||||
|
||||
typedef struct adc_channel_s
|
||||
@ -1920,27 +1917,16 @@ struct adc_sample_time_s
|
||||
{
|
||||
adc_channel_t *channel; /* Array of channels */
|
||||
uint8_t channels_nbr:5; /* Number of channels in array */
|
||||
bool all_same:1; /* All 32 channels will get the
|
||||
bool all_same:1; /* All channels will get the
|
||||
* same value of the sample time */
|
||||
uint8_t all_ch_sample_time:3; /* Sample time for all 32 channels */
|
||||
uint8_t all_ch_sample_time:3; /* Sample time for all channels */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F33XX
|
||||
|
||||
/* At this moment only for STM32F33XX family */
|
||||
|
||||
/* ADC resolution can be reduced in order to perform faster conversion */
|
||||
|
||||
enum stm32_adc_resoluton_e
|
||||
{
|
||||
ADC_RESOLUTION_12BIT = 0, /* 12 bit, 15 ADCCLK cycles */
|
||||
ADC_RESOLUTION_10BIT = 1, /* 10 bit, 12 ADCCLK cycles */
|
||||
ADC_RESOLUTION_8BIT = 2, /* 8 bit, 10 ADCCLK cycles */
|
||||
ADC_RESOLUTION_6BIT = 3 /* 6 bit, 8 ADCCLK cycles */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_STM32_ADC_NOIRQ
|
||||
|
||||
/* This structure provides the publicly visable representation of the
|
||||
@ -2024,7 +2010,7 @@ struct adc_dev_s;
|
||||
struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
|
||||
int nchannels);
|
||||
|
||||
#ifdef CONFIG_STM32_STM32L15XX
|
||||
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
|
||||
void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev,
|
||||
FAR struct adc_sample_time_s *time_samples);
|
||||
#endif
|
||||
|
||||
@ -60,6 +60,26 @@
|
||||
# error "Unknown STM32 DMA"
|
||||
#endif
|
||||
|
||||
/* Support for STM32 DMA IP version 1 - F0, F1, F3, L0, L1
|
||||
* REVISIT: move this to Kconfig
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define HAVE_IP_DMA_V1
|
||||
#endif
|
||||
|
||||
/* Support for STM32 DMA IP version 2 - F2, F4, F7, H7 */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
# define HAVE_IP_DMA_V2
|
||||
#endif
|
||||
|
||||
#if !defined(HAVE_IP_DMA_V1) && !defined(HAVE_IP_DMA_V2)
|
||||
# error Unknown STM32 DMA IP version
|
||||
#endif
|
||||
|
||||
/* These definitions provide the bit encoding of the 'status' parameter passed to the
|
||||
* DMA callback function (see dma_callback_t).
|
||||
*/
|
||||
|
||||
@ -61,6 +61,10 @@
|
||||
|
||||
/* This module then only compiles if there is at least one enabled timer
|
||||
* intended for use with the PWM upper half driver.
|
||||
*
|
||||
* It implements support for both:
|
||||
* 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1
|
||||
* 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
|
||||
@ -3148,7 +3152,6 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev)
|
||||
|
||||
ret = pwm_soft_break(dev, false);
|
||||
if (ret < 0)
|
||||
|
||||
{
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -119,10 +119,6 @@
|
||||
# define ADC2_HAVE_JEXTSEL
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_ADC_NOIRQ) && defined(ADC_HAVE_DMA)
|
||||
# error "ADC DMA support requires common ADC interrupts"
|
||||
#endif
|
||||
|
||||
/* RCC reset ****************************************************************/
|
||||
|
||||
#define STM32_RCC_RSTR STM32_RCC_AHBRSTR
|
||||
@ -132,12 +128,12 @@
|
||||
|
||||
/* ADC interrupts ***********************************************************/
|
||||
|
||||
#define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET
|
||||
#define ADC_DMAREG_DMA ADC_CFGR_DMAEN
|
||||
#define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET
|
||||
#define ADC_EXTREG_EXTSEL_MASK ADC_CFGR_EXTSEL_MASK
|
||||
#define ADC_EXTREG_EXTEN_MASK ADC_CFGR_EXTEN_MASK
|
||||
#define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR_EXTEN_RISING
|
||||
#define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET
|
||||
#define ADC_DMAREG_DMA ADC_CFGR1_DMAEN
|
||||
#define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET
|
||||
#define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK
|
||||
#define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK
|
||||
#define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING
|
||||
#define STM32_ADC_JEXTREG_OFFSET STM32_ADC_JSQR_OFFSET
|
||||
#define ADC_JEXTREG_JEXTSEL_MASK ADC_JSQR_JEXTSEL_MASK
|
||||
#define ADC_JEXTREG_JEXTEN_MASK ADC_JSQR_JEXTEN_MASK
|
||||
@ -374,10 +370,10 @@
|
||||
/* Default ADC DMA configuration */
|
||||
|
||||
#ifndef ADC1_DMA_CFG
|
||||
# define ADC1_DMA_CFG ADC_CFGR_DMACFG
|
||||
# define ADC1_DMA_CFG ADC_CFGR1_DMACFG
|
||||
#endif
|
||||
#ifndef ADC2_DMA_CFG
|
||||
# define ADC2_DMA_CFG ADC_CFGR_DMACFG
|
||||
# define ADC2_DMA_CFG ADC_CFGR1_DMACFG
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@ -1591,42 +1587,42 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
|
||||
/* Enable the analog watchdog */
|
||||
|
||||
clrbits = ADC_CFGR_AWD1CH_MASK;
|
||||
setbits = ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL |
|
||||
(priv->r_chanlist[0] << ADC_CFGR_AWD1CH_SHIFT);
|
||||
clrbits = ADC_CFGR1_AWD1CH_MASK;
|
||||
setbits = ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL |
|
||||
(priv->r_chanlist[0] << ADC_CFGR1_AWD1CH_SHIFT);
|
||||
|
||||
/* Set the resolution of the conversion */
|
||||
|
||||
clrbits |= ADC_CFGR_RES_MASK;
|
||||
setbits |= priv->resolution << ADC_CFGR_RES_SHIFT;
|
||||
clrbits |= ADC_CFGR1_RES_MASK;
|
||||
setbits |= priv->resolution << ADC_CFGR1_RES_SHIFT;
|
||||
|
||||
#ifdef ADC_HAVE_DMA
|
||||
if (priv->hasdma)
|
||||
{
|
||||
/* Set DMA mode */
|
||||
|
||||
clrbits |= ADC_CFGR_DMACFG;
|
||||
clrbits |= ADC_CFGR1_DMACFG;
|
||||
|
||||
setbits |= priv->dmacfg;
|
||||
|
||||
/* Enable DMA */
|
||||
|
||||
setbits |= ADC_CFGR_DMAEN;
|
||||
setbits |= ADC_CFGR1_DMAEN;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Disable continuous mode and set align to right */
|
||||
|
||||
clrbits |= ADC_CFGR_CONT | ADC_CFGR_ALIGN;
|
||||
clrbits |= ADC_CFGR1_CONT | ADC_CFGR1_ALIGN;
|
||||
|
||||
/* Disable external trigger for regular channels */
|
||||
|
||||
clrbits |= ADC_CFGR_EXTEN_MASK;
|
||||
setbits |= ADC_CFGR_EXTEN_NONE;
|
||||
clrbits |= ADC_CFGR1_EXTEN_MASK;
|
||||
setbits |= ADC_CFGR1_EXTEN_NONE;
|
||||
|
||||
/* Set CFGR configuration */
|
||||
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits);
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
|
||||
|
||||
#ifndef CONFIG_STM32_ADC_NOIRQ
|
||||
/* Enable interrupt flags, but disable overrun interrupt */
|
||||
@ -1752,7 +1748,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n",
|
||||
adc_getreg(priv, STM32_ADC_ISR_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_CR_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_CFGR_OFFSET));
|
||||
adc_getreg(priv, STM32_ADC_CFGR1_OFFSET));
|
||||
|
||||
ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
|
||||
adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
|
||||
|
||||
55
configs/nucleo-f303ze/adc/defconfig
Normal file
55
configs/nucleo-f303ze/adc/defconfig
Normal file
@ -0,0 +1,55 @@
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_STM32_CCMEXCLUDE is not set
|
||||
CONFIG_ADC=y
|
||||
CONFIG_ANALOG=y
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-f303ze"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32F303ZE=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=6522
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_EXAMPLES_ADC=y
|
||||
CONFIG_EXAMPLES_ADC_GROUPSIZE=3
|
||||
CONFIG_EXAMPLES_ADC_SWTRIG=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=2048
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_NFILE_DESCRIPTORS=8
|
||||
CONFIG_NFILE_STREAMS=8
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_PREALLOC_MQ_MSGS=4
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_PREALLOC_WDOGS=8
|
||||
CONFIG_RAM_SIZE=65536
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_START_DAY=27
|
||||
CONFIG_START_YEAR=2013
|
||||
CONFIG_STM32_ADC1=y
|
||||
CONFIG_STM32_ADC1_DMA=y
|
||||
CONFIG_STM32_ADC3=y
|
||||
CONFIG_STM32_ADC3_RESOLUTION=3
|
||||
CONFIG_STM32_DMA1=y
|
||||
CONFIG_STM32_DMA2=y
|
||||
CONFIG_STM32_FORCEPOWER=y
|
||||
CONFIG_STM32_JTAG_SW_ENABLE=y
|
||||
CONFIG_STM32_TIM1=y
|
||||
CONFIG_STM32_TIM1_ADC=y
|
||||
CONFIG_STM32_USART3=y
|
||||
CONFIG_SYSLOG_NONE=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_USART3_SERIAL_CONSOLE=y
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=1
|
||||
@ -198,4 +198,9 @@
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
|
||||
|
||||
/* DMA **********************************************************************/
|
||||
|
||||
#define ADC1_DMA_CHAN DMACHAN_ADC1
|
||||
#define ADC3_DMA_CHAN DMACHAN_ADC3
|
||||
|
||||
#endif /* __CONFIG_NUCLEO_F303ZE_INCLUDE_BOARD_H */
|
||||
|
||||
@ -52,4 +52,8 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += stm32_appinitialize.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ADC),y)
|
||||
CSRCS += stm32_adc.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
|
||||
@ -92,4 +92,18 @@
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_bringup(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_adc_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize ADC and register the ADC driver.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
int stm32_adc_setup(void);
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIGS_NUCLEO_F303ZE_SRC_NUCLEO_F303ZE_H */
|
||||
|
||||
253
configs/nucleo-f303ze/src/stm32_adc.c
Normal file
253
configs/nucleo-f303ze/src/stm32_adc.c
Normal file
@ -0,0 +1,253 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-f303ze/src/stm32_adc.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3))
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* 1 or 2 ADC devices (DEV1, DEV2).
|
||||
* ADC1 and ADC3 supported for now.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_ADC1)
|
||||
# define DEV1_PORT 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_ADC3)
|
||||
# if defined(DEV1_PORT)
|
||||
# define DEV2_PORT 3
|
||||
# else
|
||||
# define DEV1_PORT 3
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* The number of ADC channels in the conversion list */
|
||||
/* TODO DMA */
|
||||
|
||||
#define ADC1_NCHANNELS 3
|
||||
#define ADC3_NCHANNELS 3
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* DEV 1 */
|
||||
|
||||
#if DEV1_PORT == 1
|
||||
|
||||
#define DEV1_NCHANNELS ADC1_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
|
||||
|
||||
static const uint8_t g_chanlist1[3] =
|
||||
{
|
||||
4,
|
||||
6,
|
||||
9
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist1[3] =
|
||||
{
|
||||
GPIO_ADC1_IN4, /* PA3/A0 */
|
||||
GPIO_ADC1_IN6, /* PC0/A1 */
|
||||
GPIO_ADC1_IN9, /* PC3/A2 */
|
||||
};
|
||||
|
||||
#elif DEV1_PORT == 3
|
||||
|
||||
#define DEV1_NCHANNELS ADC3_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel */
|
||||
|
||||
static const uint8_t g_chanlist1[3] =
|
||||
{
|
||||
8,
|
||||
9,
|
||||
10
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist1[3] =
|
||||
{
|
||||
GPIO_ADC3_IN8, /* PD11/A3 */
|
||||
GPIO_ADC3_IN9, /* PD12/A4 */
|
||||
GPIO_ADC3_IN10, /* PD13/A5 */
|
||||
};
|
||||
|
||||
#endif /* DEV1_PORT == 1 */
|
||||
|
||||
#ifdef DEV2_PORT
|
||||
|
||||
/* DEV 2 */
|
||||
|
||||
#if DEV2_PORT == 3
|
||||
|
||||
#define DEV2_NCHANNELS ADC3_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel */
|
||||
|
||||
static const uint8_t g_chanlist2[3] =
|
||||
{
|
||||
8,
|
||||
9,
|
||||
10
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist2[3] =
|
||||
{
|
||||
GPIO_ADC3_IN8, /* PD11/A3 */
|
||||
GPIO_ADC3_IN9, /* PD12/A4 */
|
||||
GPIO_ADC3_IN10, /* PD13/A5 */
|
||||
};
|
||||
|
||||
#endif /* DEV2_PORT == 3 */
|
||||
#endif /* DEV2_PORT */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_adc_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize ADC and register the ADC driver.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_adc_setup(void)
|
||||
{
|
||||
static bool initialized = false;
|
||||
FAR struct adc_dev_s *adc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Check if we have already initialized */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
/* DEV1 */
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < DEV1_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(g_pinlist1[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC interface 1\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc0" */
|
||||
|
||||
ret = adc_register("/dev/adc0", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef DEV2_PORT
|
||||
/* DEV2 */
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < DEV2_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(g_pinlist2[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC interface 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc1" */
|
||||
|
||||
ret = adc_register("/dev/adc1", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
initialized = true;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */
|
||||
@ -74,5 +74,15 @@ int stm32_bringup(void)
|
||||
|
||||
UNUSED(ret);
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
/* Initialize ADC and register the ADC driver. */
|
||||
|
||||
ret = stm32_adc_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
65
configs/stm32f429i-disco/adc/defconfig
Normal file
65
configs/stm32f429i-disco/adc/defconfig
Normal file
@ -0,0 +1,65 @@
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_STM32_CCMEXCLUDE is not set
|
||||
# CONFIG_STM32_FLASH_PREFETCH is not set
|
||||
CONFIG_ADC=y
|
||||
CONFIG_ANALOG=y
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="stm32f429i-disco"
|
||||
CONFIG_ARCH_BOARD_STM32F429I_DISCO=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32F429Z=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_EXAMPLES_ADC=y
|
||||
CONFIG_EXAMPLES_ADC_GROUPSIZE=3
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_HEAP2_BASE=0xD0000000
|
||||
CONFIG_HEAP2_SIZE=8388608
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_MM_REGIONS=3
|
||||
CONFIG_NFILE_DESCRIPTORS=8
|
||||
CONFIG_NFILE_STREAMS=8
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_MQ_MSGS=4
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_PREALLOC_WDOGS=4
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_START_DAY=6
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2011
|
||||
CONFIG_STM32_ADC1=y
|
||||
CONFIG_STM32_ADC1_DMA=y
|
||||
CONFIG_STM32_ADC3=y
|
||||
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
|
||||
CONFIG_STM32_DMA1=y
|
||||
CONFIG_STM32_DMA2=y
|
||||
CONFIG_STM32_FSMC=y
|
||||
CONFIG_STM32_FSMC_SRAM=y
|
||||
CONFIG_STM32_JTAG_SW_ENABLE=y
|
||||
CONFIG_STM32_PWR=y
|
||||
CONFIG_STM32_TIM1=y
|
||||
CONFIG_STM32_TIM1_ADC=y
|
||||
CONFIG_STM32_USART1=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_USART1_SERIAL_CONSOLE=y
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=0
|
||||
@ -443,4 +443,9 @@
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ)
|
||||
|
||||
#endif /* CONFIG_STM32_LTDC */
|
||||
|
||||
/* DMA *************************************************************************/
|
||||
|
||||
#define ADC1_DMA_CHAN DMAMAP_ADC1_1
|
||||
|
||||
#endif /* __CONFIG_STM32F429I_DISCO_INCLUDE_BOARD_H */
|
||||
|
||||
@ -91,4 +91,8 @@ ifeq ($(CONFIG_PWM),y)
|
||||
CSRCS += stm32_pwm.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ADC),y)
|
||||
CSRCS += stm32_adc.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
|
||||
247
configs/stm32f429i-disco/src/stm32_adc.c
Normal file
247
configs/stm32f429i-disco/src/stm32_adc.c
Normal file
@ -0,0 +1,247 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-f303ze/src/stm32_adc.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3))
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* 1 or 2 ADC devices (DEV1, DEV2).
|
||||
* ADC1 and ADC3 supported for now.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_ADC1)
|
||||
# define DEV1_PORT 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_ADC3)
|
||||
# if defined(DEV1_PORT)
|
||||
# define DEV2_PORT 3
|
||||
# else
|
||||
# define DEV1_PORT 3
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* The number of ADC channels in the conversion list */
|
||||
/* TODO DMA */
|
||||
|
||||
#define ADC1_NCHANNELS 2
|
||||
#define ADC3_NCHANNELS 1
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* DEV 1 */
|
||||
|
||||
#if DEV1_PORT == 1
|
||||
|
||||
#define DEV1_NCHANNELS ADC1_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
|
||||
|
||||
static const uint8_t g_chanlist1[2] =
|
||||
{
|
||||
5,
|
||||
13,
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist1[2] =
|
||||
{
|
||||
GPIO_ADC1_IN5, /* PA5 */
|
||||
GPIO_ADC1_IN13, /* PC3 */
|
||||
};
|
||||
|
||||
#elif DEV1_PORT == 3
|
||||
|
||||
#define DEV1_NCHANNELS ADC3_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel */
|
||||
|
||||
static const uint8_t g_chanlist1[1] =
|
||||
{
|
||||
4,
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist1[1] =
|
||||
{
|
||||
GPIO_ADC3_IN4, /* PF6 */
|
||||
};
|
||||
|
||||
#endif /* DEV1_PORT == 1 */
|
||||
|
||||
#ifdef DEV2_PORT
|
||||
|
||||
/* DEV 2 */
|
||||
|
||||
#if DEV2_PORT == 3
|
||||
|
||||
#define DEV2_NCHANNELS ADC3_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel */
|
||||
|
||||
static const uint8_t g_chanlist2[3] =
|
||||
{
|
||||
8,
|
||||
9,
|
||||
10
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist2[3] =
|
||||
{
|
||||
GPIO_ADC3_IN8, /* PD11/A3 */
|
||||
GPIO_ADC3_IN9, /* PD12/A4 */
|
||||
GPIO_ADC3_IN10, /* PD13/A5 */
|
||||
};
|
||||
|
||||
#endif /* DEV2_PORT == 3 */
|
||||
#endif /* DEV2_PORT */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_adc_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize ADC and register the ADC driver.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_adc_setup(void)
|
||||
{
|
||||
static bool initialized = false;
|
||||
FAR struct adc_dev_s *adc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Check if we have already initialized */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
/* DEV1 */
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < DEV1_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(g_pinlist1[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC interface 1\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc0" */
|
||||
|
||||
ret = adc_register("/dev/adc0", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef DEV2_PORT
|
||||
/* DEV2 */
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < DEV2_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(g_pinlist2[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC interface 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc1" */
|
||||
|
||||
ret = adc_register("/dev/adc1", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
initialized = true;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */
|
||||
@ -376,6 +376,16 @@ int stm32_bringup(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
/* Initialize ADC and register the ADC device. */
|
||||
|
||||
ret = stm32_adc_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -403,5 +403,17 @@ int stm32_l3gd20initialize(FAR const char *devpath);
|
||||
int stm32_pwm_setup(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_adc_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize ADC and register the ADC device.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
int stm32_adc_setup(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __CONFIGS_STM32F429I_DISCO_SRC_STM32F429I_DISCO_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user