From becb667f56ab8bd18499dc501ff5f44f87a375e5 Mon Sep 17 00:00:00 2001 From: Mateusz Szafoni Date: Mon, 12 Nov 2018 15:45:55 +0000 Subject: [PATCH] Merged in raiden00/nuttx_pe (pull request #758) stm32/stm32_adc: major refator stm32/stm32_adc: use STM32 ADC IP core version and ADC available functions instead of chip family names in conditional compilation stm32/chip: replace family specific ADC headers with STM32 ADC IP core version headers stm32/stm32_adc: configurable sample time supported for all chips, not only L1 stm32/stm32_adc: enable/disable interrupts supported for all chips, not only L1 stm32/stm32_adc: resolution configuration stm32/stm32f33xxx_adc: remove wrong assertion configs/nucleo-f303ze: support for ADC and ADC example configs/stm32f429i-disco: support for ADC and ADC example Approved-by: GregoryN --- arch/arm/src/stm32/Kconfig | 72 ++ arch/arm/src/stm32/chip/stm32_adc.h | 857 +---------------- arch/arm/src/stm32/chip/stm32_adc_v1.h | 627 ++++++++++++ arch/arm/src/stm32/chip/stm32_adc_v1l1.h | 563 +++++++++++ .../{stm32f33xxx_adc.h => stm32_adc_v2.h} | 425 ++++++--- arch/arm/src/stm32/chip/stm32_tim.h | 6 +- .../src/stm32/chip/stm32f20xxx_memorymap.h | 4 - arch/arm/src/stm32/chip/stm32f30xxx_adc.h | 620 ------------ .../src/stm32/chip/stm32f30xxx_memorymap.h | 8 +- .../src/stm32/chip/stm32f33xxx_memorymap.h | 2 +- arch/arm/src/stm32/chip/stm32f37xxx_adc.h | 321 ------- .../src/stm32/chip/stm32f37xxx_memorymap.h | 4 +- arch/arm/src/stm32/chip/stm32f37xxx_rcc.h | 1 + .../src/stm32/chip/stm32f40xxx_memorymap.h | 4 - .../src/stm32/chip/stm32l15xxx_memorymap.h | 1 - arch/arm/src/stm32/chip/stm32l15xxx_rcc.h | 1 + arch/arm/src/stm32/stm32_adc.c | 894 +++++++++++------- arch/arm/src/stm32/stm32_adc.h | 560 ++++++----- arch/arm/src/stm32/stm32_dma.h | 20 + arch/arm/src/stm32/stm32_pwm.c | 5 +- arch/arm/src/stm32/stm32f33xxx_adc.c | 44 +- configs/nucleo-f303ze/adc/defconfig | 55 ++ configs/nucleo-f303ze/include/board.h | 5 + configs/nucleo-f303ze/src/Makefile | 4 + configs/nucleo-f303ze/src/nucleo-f303ze.h | 14 + configs/nucleo-f303ze/src/stm32_adc.c | 253 +++++ configs/nucleo-f303ze/src/stm32_bringup.c | 10 + configs/stm32f429i-disco/adc/defconfig | 65 ++ configs/stm32f429i-disco/include/board.h | 5 + configs/stm32f429i-disco/src/Makefile | 4 + configs/stm32f429i-disco/src/stm32_adc.c | 247 +++++ configs/stm32f429i-disco/src/stm32_bringup.c | 10 + .../stm32f429i-disco/src/stm32f429i-disco.h | 12 + 33 files changed, 3159 insertions(+), 2564 deletions(-) create mode 100644 arch/arm/src/stm32/chip/stm32_adc_v1.h create mode 100644 arch/arm/src/stm32/chip/stm32_adc_v1l1.h rename arch/arm/src/stm32/chip/{stm32f33xxx_adc.h => stm32_adc_v2.h} (59%) delete mode 100644 arch/arm/src/stm32/chip/stm32f30xxx_adc.h delete mode 100644 arch/arm/src/stm32/chip/stm32f37xxx_adc.h create mode 100644 configs/nucleo-f303ze/adc/defconfig create mode 100644 configs/nucleo-f303ze/src/stm32_adc.c create mode 100644 configs/stm32f429i-disco/adc/defconfig create mode 100644 configs/stm32f429i-disco/src/stm32_adc.c diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 21eb8c94c5..5b500c1b90 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1381,6 +1381,8 @@ config STM32_STM32L15XX select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY + select STM32_HAVE_IP_TIMERS_V1 + select STM32_HAVE_IP_ADC_V1 config STM32_ENERGYLITE bool @@ -1401,6 +1403,8 @@ config STM32_STM32F10XX select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_RTC_COUNTER select STM32_HAVE_TIM3 + select STM32_HAVE_IP_TIMERS_V1 + select STM32_HAVE_IP_ADC_V1_BASIC config STM32_VALUELINE bool @@ -1511,6 +1515,8 @@ config STM32_STM32F20XX bool default n select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_TIMERS_V1 + select STM32_HAVE_IP_ADC_V1 config STM32_STM32F205 bool @@ -1593,6 +1599,7 @@ config STM32_STM32F30XX select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 select STM32_HAVE_IP_TIMERS_V2 + select STM32_HAVE_IP_ADC_V2 config STM32_STM32F302 bool @@ -1632,6 +1639,7 @@ config STM32_STM32F33XX select STM32_HAVE_DAC2 select STM32_HAVE_USART3 select STM32_HAVE_IP_TIMERS_V2 + select STM32_HAVE_IP_ADC_V2 config STM32_STM32F37XX bool @@ -1655,6 +1663,8 @@ config STM32_STM32F37XX select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 select STM32_HAVE_USART3 + select STM32_HAVE_IP_TIMERS_V1 + select STM32_HAVE_IP_ADC_V1_BASIC config STM32_STM32F4XXX bool @@ -1662,6 +1672,8 @@ config STM32_STM32F4XXX select STM32_HAVE_SPI2 select STM32_HAVE_I2C2 select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_TIMERS_V1 + select STM32_HAVE_IP_ADC_V1 config STM32_STM32F401xBC bool @@ -2027,6 +2039,10 @@ config STM32_HAVE_UART8 bool default n +config STM32_HAVE_IP_TIMERS_V1 + bool + default n + config STM32_HAVE_IP_TIMERS_V2 bool default n @@ -2099,6 +2115,24 @@ config STM32_HAVE_TIM17 bool default n +config STM32_HAVE_IP_ADC_V1 + bool + default n + +config STM32_HAVE_IP_ADC_V1_BASIC + bool + default n + select STM32_HAVE_IP_ADC_V1 + +config STM32_HAVE_IP_ADC_V2 + bool + default n + +config STM32_HAVE_IP_ADC_V2_BASIC + bool + default n + select STM32_HAVE_IP_ADC_V2 + config STM32_HAVE_ADC2 bool default n @@ -7484,6 +7518,38 @@ endmenu # "HRTIM Configuration" menu "ADC Configuration" depends on STM32_ADC +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC4_RESOLUTION + int "ADC4 resolution" + depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + config STM32_ADC_NO_STARTUP_CONV bool "Do not start conversion when opening ADC device" default n @@ -7498,6 +7564,12 @@ config STM32_ADC_NOIRQ Do not use default ADC interrupts handlers. Only for STM32_STM32F33XX at this moment. +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + default n + ---help--- + Enable ADC sample time configuration (SMPRx registers). + config STM32_ADC1_DMA bool "ADC1 DMA" depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h index 73d3acb353..87a2d37aa2 100644 --- a/arch/arm/src/stm32/chip/stm32_adc.h +++ b/arch/arm/src/stm32/chip/stm32_adc.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * arch/arm/src/stm32/chip/stm32_adc.h * - * Copyright (C) 2009, 2011, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,847 +44,28 @@ #include "chip.h" -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ +/* There are 2 main types of ADC IP cores among STM32 chips: + * 1. STM32 ADC IPv1: + * a) basic version for F1 and F37x + * b) extended version for F2, F4, F7, L1: + * 2. STM32 ADC IPv2: + * a) basic version for F0 and L0 + * b) extended version for F3 (without F37x), H7, L4, L4+ + * + * We also distinguish the modified STM32 ADC IPv1 core for the L1 family, + * which differs too much to keep it in the same file as ADC IPv1. + */ -/* Register Offsets *********************************************************************************/ - -#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ -#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ -#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ -#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ -#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ -#ifndef CONFIG_STM32_STM32L15XX -# define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */ -# define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */ -# define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */ -# define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */ -# define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */ -# define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */ -# define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */ -# define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */ -# define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */ -# define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */ -# define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ -#else -# define STM32_ADC_SMPR3_OFFSET 0x0014 /* ADC sample time register 3 (32-bit) */ -# define STM32_ADC_JOFR1_OFFSET 0x0018 /* ADC injected channel data offset register 1 (32-bit) */ -# define STM32_ADC_JOFR2_OFFSET 0x001c /* ADC injected channel data offset register 2 (32-bit) */ -# define STM32_ADC_JOFR3_OFFSET 0x0020 /* ADC injected channel data offset register 3 (32-bit) */ -# define STM32_ADC_JOFR4_OFFSET 0x0024 /* ADC injected channel data offset register 4 (32-bit) */ -# define STM32_ADC_HTR_OFFSET 0x0028 /* ADC watchdog high threshold register (32-bit) */ -# define STM32_ADC_LTR_OFFSET 0x002c /* ADC watchdog low threshold register (32-bit) */ -# define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 (32-bit) */ -# define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 (32-bit) */ -# define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 (32-bit) */ -# define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 (32-bit) */ -# define STM32_ADC_SQR5_OFFSET 0x0040 /* ADC regular sequence register 5 (32-bit) */ -# define STM32_ADC_JSQR_OFFSET 0x0044 /* ADC injected sequence register (32-bit) */ -# define STM32_ADC_JDR1_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_JDR2_OFFSET 0x004c /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_JDR3_OFFSET 0x0050 /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_JDR4_OFFSET 0x0054 /* ADC injected data register 1 (32-bit) */ -# define STM32_ADC_DR_OFFSET 0x0058 /* ADC regular data register (32-bit) */ -# define STM32_ADC_SMPR0_OFFSET 0X005c /* ADC sample time register 3 (32-bit) */ -#endif - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ -# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ -# ifndef CONFIG_STM32_STM32L15XX -# define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ -# endif -#endif - -/* Register Addresses *******************************************************************************/ - -#ifdef CONFIG_STM32_STM32L15XX -# define STM32_ADC1_BASE STM32_ADC_BASE -#endif - -#if STM32_NADC > 0 -# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) -# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) -# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) -# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) -# ifdef CONFIG_STM32_STM32L15XX -# define STM32_ADC1_SMPR3 (STM32_ADC1_BASE+STM32_ADC_SMPR3_OFFSET) -# endif -# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET) -# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET) -# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) -# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) -# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) -# ifdef CONFIG_STM32_STM32L15XX -# define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) -# define STM32_ADC1_SQR5 (STM32_ADC1_BASE+STM32_ADC_SQR5_OFFSET) -# endif -# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) -# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) -# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) -# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) -# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) -# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) -# ifdef CONFIG_STM32_STM32L15XX -# define STM32_ADC1_SMPR0 (STM32_ADC1_BASE+STM32_ADC_SMPR0_OFFSET) -# endif -#endif - -#if STM32_NADC > 1 -# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) -# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) -# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) -# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET) -# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET) -# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) -# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) -# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) -# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) -# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) -# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) -# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) -# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) -# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) -#endif - -#if STM32_NADC > 2 -# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) -# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) -# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) -# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET) -# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET) -# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) -# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) -# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) -# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) -# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) -# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) -# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) -# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) -# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) -#endif - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -# define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) -# define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) -# ifndef CONFIG_STM32_STM32L15XX -# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) -# endif -#endif - -/* Register Bitfield Definitions ********************************************************************/ - -/* ADC status register */ - -#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ -#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ -#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ -#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ -#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ -#endif -#if defined(CONFIG_STM32_STM32L15XX) -# define ADC_SR_ADONS (1 << 6) /* Bit 6 : ADC ON status. Set and cleared by HW */ -# define ADC_SR_RCNR (1 << 8) /* Bit 8 : Regular channel not ready. Set and cleared by HW */ -# define ADC_SR_JCNR (1 << 9) /* Bit 9 : Injected channel not ready. Set and cleared by HW */ -#endif - -/* ADC control register 1 */ - -#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ -#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) - -#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ -#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ -#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ -#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ -#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ -#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) - -#if defined(CONFIG_STM32_STM32L15XX) -# define ADC_CR1_PDD (1 << 16) /* Bit 16 : Power down during the delay phase. This bit must be written only when ADON=0 */ -# define ADC_CR1_PDI (1 << 17) /* Bit 17 : Power down during the idle phase. This bit must - * be written only when ADON=0 */ -#endif - -#ifdef CONFIG_STM32_STM32F10XX -# define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */ -# define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT) -# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */ -# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */ -# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */ -# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */ -# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */ -# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */ -# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */ -# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */ -#endif - -#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ -# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) -# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */ -# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */ -# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */ -# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */ -# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ -# define ADC_CR1_RESERVED (0xfb3f0000) -#endif - -/* ADC control register 2 */ - -#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ -#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ - -#ifdef CONFIG_STM32_STM32F10XX -# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */ -#elif defined(CONFIG_STM32_STM32L15XX) -# define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no - * conversion is on going. This bit is available in high and medium+ - * density devices only. - */ -#endif - -#ifndef CONFIG_STM32_STM32L15XX -# define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */ -#endif - -#ifdef CONFIG_STM32_STM32L15XX -# define ADC_CR2_DELS_SHIFT (4) /* Bits 2-0: Delay selection */ -# define ADC_CR2_DELS_MASK (0x07 << ADC_CR2_DELS_SHIFT) -# -# define ADC_CR2_DELS_NODEL (0x0 << ADC_CR2_DELS_SHIFT) /* No delay */ -# define ADC_CR2_DELS_TILLRD (0x01 << ADC_CR2_DELS_SHIFT) /* Until the converted data have been read */ -# define ADC_CR2_DELS_APB7 (0x02 << ADC_CR2_DELS_SHIFT) /* 7 APB clock cycles after the end of conversion */ -# define ADC_CR2_DELS_APB15 (0x03 << ADC_CR2_DELS_SHIFT) /* 15 APB clock cycles after the end of conversion */ -# define ADC_CR2_DELS_APB31 (0x04 << ADC_CR2_DELS_SHIFT) /* 31 APB clock cycles after the end of conversion */ -# define ADC_CR2_DELS_APB63 (0x05 << ADC_CR2_DELS_SHIFT) /* 63 APB clock cycles after the end of conversion */ -# define ADC_CR2_DELS_APB127 (0x06 << ADC_CR2_DELS_SHIFT) /* 127 APB clock cycles after the end of conversion */ -# define ADC_CR2_DELS_APB255 (0x07 << ADC_CR2_DELS_SHIFT) /* 255 APB clock cycles after the end of conversion */ -#endif - -#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ -# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ -#endif - -#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) - /* Bits 12-15: Reserved */ -# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ -# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) -# ifdef CONFIG_STM32_STM32L15XX -# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */ -# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ -# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/ -# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ -# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ -# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ -# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */ -# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */ -# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ +#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) +# if defined(CONFIG_STM32_STM32L15XX) +# include "stm32_adc_v1l1.h" /* Special case for L1 */ # else -# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */ -# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */ -# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */ -# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */ -# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */ -# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ -# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ -# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */ -# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */ -# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */ -# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */ -# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */ -# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ +# include "stm32_adc_v1.h" # endif - -# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ -# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) -# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -# define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ - /* Bit 23: Reserved, must be kept at reset value. */ -# define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ -# define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) -# ifdef CONFIG_STM32_STM32L15XX -# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */ -# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ -# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */ -# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ -# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ -# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ -# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ -# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */ -# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ -# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */ -# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ -# else -# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ -# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ -# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ -# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ -# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */ -# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */ -# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ -# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ -# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */ -# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */ -# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */ -# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */ -# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */ -# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */ -# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ -# endif - -# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ -# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) -# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ -# define ADC_CR2_RESERVED (0x8080f0fc) +#elif defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# include "stm32_adc_v2.h" #else -# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */ -# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_T1TRGO (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */ -# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */ -# define ADC_CR2_JEXTSEL_T2TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */ -# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */ -# define ADC_CR2_JEXTSEL_SWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */ - -# define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */ -# define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */ -# define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */ -# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */ -# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */ -# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */ -# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */ -# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */ -# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */ - -# define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */ -# define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */ -# define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */ -# define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */ +# error "STM32 ADC IP version not specified" #endif -/* ADC sample time register 1 */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -# define ADC_SMPR_3 0 /* 000: 3 cycles */ -# define ADC_SMPR_15 1 /* 001: 15 cycles */ -# define ADC_SMPR_28 2 /* 010: 28 cycles */ -# define ADC_SMPR_56 3 /* 011: 56 cycles */ -# define ADC_SMPR_84 4 /* 100: 84 cycles */ -# define ADC_SMPR_112 5 /* 101: 112 cycles */ -# define ADC_SMPR_144 6 /* 110: 144 cycles */ -# define ADC_SMPR_480 7 /* 111: 480 cycles */ - -#elif !defined(CONFIG_STM32_STM32L15XX) && !defined(CONFIG_STM32_STM32F20XX) && !defined(CONFIG_STM32_STM32F4XXX) - -# define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ -# define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */ -# define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */ -# define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */ -# define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */ -# define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */ -# define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */ -# define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */ - -#elif defined(CONFIG_STM32_STM32L15XX) - -# define ADC_SMPR_4 0 /* 000: 3 cycles */ -# define ADC_SMPR_9 1 /* 001: 9 cycles */ -# define ADC_SMPR_16 2 /* 010: 16 cycles */ -# define ADC_SMPR_24 3 /* 011: 24 cycles */ -# define ADC_SMPR_48 4 /* 100: 48 cycles */ -# define ADC_SMPR_96 5 /* 101: 96 cycles */ -# define ADC_SMPR_192 6 /* 110: 192 cycles */ -# define ADC_SMPR_384 7 /* 111: 384 cycles */ - -#endif - -#ifndef CONFIG_STM32_STM32L15XX -# define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -# define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) -# define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -# define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) -# define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -# define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) -# define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -# define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) -# define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -# define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) -# define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -# define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) -# define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -# define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) -# define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -# define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT) -# endif -#else -# define ADC_SMPR1_SMP20_SHIFT (0) /* Bits 0-2: Channel 20 Sample time selection */ -# define ADC_SMPR1_SMP20_MASK (7 << ADC_SMPR1_SMP20_SHIFT) -# define ADC_SMPR1_SMP21_SHIFT (3) /* Bits 3-5: Channel 21 Sample time selection */ -# define ADC_SMPR1_SMP21_MASK (7 << ADC_SMPR1_SMP21_SHIFT) -# define ADC_SMPR1_SMP22_SHIFT (6) /* Bits 6-8: Channel 22 Sample time selection */ -# define ADC_SMPR1_SMP22_MASK (7 << ADC_SMPR1_SMP22_SHIFT) -# define ADC_SMPR1_SMP23_SHIFT (9) /* Bits 9-11: Channel 23 Sample time selection */ -# define ADC_SMPR1_SMP23_MASK (7 << ADC_SMPR1_SMP23_SHIFT) -# define ADC_SMPR1_SMP24_SHIFT (12) /* Bits 12-14: Channel 24 Sample time selection */ -# define ADC_SMPR1_SMP24_MASK (7 << ADC_SMPR1_SMP24_SHIFT) -# define ADC_SMPR1_SMP25_SHIFT (15) /* Bits 15-17: Channel 25 Sample time selection */ -# define ADC_SMPR1_SMP25_MASK (7 << ADC_SMPR1_SMP25_SHIFT) -# define ADC_SMPR1_SMP26_SHIFT (18) /* Bits 18-20: Channel 26 Sample time selection */ -# define ADC_SMPR1_SMP26_MASK (7 << ADC_SMPR1_SMP26_SHIFT) -# define ADC_SMPR1_SMP27_SHIFT (21) /* Bits 21-23: Channel 27 Sample time selection */ -# define ADC_SMPR1_SMP27_MASK (7 << ADC_SMPR1_SMP27_SHIFT) -# define ADC_SMPR1_SMP28_SHIFT (24) /* Bits 24-26: Channel 28 Sample time selection */ -# define ADC_SMPR1_SMP28_MASK (7 << ADC_SMPR1_SMP28_SHIFT) -# define ADC_SMPR1_SMP29_SHIFT (27) /* Bits 27-29: Channel 29 Sample time selection */ -# define ADC_SMPR1_SMP29_MASK (7 << ADC_SMPR1_SMP29_SHIFT) -#endif - -/* ADC sample time register 2 */ - -#ifndef CONFIG_STM32_STM32L15XX -# define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ -# define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) -# define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -# define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) -# define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -# define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) -# define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -# define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) -# define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -# define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) -# define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -# define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) -# define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -# define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) -# define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -# define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) -# define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -# define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) -# define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -# define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) -#else -# define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -# define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) -# define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -# define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) -# define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -# define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) -# define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -# define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) -# define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -# define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) -# define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -# define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) -# define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -# define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) -# define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -# define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) -# define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -# define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) -# define ADC_SMPR2_SMP19_SHIFT (27) /* Bits 27-29: Channel 18 Sample time selection */ -# define ADC_SMPR2_SMP19_MASK (7 << ADC_SMPR2_SMP19_SHIFT) -#endif - -/* ADC sample time register 3 */ - -#ifdef CONFIG_STM32_STM32L15XX -# define ADC_SMPR3_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ -# define ADC_SMPR3_SMP0_MASK (7 << ADC_SMPR3_SMP0_SHIFT) -# define ADC_SMPR3_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -# define ADC_SMPR3_SMP1_MASK (7 << ADC_SMPR3_SMP1_SHIFT) -# define ADC_SMPR3_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -# define ADC_SMPR3_SMP2_MASK (7 << ADC_SMPR3_SMP2_SHIFT) -# define ADC_SMPR3_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -# define ADC_SMPR3_SMP3_MASK (7 << ADC_SMPR3_SMP3_SHIFT) -# define ADC_SMPR3_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -# define ADC_SMPR3_SMP4_MASK (7 << ADC_SMPR3_SMP4_SHIFT) -# define ADC_SMPR3_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -# define ADC_SMPR3_SMP5_MASK (7 << ADC_SMPR3_SMP5_SHIFT) -# define ADC_SMPR3_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -# define ADC_SMPR3_SMP6_MASK (7 << ADC_SMPR3_SMP6_SHIFT) -# define ADC_SMPR3_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -# define ADC_SMPR3_SMP7_MASK (7 << ADC_SMPR3_SMP7_SHIFT) -# define ADC_SMPR3_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -# define ADC_SMPR3_SMP8_MASK (7 << ADC_SMPR3_SMP8_SHIFT) -# define ADC_SMPR3_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -# define ADC_SMPR3_SMP9_MASK (7 << ADC_SMPR3_SMP9_SHIFT) -#endif - -/* ADC sample time register 0 */ - -#ifdef CONFIG_STM32_STM32L15XX -# define ADC_SMPR3_SMP30_SHIFT (0) /* Bits 2-0: Channel 30 Sample time selection */ -# define ADC_SMPR3_SMP30_MASK (7 << ADC_SMPR3_SMP30_SHIFT) -# define ADC_SMPR3_SMP31_SHIFT (3) /* Bits 5-3: Channel 31 Sample time selection */ -# define ADC_SMPR3_SMP31_MASK (7 << ADC_SMPR3_SMP31_SHIFT) -#endif -/* ADC injected channel data offset register 1-4 */ - -#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ -#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) - -/* ADC watchdog high threshold register */ - -#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ -#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) - -/* ADC watchdog low threshold register */ - -#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ -#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) - -/* ADC regular sequence register 1 */ - -#ifndef CONFIG_STM32_STM32L15XX -# define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ -# define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) -# define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ -# define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) -# define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ -# define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) -# define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ -# define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) -# define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ -# define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) -# define ADC_SQR1_RESERVED (0xff000000) -# define ADC_SQR1_FIRST (13) -# define ADC_SQR1_LAST (16) -# define ADC_SQR1_SQ_OFFSET (0) -#else -# define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */ -# define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT) -# define ADC_SQR1_SQ26_SHIFT (5) /* Bits 9-5: 26th conversion in regular sequence */ -# define ADC_SQR1_SQ26_MASK (0x1f << ADC_SQR1_SQ26_SHIFT) -# define ADC_SQR1_SQ27_SHIFT (10) /* Bits 14-10: 27th conversion in regular sequence */ -# define ADC_SQR1_SQ27_MASK (0x1f << ADC_SQR1_SQ27_SHIFT) -# define ADC_SQR1_SQ28_SHIFT (15) /* Bits 19-15: 28th conversion in regular sequence */ -# define ADC_SQR1_SQ28_MASK (0x1f << ADC_SQR1_SQ28_SHIFT) -# define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */ -# define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT) -# define ADC_SQR1_RESERVED (0xff000000) -# define ADC_SQR1_FIRST (25) -# define ADC_SQR1_LAST (28) -# define ADC_SQR1_SQ_OFFSET (0) -#endif - -/* ADC regular sequence register 2 */ - -#ifndef CONFIG_STM32_STM32L15XX -# define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ -# define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -# define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ -# define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -# define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ -# define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -# define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ -# define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) -# define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ -# define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT ) -# define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ -# define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) -# define ADC_SQR2_RESERVED (0xc0000000) -# define ADC_SQR2_FIRST (7) -# define ADC_SQR2_LAST (12) -# define ADC_SQR2_SQ_OFFSET (0) -#else -# define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */ -# define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT) -# define ADC_SQR2_SQ20_SHIFT (5) /* Bits 9-5: 20th conversion in regular sequence */ -# define ADC_SQR2_SQ20_MASK (0x1f << ADC_SQR2_SQ20_SHIFT) -# define ADC_SQR2_SQ21_SHIFT (10) /* Bits 14-10: 21th conversion in regular sequence */ -# define ADC_SQR2_SQ21_MASK (0x1f << ADC_SQR2_SQ21_SHIFT) -# define ADC_SQR2_SQ22_SHIFT (15) /* Bits 19-15: 22th conversion in regular sequence */ -# define ADC_SQR2_SQ22_MASK (0x1f << ADC_SQR2_SQ22_SHIFT) -# define ADC_SQR2_SQ23_SHIFT (20) /* Bits 24-20: 23th conversion in regular sequence */ -# define ADC_SQR2_SQ23_MASK (0x1f << ADC_SQR2_SQ23_SHIFT ) -# define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */ -# define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT) -# define ADC_SQR2_RESERVED (0xc0000000) -# define ADC_SQR2_FIRST (19) -# define ADC_SQR2_LAST (24) -# define ADC_SQR2_SQ_OFFSET (0) -#endif - -/* ADC regular sequence register 3 */ - -#ifndef CONFIG_STM32_STM32L15XX -# define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ -# define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) -# define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ -# define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) -# define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ -# define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) -# define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ -# define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) -# define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ -# define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT ) -# define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ -# define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) -# define ADC_SQR3_RESERVED (0xc0000000) -# define ADC_SQR3_FIRST (1) -# define ADC_SQR3_LAST (6) -# define ADC_SQR3_SQ_OFFSET (0) -#else -# define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ -# define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) -# define ADC_SQR3_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ -# define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) -# define ADC_SQR3_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ -# define ADC_SQR3_SQ15_MASK (0x1f << ADC_SQR3_SQ15_SHIFT) -# define ADC_SQR3_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ -# define ADC_SQR3_SQ16_MASK (0x1f << ADC_SQR3_SQ16_SHIFT) -# define ADC_SQR3_SQ17_SHIFT (20) /* Bits 24-20: 17th conversion in regular sequence */ -# define ADC_SQR3_SQ17_MASK (0x1f << ADC_SQR3_SQ17_SHIFT ) -# define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */ -# define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT) -# define ADC_SQR3_RESERVED (0xc0000000) -# define ADC_SQR3_FIRST (13) -# define ADC_SQR3_LAST (18) -# define ADC_SQR3_SQ_OFFSET (0) -#endif - -/* ADC regular sequence register 4 */ - -#ifdef CONFIG_STM32_STM32L15XX -# define ADC_SQR4_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ -# define ADC_SQR4_SQ7_MASK (0x1f << ADC_SQR4_SQ7_SHIFT) -# define ADC_SQR4_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ -# define ADC_SQR4_SQ8_MASK (0x1f << ADC_SQR4_SQ8_SHIFT) -# define ADC_SQR4_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ -# define ADC_SQR4_SQ9_MASK (0x1f << ADC_SQR4_SQ9_SHIFT) -# define ADC_SQR4_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ -# define ADC_SQR4_SQ10_MASK (0x1f << ADC_SQR4_SQ10_SHIFT) -# define ADC_SQR4_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ -# define ADC_SQR4_SQ11_MASK (0x1f << ADC_SQR4_SQ11_SHIFT ) -# define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ -# define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT) -# define ADC_SQR4_RESERVED (0xc0000000) -# define ADC_SQR4_FIRST (7) -# define ADC_SQR4_LAST (12) -# define ADC_SQR4_SQ_OFFSET (0) -#endif - -/* ADC regular sequence register 5 */ - -#ifdef CONFIG_STM32_STM32L15XX -# define ADC_SQR5_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ -# define ADC_SQR5_SQ1_MASK (0x1f << ADC_SQR5_SQ1_SHIFT) -# define ADC_SQR5_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ -# define ADC_SQR5_SQ2_MASK (0x1f << ADC_SQR5_SQ2_SHIFT) -# define ADC_SQR5_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ -# define ADC_SQR5_SQ3_MASK (0x1f << ADC_SQR5_SQ3_SHIFT) -# define ADC_SQR5_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ -# define ADC_SQR5_SQ4_MASK (0x1f << ADC_SQR5_SQ4_SHIFT) -# define ADC_SQR5_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ -# define ADC_SQR5_SQ5_MASK (0x1f << ADC_SQR5_SQ5_SHIFT ) -# define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ -# define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT) -# define ADC_SQR5_RESERVED (0xc0000000) -# define ADC_SQR5_FIRST (1) -# define ADC_SQR5_LAST (6) -# define ADC_SQR5_SQ_OFFSET (0) -#endif - -/* Offset between SQ bits */ - -#define ADC_SQ_OFFSET (5) - -/* ADC injected sequence register */ - -#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) -#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) - -/* ADC injected data register 1-4 */ - -#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC regular data register */ - -#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -#ifdef CONFIG_STM32_STM32F10XX -# define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */ -# define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT) -#endif - -/* Common status register */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) -# -# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ -# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ -# define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ -# define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ -# define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ -# define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ -# /* Bits 6-7: Reserved, must be kept at reset value. */ -#ifdef CONFIG_STM32_STM32L15XX -# define ADC_CSR_ADONS1 (1 << 6) /* Bit 6: ADON Status of ADC1. This bit is a copy of the ADONS bit in the ADC_SR register. */ -#endif -# -# ifndef CONFIG_STM32_STM32L15XX -# define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */ -# define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */ -# define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */ -# define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */ -# define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */ -# define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */ -# /* Bits 14-15: Reserved, must be kept at reset value. */ -# define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */ -# define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */ -# define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */ -# define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */ -# define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */ -# define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */ -# /* Bits 22-31: Reserved, must be kept at reset value. */ -# endif -# -#endif - -/* Common control register */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ -# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT) -# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ - /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ -# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ -# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ - /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ -# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ -# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ - /* Bits 5-7: Reserved, must be kept at reset value. */ -# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ - /* Bit 12 Reserved, must be kept at reset value. */ -# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ - -# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ -# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT) -# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */ -# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */ -# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */ -# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */ - -# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ -# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) -# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */ -# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ -# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ -# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ - /* Bits 18-21: Reserved, must be kept at reset value. */ -# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */ -# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ - /* Bits 24-31 Reserved, must be kept at reset value. */ -#elif defined(CONFIG_STM32_STM32L15XX) - /* Bits 15-0: Reserved, must be kept at reset value */ -# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ -# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) -# define ADC_CCR_ADCPRE_DIV1 (0 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 1 */ -# define ADC_CCR_ADCPRE_DIV2 (1 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 2 */ -# define ADC_CCR_ADCPRE_DIV4 (2 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 4 */ - /* 11: Reserved */ - /* Bits 22-18: Reserved, must be kept at reset value */ -# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ - /* Bits 31-24: Reserved, must be kept at reset value */ -#endif - -/* Data register for dual and triple modes (32-bit data with no named fields) */ - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Data - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Function Prototypes - ****************************************************************************************************/ - #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_H */ diff --git a/arch/arm/src/stm32/chip/stm32_adc_v1.h b/arch/arm/src/stm32/chip/stm32_adc_v1.h new file mode 100644 index 0000000000..75b9b27202 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32_adc_v1.h @@ -0,0 +1,627 @@ +/**************************************************************************************************** + * arch/arm/src/stm32/chip/stm32_adc_ipv1.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/* This is implementation for STM32 ADC IPv1 - F1, F2, F37x, F4, F7. + * NOTE: L1 use modified IPv1 (look at chip/stm32_adc_v1l1.h). + */ + +#define HAVE_IP_ADC_V1 +#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */ +#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ +#undef HAVE_ADC_POWERDOWN /* No ADC power down */ + +/* F1 and F37x have basic version of ADC hardware + * - no common ADC registers + * - ADCs are not coupled in single ADC block (no common ADC base address) + * - no configurable resolution + * - no overrun + * - ... + */ + +#if defined(CONFIG_STM32_HAVE_IP_ADC_V1_BASIC) +# define HAVE_BASIC_ADC +#else +# undef HAVE_BASIC_ADC +#endif + +/* VBAT channel support only if no basic ADC */ + +#ifndef HAVE_BASIC_ADC +# define HAVE_ADC_VBAT +#else +# undef HAVE_ADC_VBAT +#endif + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* For the basic ADC IPv1, the ADCx_BASE definitions are defined in chip/stm32xxx_memorymap.h files */ + +#ifndef HAVE_BASIC_ADC +# define STM32_ADC1_OFFSET 0x0000 +# define STM32_ADC2_OFFSET 0x0100 +# define STM32_ADC3_OFFSET 0x0200 +# define STM32_ADC_CMN_OFFSET 0x0300 + +# define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC_BASE) /* ADC1 ADC */ +# define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC_BASE) /* ADC2 ADC */ +# define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC_BASE) /* ADC3 ADC */ +# define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET+STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */ +#endif + +/* Register Offsets *********************************************************************************/ + +#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ +#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ +#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ +#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ +#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ +#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */ +#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */ +#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */ +#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */ +#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */ +#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */ +#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */ +#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */ +#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */ +#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */ +#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ + +#ifndef HAVE_BASIC_ADC +# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ +# define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ +#endif + +/* Register Addresses *******************************************************************************/ + +#if STM32_NADC > 0 +# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#endif + +#if STM32_NADC > 1 +# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#endif + +#ifndef HAVE_BASIC_ADC +# define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +# define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) +# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************************************/ + +/* ADC status register */ + +#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ +#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ +#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ +#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ +#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ +#ifndef HAVE_BASIC_ADC +# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ +#endif + +/* ADC control register 1 */ + +#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ +#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) + +#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ +#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ +#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ +#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ +#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ +#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) + +#ifdef HAVE_BASIC_ADC +# define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */ +# define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT) +# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */ +# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */ +# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */ +# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */ +# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */ +# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */ +# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */ +# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */ +#endif + +#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ + +#ifndef HAVE_BASIC_ADC +# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ +# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) +# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles */ +# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles */ +# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */ +# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */ +# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ +# define ADC_CR1_RESERVED (0xfb3f0000) +#endif + +/* ADC control register 2 */ + +#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ +#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ +#ifdef HAVE_BASIC_ADC +# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */ +# define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */ +#endif +#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ +#ifndef HAVE_BASIC_ADC +# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ +# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ +#endif + +#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ + +#ifndef HAVE_BASIC_ADC + /* Bits 12-15: Reserved */ +# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ +# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */ +# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */ +# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */ +# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */ +# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */ +# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */ +# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */ +# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ +# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ +# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) +# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +# define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ + /* Bit 23: Reserved, must be kept at reset value. */ +# define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ +# define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ +# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ +# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */ +# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */ +# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */ +# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */ +# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ +# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ +# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) +# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ +# define ADC_CR2_RESERVED (0x8080f0fc) +#else /* HAVE_BASIC_ADC */ +# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */ +# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT) +# if defined(CONFIG_STM32_STM32F37XX) +# define ADC_CR2_JEXTSEL_T19CC1 (0 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_T19CC2 (1 << ADC_CR2_JEXTSEL_SHIFT) +# else +# define ADC_CR2_JEXTSEL_T1TRGO (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */ +# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */ +# endif +# define ADC_CR2_JEXTSEL_T2TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */ +# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */ +# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */ +# define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */ +# define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */ +# define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT) +# if defined(CONFIG_STM32_STM32F37XX) +# define ADC_CR2_EXTSEL_T19TRGO (0 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T19CC3 (1 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T19CC4 (2 << ADC_CR2_EXTSEL_SHIFT) +# else +# define ADC_CR2_EXTSEL_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */ +# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */ +# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */ +# endif +# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */ +# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */ +# define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */ +# define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */ +# define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */ +# define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */ +#endif + +/* ADC sample time register 1 */ + +#ifndef HAVE_BASIC_ADC +# define ADC_SMPR_3 0 /* 000: 3 cycles */ +# define ADC_SMPR_15 1 /* 001: 15 cycles */ +# define ADC_SMPR_28 2 /* 010: 28 cycles */ +# define ADC_SMPR_56 3 /* 011: 56 cycles */ +# define ADC_SMPR_84 4 /* 100: 84 cycles */ +# define ADC_SMPR_112 5 /* 101: 112 cycles */ +# define ADC_SMPR_144 6 /* 110: 144 cycles */ +# define ADC_SMPR_480 7 /* 111: 480 cycles */ +#else +# define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ +# define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */ +# define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */ +# define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */ +# define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */ +# define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */ +# define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */ +# define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */ +#endif + +#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) +#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) +#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) +#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) +#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) +#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) +#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) +#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) +#ifndef HAVE_BASIC_ADC +# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT) +#endif + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ +#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) +#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) +#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) +#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) +#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) +#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) +#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) +#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) +#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) +#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) + +/* ADC injected channel data offset register 1-4 */ + +#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ +#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) + +/* ADC watchdog high threshold register */ + +#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ +#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) + +/* ADC watchdog low threshold register */ + +#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ +#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ +#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) +#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ +#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) +#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ +#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) +#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ +#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) +#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_RESERVED (0xff000000) +#define ADC_SQR1_FIRST (13) +#define ADC_SQR1_LAST (16) +#define ADC_SQR1_SQ_OFFSET (0) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ +#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) +#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ +#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT ) +#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ +#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) +#define ADC_SQR2_RESERVED (0xc0000000) +#define ADC_SQR2_FIRST (7) +#define ADC_SQR2_LAST (12) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ +#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) +#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ +#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) +#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ +#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) +#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ +#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) +#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ +#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT ) +#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ +#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) +#define ADC_SQR3_RESERVED (0xc0000000) +#define ADC_SQR3_FIRST (1) +#define ADC_SQR3_LAST (6) +#define ADC_SQR3_SQ_OFFSET (0) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) + +/* ADC injected data register 1-4 */ + +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) +#ifdef HAVE_BASIC_ADC +# define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */ +# define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT) +#endif + +/* Common status register */ + +#ifndef HAVE_BASIC_ADC +# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ +# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ +# define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ +# define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ +# define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ +# define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ + /* Bits 6-7: Reserved, must be kept at reset value. */ + +# define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */ +# define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */ +# define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */ +# define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */ +# define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */ +# define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */ + /* Bits 14-15: Reserved, must be kept at reset value. */ +# define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */ +# define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */ +# define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */ +# define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */ +# define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */ +# define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */ + /* Bits 22-31: Reserved, must be kept at reset value. */ +#endif + +/* Common control register */ + +#ifndef HAVE_BASIC_ADC +# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ +# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT) +# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ + /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ +# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ + /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ +# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ + /* Bits 5-7: Reserved, must be kept at reset value. */ +# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) +# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ + /* Bit 12 Reserved, must be kept at reset value. */ +# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ + +# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ +# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT) +# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */ +# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */ +# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */ +# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */ + +# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ +# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) +# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */ +# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ +# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ +# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ + /* Bits 18-21: Reserved, must be kept at reset value. */ +# define ADC_CCR_VBATEN (1 << 22) /* Bit 22: VBAT enable */ +# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ + /* Bits 24-31 Reserved, must be kept at reset value. */ +#endif + +/* Data register for dual and triple modes (32-bit data with no named fields) */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Function Prototypes + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1_H */ diff --git a/arch/arm/src/stm32/chip/stm32_adc_v1l1.h b/arch/arm/src/stm32/chip/stm32_adc_v1l1.h new file mode 100644 index 0000000000..625790bed1 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32_adc_v1l1.h @@ -0,0 +1,563 @@ +/**************************************************************************************************** + * arch/arm/src/stm32/chip/stm32_adc_ipv1l1.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1L1_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1L1_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/* This is implementation for STM32 ADC IPv1 modified for L1 */ + +#define HAVE_IP_ADC_V1 +#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */ +#undef HAVE_BASIC_ADC /* No basic ADC */ +#undef HAVE_ADC_VBAT /* No VBAT channel */ + +/* Some families use HSI as clock-source for the ADC (L0, L1). + * NOTE: F0 use dedicated HSI14 clock which does not belong here. + */ + +#ifdef CONFIG_STM32_STM32L15XX +# define HAVE_ADC_CLOCK_HSI +#endif + +/* Power down functions for ADC (L1) */ + +#ifdef CONFIG_STM32_STM32L15XX +# define HAVE_ADC_POWERDOWN +#endif + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +#define STM32_ADC1_OFFSET 0x0000 +#define STM32_ADC2_OFFSET 0x0100 +#define STM32_ADC3_OFFSET 0x0200 +#define STM32_ADC_CMN_OFFSET 0x0300 + +#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC_BASE) /* ADC1 ADC */ +#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC_BASE) /* ADC2 ADC */ +#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC_BASE) /* ADC3 ADC */ +#define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET+STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */ + +/* Register Offsets *********************************************************************************/ + +#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ +#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ +#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ +#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ +#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ +#define STM32_ADC_SMPR3_OFFSET 0x0014 /* ADC sample time register 3 (32-bit) */ +#define STM32_ADC_JOFR1_OFFSET 0x0018 /* ADC injected channel data offset register 1 (32-bit) */ +#define STM32_ADC_JOFR2_OFFSET 0x001c /* ADC injected channel data offset register 2 (32-bit) */ +#define STM32_ADC_JOFR3_OFFSET 0x0020 /* ADC injected channel data offset register 3 (32-bit) */ +#define STM32_ADC_JOFR4_OFFSET 0x0024 /* ADC injected channel data offset register 4 (32-bit) */ +#define STM32_ADC_HTR_OFFSET 0x0028 /* ADC watchdog high threshold register (32-bit) */ +#define STM32_ADC_LTR_OFFSET 0x002c /* ADC watchdog low threshold register (32-bit) */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 (32-bit) */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 (32-bit) */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 (32-bit) */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 (32-bit) */ +#define STM32_ADC_SQR5_OFFSET 0x0040 /* ADC regular sequence register 5 (32-bit) */ +#define STM32_ADC_JSQR_OFFSET 0x0044 /* ADC injected sequence register (32-bit) */ +#define STM32_ADC_JDR1_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR2_OFFSET 0x004c /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR3_OFFSET 0x0050 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR4_OFFSET 0x0054 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_DR_OFFSET 0x0058 /* ADC regular data register (32-bit) */ +#define STM32_ADC_SMPR0_OFFSET 0X005c /* ADC sample time register 3 (32-bit) */ + +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ + +/* Register Addresses *******************************************************************************/ + +#if STM32_NADC > 0 +# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_SMPR3 (STM32_ADC1_BASE+STM32_ADC_SMPR3_OFFSET) +# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) +# define STM32_ADC1_SQR5 (STM32_ADC1_BASE+STM32_ADC_SQR5_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +# define STM32_ADC1_SMPR0 (STM32_ADC1_BASE+STM32_ADC_SMPR0_OFFSET) +#endif + +#if STM32_NADC > 1 +# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#endif + +#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* ADC status register */ + +#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ +#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ +#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ +#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ +#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ +#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ +#define ADC_SR_ADONS (1 << 6) /* Bit 6 : ADC ON status. Set and cleared by HW */ +#define ADC_SR_RCNR (1 << 8) /* Bit 8 : Regular channel not ready. Set and cleared by HW */ +#define ADC_SR_JCNR (1 << 9) /* Bit 9 : Injected channel not ready. Set and cleared by HW */ + +/* ADC control register 1 */ + +#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ +#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) + +#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ +#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ +#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ +#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ +#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ +#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) + +#define ADC_CR1_PDD (1 << 16) /* Bit 16 : Power down during the delay phase. This bit must be written only when ADON=0 */ +#define ADC_CR1_PDI (1 << 17) /* Bit 17 : Power down during the idle phase. This bit must + * be written only when ADON=0 */ +#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ +#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) +# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 12 ADCCLK cycles */ +# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */ +# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */ +# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 7 ADCCLK cycles */ +#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ +#define ADC_CR1_RESERVED (0xfb3f0000) + +/* ADC control register 2 */ + +#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ +#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ +#define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no + * conversion is on going. This bit is available in high and medium+ + * density devices only. + */ +#define ADC_CR2_DELS_SHIFT (4) /* Bits 2-0: Delay selection */ +#define ADC_CR2_DELS_MASK (0x07 << ADC_CR2_DELS_SHIFT) +#define ADC_CR2_DELS_NODEL (0x0 << ADC_CR2_DELS_SHIFT) /* No delay */ +#define ADC_CR2_DELS_TILLRD (0x01 << ADC_CR2_DELS_SHIFT) /* Until the converted data have been read */ +#define ADC_CR2_DELS_APB7 (0x02 << ADC_CR2_DELS_SHIFT) /* 7 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB15 (0x03 << ADC_CR2_DELS_SHIFT) /* 15 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB31 (0x04 << ADC_CR2_DELS_SHIFT) /* 31 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB63 (0x05 << ADC_CR2_DELS_SHIFT) /* 63 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB127 (0x06 << ADC_CR2_DELS_SHIFT) /* 127 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB255 (0x07 << ADC_CR2_DELS_SHIFT) /* 255 APB clock cycles after the end of conversion */ +#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ +#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ +#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ +#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ + /* Bits 12-15: Reserved */ +#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ +#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */ +# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/ +# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */ +# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ +#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ +#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) +# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ +#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ + /* Bit 23: Reserved, must be kept at reset value. */ +#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ +#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */ +# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */ +# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ +#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ +#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) +# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ +#define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ +#define ADC_CR2_RESERVED (0x8080f0fc) + +/* ADC sample time register 1 */ + +#define ADC_SMPR_4 0 /* 000: 3 cycles */ +#define ADC_SMPR_9 1 /* 001: 9 cycles */ +#define ADC_SMPR_16 2 /* 010: 16 cycles */ +#define ADC_SMPR_24 3 /* 011: 24 cycles */ +#define ADC_SMPR_48 4 /* 100: 48 cycles */ +#define ADC_SMPR_96 5 /* 101: 96 cycles */ +#define ADC_SMPR_192 6 /* 110: 192 cycles */ +#define ADC_SMPR_384 7 /* 111: 384 cycles */ + +#define ADC_SMPR1_SMP20_SHIFT (0) /* Bits 0-2: Channel 20 Sample time selection */ +#define ADC_SMPR1_SMP20_MASK (7 << ADC_SMPR1_SMP20_SHIFT) +#define ADC_SMPR1_SMP21_SHIFT (3) /* Bits 3-5: Channel 21 Sample time selection */ +#define ADC_SMPR1_SMP21_MASK (7 << ADC_SMPR1_SMP21_SHIFT) +#define ADC_SMPR1_SMP22_SHIFT (6) /* Bits 6-8: Channel 22 Sample time selection */ +#define ADC_SMPR1_SMP22_MASK (7 << ADC_SMPR1_SMP22_SHIFT) +#define ADC_SMPR1_SMP23_SHIFT (9) /* Bits 9-11: Channel 23 Sample time selection */ +#define ADC_SMPR1_SMP23_MASK (7 << ADC_SMPR1_SMP23_SHIFT) +#define ADC_SMPR1_SMP24_SHIFT (12) /* Bits 12-14: Channel 24 Sample time selection */ +#define ADC_SMPR1_SMP24_MASK (7 << ADC_SMPR1_SMP24_SHIFT) +#define ADC_SMPR1_SMP25_SHIFT (15) /* Bits 15-17: Channel 25 Sample time selection */ +#define ADC_SMPR1_SMP25_MASK (7 << ADC_SMPR1_SMP25_SHIFT) +#define ADC_SMPR1_SMP26_SHIFT (18) /* Bits 18-20: Channel 26 Sample time selection */ +#define ADC_SMPR1_SMP26_MASK (7 << ADC_SMPR1_SMP26_SHIFT) +#define ADC_SMPR1_SMP27_SHIFT (21) /* Bits 21-23: Channel 27 Sample time selection */ +#define ADC_SMPR1_SMP27_MASK (7 << ADC_SMPR1_SMP27_SHIFT) +#define ADC_SMPR1_SMP28_SHIFT (24) /* Bits 24-26: Channel 28 Sample time selection */ +#define ADC_SMPR1_SMP28_MASK (7 << ADC_SMPR1_SMP28_SHIFT) +#define ADC_SMPR1_SMP29_SHIFT (27) /* Bits 27-29: Channel 29 Sample time selection */ +#define ADC_SMPR1_SMP29_MASK (7 << ADC_SMPR1_SMP29_SHIFT) + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) +#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) +#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) +#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) +#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) +#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) +#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) +#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) +#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) +#define ADC_SMPR2_SMP19_SHIFT (27) /* Bits 27-29: Channel 18 Sample time selection */ +#define ADC_SMPR2_SMP19_MASK (7 << ADC_SMPR2_SMP19_SHIFT) + +/* ADC sample time register 3 */ + +#define ADC_SMPR3_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ +#define ADC_SMPR3_SMP0_MASK (7 << ADC_SMPR3_SMP0_SHIFT) +#define ADC_SMPR3_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR3_SMP1_MASK (7 << ADC_SMPR3_SMP1_SHIFT) +#define ADC_SMPR3_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR3_SMP2_MASK (7 << ADC_SMPR3_SMP2_SHIFT) +#define ADC_SMPR3_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR3_SMP3_MASK (7 << ADC_SMPR3_SMP3_SHIFT) +#define ADC_SMPR3_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR3_SMP4_MASK (7 << ADC_SMPR3_SMP4_SHIFT) +#define ADC_SMPR3_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR3_SMP5_MASK (7 << ADC_SMPR3_SMP5_SHIFT) +#define ADC_SMPR3_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR3_SMP6_MASK (7 << ADC_SMPR3_SMP6_SHIFT) +#define ADC_SMPR3_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR3_SMP7_MASK (7 << ADC_SMPR3_SMP7_SHIFT) +#define ADC_SMPR3_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR3_SMP8_MASK (7 << ADC_SMPR3_SMP8_SHIFT) +#define ADC_SMPR3_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR3_SMP9_MASK (7 << ADC_SMPR3_SMP9_SHIFT) + +/* ADC sample time register 0 */ + +#define ADC_SMPR0_SMP30_SHIFT (0) /* Bits 2-0: Channel 30 Sample time selection */ +#define ADC_SMPR0_SMP30_MASK (7 << ADC_SMPR3_SMP30_SHIFT) +#define ADC_SMPR0_SMP31_SHIFT (3) /* Bits 5-3: Channel 31 Sample time selection */ +#define ADC_SMPR0_SMP31_MASK (7 << ADC_SMPR3_SMP31_SHIFT) + +/* ADC injected channel data offset register 1-4 */ + +#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ +#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) + +/* ADC watchdog high threshold register */ + +#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ +#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) + +/* ADC watchdog low threshold register */ + +#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ +#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */ +#define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT) +#define ADC_SQR1_SQ26_SHIFT (5) /* Bits 9-5: 26th conversion in regular sequence */ +#define ADC_SQR1_SQ26_MASK (0x1f << ADC_SQR1_SQ26_SHIFT) +#define ADC_SQR1_SQ27_SHIFT (10) /* Bits 14-10: 27th conversion in regular sequence */ +#define ADC_SQR1_SQ27_MASK (0x1f << ADC_SQR1_SQ27_SHIFT) +#define ADC_SQR1_SQ28_SHIFT (15) /* Bits 19-15: 28th conversion in regular sequence */ +#define ADC_SQR1_SQ28_MASK (0x1f << ADC_SQR1_SQ28_SHIFT) +#define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_RESERVED (0xff000000) +#define ADC_SQR1_FIRST (25) +#define ADC_SQR1_LAST (28) +#define ADC_SQR1_SQ_OFFSET (0) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */ +#define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT) +#define ADC_SQR2_SQ20_SHIFT (5) /* Bits 9-5: 20th conversion in regular sequence */ +#define ADC_SQR2_SQ20_MASK (0x1f << ADC_SQR2_SQ20_SHIFT) +#define ADC_SQR2_SQ21_SHIFT (10) /* Bits 14-10: 21th conversion in regular sequence */ +#define ADC_SQR2_SQ21_MASK (0x1f << ADC_SQR2_SQ21_SHIFT) +#define ADC_SQR2_SQ22_SHIFT (15) /* Bits 19-15: 22th conversion in regular sequence */ +#define ADC_SQR2_SQ22_MASK (0x1f << ADC_SQR2_SQ22_SHIFT) +#define ADC_SQR2_SQ23_SHIFT (20) /* Bits 24-20: 23th conversion in regular sequence */ +#define ADC_SQR2_SQ23_MASK (0x1f << ADC_SQR2_SQ23_SHIFT ) +#define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */ +#define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT) +#define ADC_SQR2_RESERVED (0xc0000000) +#define ADC_SQR2_FIRST (19) +#define ADC_SQR2_LAST (24) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) +#define ADC_SQR3_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) +#define ADC_SQR3_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ +#define ADC_SQR3_SQ15_MASK (0x1f << ADC_SQR3_SQ15_SHIFT) +#define ADC_SQR3_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ +#define ADC_SQR3_SQ16_MASK (0x1f << ADC_SQR3_SQ16_SHIFT) +#define ADC_SQR3_SQ17_SHIFT (20) /* Bits 24-20: 17th conversion in regular sequence */ +#define ADC_SQR3_SQ17_MASK (0x1f << ADC_SQR3_SQ17_SHIFT ) +#define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */ +#define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT) +#define ADC_SQR3_RESERVED (0xc0000000) +#define ADC_SQR3_FIRST (13) +#define ADC_SQR3_LAST (18) +#define ADC_SQR3_SQ_OFFSET (0) + +/* ADC regular sequence register 4 */ + +#define ADC_SQR4_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ +#define ADC_SQR4_SQ7_MASK (0x1f << ADC_SQR4_SQ7_SHIFT) +#define ADC_SQR4_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ +#define ADC_SQR4_SQ8_MASK (0x1f << ADC_SQR4_SQ8_SHIFT) +#define ADC_SQR4_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ +#define ADC_SQR4_SQ9_MASK (0x1f << ADC_SQR4_SQ9_SHIFT) +#define ADC_SQR4_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ +#define ADC_SQR4_SQ10_MASK (0x1f << ADC_SQR4_SQ10_SHIFT) +#define ADC_SQR4_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ +#define ADC_SQR4_SQ11_MASK (0x1f << ADC_SQR4_SQ11_SHIFT ) +#define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ +#define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT) +#define ADC_SQR4_RESERVED (0xc0000000) +#define ADC_SQR4_FIRST (7) +#define ADC_SQR4_LAST (12) +#define ADC_SQR4_SQ_OFFSET (0) + +/* ADC regular sequence register 5 */ + +#define ADC_SQR5_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ +#define ADC_SQR5_SQ1_MASK (0x1f << ADC_SQR5_SQ1_SHIFT) +#define ADC_SQR5_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ +#define ADC_SQR5_SQ2_MASK (0x1f << ADC_SQR5_SQ2_SHIFT) +#define ADC_SQR5_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ +#define ADC_SQR5_SQ3_MASK (0x1f << ADC_SQR5_SQ3_SHIFT) +#define ADC_SQR5_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ +#define ADC_SQR5_SQ4_MASK (0x1f << ADC_SQR5_SQ4_SHIFT) +#define ADC_SQR5_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ +#define ADC_SQR5_SQ5_MASK (0x1f << ADC_SQR5_SQ5_SHIFT ) +#define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ +#define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT) +#define ADC_SQR5_RESERVED (0xc0000000) +#define ADC_SQR5_FIRST (1) +#define ADC_SQR5_LAST (6) +#define ADC_SQR5_SQ_OFFSET (0) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) + +/* ADC injected data register 1-4 */ + +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* Common status register */ + +#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ +#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ +#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ +#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ +#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ +#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ + /* Bits 6-7: Reserved, must be kept at reset value. */ +#define ADC_CSR_ADONS1 (1 << 6) /* Bit 6: ADON Status of ADC1. This bit is a copy of the ADONS bit in the ADC_SR register. */ + +/* Common control register */ + + /* Bits 15-0: Reserved, must be kept at reset value */ +#define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ +#define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) +# define ADC_CCR_ADCPRE_DIV1 (0 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 1 */ +# define ADC_CCR_ADCPRE_DIV2 (1 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 2 */ +# define ADC_CCR_ADCPRE_DIV4 (2 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 4 */ + /* 11: Reserved */ + /* Bits 22-18: Reserved, must be kept at reset value */ +#define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ + /* Bits 31-24: Reserved, must be kept at reset value */ + +/* Data register for dual and triple modes (32-bit data with no named fields) */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Function Prototypes + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV1L1_H */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h b/arch/arm/src/stm32/chip/stm32_adc_v2.h similarity index 59% rename from arch/arm/src/stm32/chip/stm32f33xxx_adc.h rename to arch/arm/src/stm32/chip/stm32_adc_v2.h index 4d10780c05..1ab3a42bbe 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h +++ b/arch/arm/src/stm32/chip/stm32_adc_v2.h @@ -1,9 +1,9 @@ /**************************************************************************************************** - * arch/arm/src/stm32/chip/stm32f33xxx_adc.h + * arch/arm/src/stm32/chip/stm32_adc_ipv2.h * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F334 by Mateusz Szafoni + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mateusz Szafoni * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -34,8 +34,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_ADC_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_ADC_H +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV2_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV2_H /**************************************************************************************************** * Included Files @@ -45,24 +45,65 @@ #include "chip.h" +/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), H7, L0, L4, L4+ */ + +#define HAVE_IP_ADC_V2 +#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */ +#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ +#undef HAVE_ADC_POWERDOWN /* No ADC power down */ +#define HAVE_ADC_VBAT /* VBAT channel support */ + +/* F0 and L0 have basic version of ADC hardware (not present here for now): + * - channel selection register (CHSELR) + * - sampling time configuration common for all channels + * - one TR register + * - no SQR registers + * - ... + * + * TODO: definitions for basic STM32 ADC IPv2 (F0, L0) + */ + +#ifdef CONFIG_STM32_HAVE_IP_ADC_V2_BASIC +# define HAVE_BASIC_ADC +# error TODO +#else +# undef HAVE_BASIC_ADC +#endif + +/* F30X and F33x dont have CFGR2 register */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# undef HAVE_ADC_CFGR2 +#else +# define HAVE_ADC_CFGR2 +#endif + /**************************************************************************************************** * Pre-processor Definitions ****************************************************************************************************/ #define STM32_ADC1_OFFSET 0x0000 #define STM32_ADC2_OFFSET 0x0100 -#define STM32_ADC12_CMN_OFFSET 0x0300 +#define STM32_ADC3_OFFSET 0x0000 +#define STM32_ADC4_OFFSET 0x0100 +#define STM32_ADCCMN_OFFSET 0x0300 #define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */ #define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */ -#define STM32_ADC12_CMN_BASE (STM32_ADC12_CMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */ +#define STM32_ADC3_BASE (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */ +#define STM32_ADC4_BASE (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */ +#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */ +#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */ /* Register Offsets *********************************************************************************/ #define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ #define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ #define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ +#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ +#ifdef HAVE_ADC_CFGR2 +# define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#endif #define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ #define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ #define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ @@ -95,65 +136,149 @@ /* Register Addresses *******************************************************************************/ -#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET) -#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET) -#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET) -#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET) -#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) -#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) -#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET) -#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET) -#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET) -#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) -#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) -#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) -#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) -#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) -#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) -#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET) -#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET) -#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET) -#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET) -#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) -#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) -#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) -#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) -#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET) -#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET) -#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET) -#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET) +#if STM32_NADC > 0 +# define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET) +# define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET) +# define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET) +# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE+STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET) +# define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET) +# define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET) +# define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET) +# define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET) +# define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET) +#endif -#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET) -#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET) -#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET) -#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET) -#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) -#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) -#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET) -#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET) -#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET) -#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) -#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) -#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) -#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET) -#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) -#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) -#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET) -#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET) -#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET) -#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET) -#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) -#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) -#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) -#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) -#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET) -#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET) -#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) -#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) +#if STM32_NADC > 1 +# define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET) +# define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET) +# define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET) +# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE+STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET) +# define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET) +# define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET) +# define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET) +# define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET) +# define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) +#endif -#define STM32_ADC12_CSR (STM32_ADC12_CMN_BASE+STM32_ADC_CSR_OFFSET) -#define STM32_ADC12_CCR (STM32_ADC12_CMN_BASE+STM32_ADC_CCR_OFFSET) -#define STM32_ADC12_CDR (STM32_ADC12_CMN_BASE+STM32_ADC_CDR_OFFSET) +#if STM32_NADC > 2 +# define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET) +# define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET) +# define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET) +# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE+STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET) +# define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET) +# define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET) +# define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET) +# define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET) +# define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET) +#endif + +#if STM32_NADC > 3 +# define STM32_ADC4_ISR (STM32_ADC4_BASE+STM32_ADC_ISR_OFFSET) +# define STM32_ADC4_IER (STM32_ADC4_BASE+STM32_ADC_IER_OFFSET) +# define STM32_ADC4_CR (STM32_ADC4_BASE+STM32_ADC_CR_OFFSET) +# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE+STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE+STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC4_TR1 (STM32_ADC4_BASE+STM32_ADC_TR1_OFFSET) +# define STM32_ADC4_TR2 (STM32_ADC4_BASE+STM32_ADC_TR2_OFFSET) +# define STM32_ADC4_TR3 (STM32_ADC4_BASE+STM32_ADC_TR3_OFFSET) +# define STM32_ADC4_SQR1 (STM32_ADC4_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC4_SQR2 (STM32_ADC4_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC4_SQR3 (STM32_ADC4_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC4_SQR4 (STM32_ADC4_BASE+STM32_ADC_SQR4_OFFSET) +# define STM32_ADC4_DR (STM32_ADC4_BASE+STM32_ADC_DR_OFFSET) +# define STM32_ADC4_JSQR (STM32_ADC4_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC4_OFR1 (STM32_ADC4_BASE+STM32_ADC_OFR1_OFFSET) +# define STM32_ADC4_OFR2 (STM32_ADC4_BASE+STM32_ADC_OFR2_OFFSET) +# define STM32_ADC4_OFR3 (STM32_ADC4_BASE+STM32_ADC_OFR3_OFFSET) +# define STM32_ADC4_OFR4 (STM32_ADC4_BASE+STM32_ADC_OFR4_OFFSET) +# define STM32_ADC4_JDR1 (STM32_ADC4_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC4_JDR2 (STM32_ADC4_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC4_JDR3 (STM32_ADC4_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC4_JDR4 (STM32_ADC4_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE+STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE+STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE+STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC4_CALFACT (STM32_ADC4_BASE+STM32_ADC_CALFACT_OFFSET) +#endif + +#if STM32_NADC > 0 +# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE+STM32_ADC_CSR_OFFSET) +# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE+STM32_ADC_CCR_OFFSET) +# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE+STM32_ADC_CDR_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC34_CSR (STM32_ADC34CMN_BASE+STM32_ADC_CSR_OFFSET) +# define STM32_ADC34_CCR (STM32_ADC34CMN_BASE+STM32_ADC_CCR_OFFSET) +# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE+STM32_ADC_CDR_OFFSET) +#endif /* Register Bitfield Definitions ********************************************************************/ /* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ @@ -186,57 +311,92 @@ #define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ #define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ -/* ADC configuration register */ +/* ADC configuration register 1 */ -#define ADC_CFGR_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ -#define ADC_CFGR_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ -#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */ -#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT) -# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK cycles */ -# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 13 ADCCLK cycles */ -# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 11 ADCCLK cycles */ -# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 9 ADCCLK cycles */ -#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */ -#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ -#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1CC1 (0 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1CC2 (1 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T2CC2 (3 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T3TRGO (4 << ADC_CFGR_EXTSEL_SHIFT) - /* 0101: Reserved */ -# define ADC12_CFGR_EXTSEL_EXTI11 (6 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ -# define ADC12_CFGR_EXTSEL_HRT1TRG1 (7 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: HRTIM1 ADCTRG1 event */ -# define ADC12_CFGR_EXTSEL_HRT1TRG3 (8 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: HRTIM1 ADCTRG3 event */ -# define ADC12_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1TRGO2 (10 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T2TRGO (11 << ADC_CFGR_EXTSEL_SHIFT) +#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ +#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ +#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ +#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT) +# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK cycles */ +# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK cycles */ +# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK cycles */ +# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK cycles */ +#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ +#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ +#define ADC_CFGR1_EXTSEL_MASK (15 << ADC_CFGR1_EXTSEL_SHIFT) +#if defined(CONFIG_STM32_STM32F33XX) +# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) + /* 0101: Reserved */ +# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ +# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (7 << ADC_CFGR1_EXTSEL_SHIFT) /* 0111: HRTIM1 ADCTRG1 event */ +# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (8 << ADC_CFGR1_EXTSEL_SHIFT) /* 1000: HRTIM1 ADCTRG3 event */ +# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) /* 1100: Reserved */ -# define ADC12_CFGR_EXTSEL_T6TRGO (13 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T3CC4 (15 << ADC_CFGR_EXTSEL_SHIFT) -#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ -#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT) -# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */ -# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */ -# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */ -# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */ -#define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ -#define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ -#define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ -#define ADC_CFGR_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ -#define ADC_CFGR_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */ -#define ADC_CFGR_DISCNUM_MASK (7 << ADC_CFGR_DISCNUM_SHIFT) -# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT) /* n = 1..8 channels */ -#define ADC_CFGR_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */ -#define ADC_CFGR_JQM (1 << 21) /* Bit 21: JSQR queue mode */ -#define ADC_CFGR_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ -#define ADC_CFGR_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */ -#define ADC_CFGR_JAWD1EN (1 << 22) /* Bit 22: Analog watchdog enable 1 injected channels */ -#define ADC_CFGR_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */ -#define ADC_CFGR_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ -#define ADC_CFGR_AWD1CH_MASK (31 << ADC_CFGR_AWD1CH_SHIFT) -# define ADC_CFGR_AWD1CH_DISABLED (0 << ADC_CFGR_AWD1CH_SHIFT) +# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) +#elif defined(CONFIG_STM32_STM32F30XX) +# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T3TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T7TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) +#else +# error TODO EXTSEL +#endif +#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ +#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT) +# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ +# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ +# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ +# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ +#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ +#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ +#define ADC_CFGR1_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ +#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ +#define ADC_CFGR1_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_MASK (7 << ADC_CFGR1_DISCNUM_SHIFT) +# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << ADC_CFGR1_DISCNUM_SHIFT) /* n = 1..8 channels */ +#define ADC_CFGR1_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */ +#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */ +#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ +#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */ +#define ADC_CFGR1_JAWD1EN (1 << 22) /* Bit 22: Analog watchdog enable 1 injected channels */ +#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */ +#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ +#define ADC_CFGR1_AWD1CH_MASK (31 << ADC_CFGR1_AWD1CH_SHIFT) +# define ADC_CFGR1_AWD1CH_DISABLED (0 << ADC_CFGR1_AWD1CH_SHIFT) + +/* TODO: ADC configuration register 2 */ /* ADC sample time register 1 */ @@ -388,6 +548,7 @@ # define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ #define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ #define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) +#if defined(CONFIG_STM32_STM32F33XX) # define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) @@ -404,6 +565,38 @@ # define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +#elif defined(CONFIG_STM32_STM32F30XX) +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +#else +# error TODO JEXTSEL +#endif # define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */ # define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT) # define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ @@ -539,4 +732,4 @@ * Public Function Prototypes ****************************************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_ADC_H */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_IPV2_H */ diff --git a/arch/arm/src/stm32/chip/stm32_tim.h b/arch/arm/src/stm32/chip/stm32_tim.h index e249cb18c6..1f91e5c2d3 100644 --- a/arch/arm/src/stm32/chip/stm32_tim.h +++ b/arch/arm/src/stm32/chip/stm32_tim.h @@ -59,8 +59,12 @@ - 4-bit SMS in SMCR register */ -#ifdef CONFIG_STM32_HAVE_IP_TIMERS_V2 +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) # define HAVE_IP_TIMERS_V2 +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) +# define HAVE_IP_TIMERS_V1 +#else +# error "STM32 TIMER IP version not specified" #endif /* TIM16 has OR register (F3/L4) */ diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h index b1b4f41c34..4125a260c9 100644 --- a/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h @@ -156,10 +156,6 @@ #define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */ #define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */ #define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1-3 */ -# define STM32_ADC1_BASE 0x40012000 /* ADC1 */ -# define STM32_ADC2_BASE 0x40012100 /* ADC2 */ -# define STM32_ADC3_BASE 0x40012200 /* ADC3 */ -# define STM32_ADCCMN_BASE 0x40012300 /* Common */ #define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDIO */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */ #define STM32_SYSCFG_BASE 0x40013800 /* 0x40013800-0x40013bff: SYSCFG */ diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h deleted file mode 100644 index c9d2687301..0000000000 --- a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h +++ /dev/null @@ -1,620 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/stm32/chip/stm32f30xxx_adc.h - * - * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_ADC_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_ADC_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ - -/* Register Offsets *********************************************************************************/ -/* Register Offsets for Each ADC (ADC1, 2, 3, and 4). At offset 0x0000 for master and offset 0x0100 - * for slave. - */ - -#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ -#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ -#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ -#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ -#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ -#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ -#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ -#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ -#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ -#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ -#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ -#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ -#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ -#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC data offset register 4 */ -#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ -#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ -#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ -#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ -#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ -#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ -#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ - -/* Master and Slave ADC Common Registers */ - -#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ -#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ - -/* Register Addresses *******************************************************************************/ - -#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET) -#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET) -#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET) -#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET) -#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) -#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) -#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET) -#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET) -#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET) -#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) -#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) -#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) -#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) -#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) -#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) -#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET) -#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET) -#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET) -#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET) -#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) -#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) -#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) -#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) -#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET) -#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET) -#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET) -#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET) - -#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET) -#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET) -#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET) -#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET) -#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) -#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) -#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET) -#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET) -#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET) -#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) -#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) -#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) -#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET) -#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) -#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) -#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET) -#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET) -#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET) -#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET) -#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) -#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) -#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) -#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) -#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET) -#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET) -#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) -#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) - -#define STM32_ADC12_CSR (STM32_ADC12_BASE+STM32_ADC_CSR_OFFSET) -#define STM32_ADC12_CCR (STM32_ADC12_BASE+STM32_ADC_CCR_OFFSET) -#define STM32_ADC12_CDR (STM32_ADC12_BASE+STM32_ADC_CDR_OFFSET) - -#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET) -#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET) -#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET) -#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET) -#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) -#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) -#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET) -#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET) -#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET) -#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) -#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) -#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) -#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET) -#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) -#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) -#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET) -#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET) -#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET) -#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET) -#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) -#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) -#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) -#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) -#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET) -#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET) -#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET) -#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET) - -#define STM32_ADC4_ISR (STM32_ADC4_BASE+STM32_ADC_ISR_OFFSET) -#define STM32_ADC4_IER (STM32_ADC4_BASE+STM32_ADC_IER_OFFSET) -#define STM32_ADC4_CR (STM32_ADC4_BASE+STM32_ADC_CR_OFFSET) -#define STM32_ADC4_CFGR (STM32_ADC4_BASE+STM32_ADC_CFGR_OFFSET) -#define STM32_ADC4_SMPR1 (STM32_ADC4_BASE+STM32_ADC_SMPR1_OFFSET) -#define STM32_ADC4_SMPR2 (STM32_ADC4_BASE+STM32_ADC_SMPR2_OFFSET) -#define STM32_ADC4_TR1 (STM32_ADC4_BASE+STM32_ADC_TR1_OFFSET) -#define STM32_ADC4_TR2 (STM32_ADC4_BASE+STM32_ADC_TR2_OFFSET) -#define STM32_ADC4_TR3 (STM32_ADC4_BASE+STM32_ADC_TR3_OFFSET) -#define STM32_ADC4_SQR1 (STM32_ADC4_BASE+STM32_ADC_SQR1_OFFSET) -#define STM32_ADC4_SQR2 (STM32_ADC4_BASE+STM32_ADC_SQR2_OFFSET) -#define STM32_ADC4_SQR3 (STM32_ADC4_BASE+STM32_ADC_SQR3_OFFSET) -#define STM32_ADC4_SQR4 (STM32_ADC4_BASE+STM32_ADC_SQR4_OFFSET) -#define STM32_ADC4_DR (STM32_ADC4_BASE+STM32_ADC_DR_OFFSET) -#define STM32_ADC4_JSQR (STM32_ADC4_BASE+STM32_ADC_JSQR_OFFSET) -#define STM32_ADC4_OFR1 (STM32_ADC4_BASE+STM32_ADC_OFR1_OFFSET) -#define STM32_ADC4_OFR2 (STM32_ADC4_BASE+STM32_ADC_OFR2_OFFSET) -#define STM32_ADC4_OFR3 (STM32_ADC4_BASE+STM32_ADC_OFR3_OFFSET) -#define STM32_ADC4_OFR4 (STM32_ADC4_BASE+STM32_ADC_OFR4_OFFSET) -#define STM32_ADC4_JDR1 (STM32_ADC4_BASE+STM32_ADC_JDR1_OFFSET) -#define STM32_ADC4_JDR2 (STM32_ADC4_BASE+STM32_ADC_JDR2_OFFSET) -#define STM32_ADC4_JDR3 (STM32_ADC4_BASE+STM32_ADC_JDR3_OFFSET) -#define STM32_ADC4_JDR4 (STM32_ADC4_BASE+STM32_ADC_JDR4_OFFSET) -#define STM32_ADC4_AWD2CR (STM32_ADC4_BASE+STM32_ADC_AWD2CR_OFFSET) -#define STM32_ADC4_AWD3CR (STM32_ADC4_BASE+STM32_ADC_AWD3CR_OFFSET) -#define STM32_ADC4_DIFSEL (STM32_ADC4_BASE+STM32_ADC_DIFSEL_OFFSET) -#define STM32_ADC4_CALFACT (STM32_ADC4_BASE+STM32_ADC_CALFACT_OFFSET) - -#define STM32_ADC34_CSR (STM32_ADC34_BASE+STM32_ADC_CSR_OFFSET) -#define STM32_ADC34_CCR (STM32_ADC34_BASE+STM32_ADC_CCR_OFFSET) -#define STM32_ADC34_CDR (STM32_ADC34_BASE+STM32_ADC_CDR_OFFSET) - -/* Register Bitfield Definitions ********************************************************************/ -/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ - -#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ -#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ -#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ -#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ -#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ -#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */ -#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */ -#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */ -#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */ -#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */ -#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */ - -/* ADC control register */ - -#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ -#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ -#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ -#define ADC_CR_JADSTART (1 << 3) /* Bit 3: ADC start of injected conversion */ -#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ -#define ADC_CR_JADSTP (1 << 5) /* Bit 5: ADC stop of injected conversion command */ -#define ADC_CR_ADVREGEN_SHIFT (28) /* Bits 28-29: ADC voltage regulator enable */ -#define ADC_CR_ADVREGEN_MASK (3 << ADC_CR_ADVREGEN_SHIFT) -# define ADC_CR_ADVREGEN_INTER (0 << ADC_CR_ADVREGEN_SHIFT) /* Intermediate state */ -# define ADC_CR_ADVREGEN_ENABLED (1 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator enabled */ -# define ADC_CR_ADVREGEN_DISABLED (2 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator disabled */ -#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ -#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ - -/* ADC configuration register */ - -#define ADC_CFGR_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ -#define ADC_CFGR_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ -#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */ -#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT) -# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */ -# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 13 ADCCLK clyes */ -# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 11 ADCCLK clyes */ -# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 9 ADCCLK clyes */ -#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */ -#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ -#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1CC1 (0 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1CC2 (1 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T2CC2 (3 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T3TRGO (4 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T4CC4 (5 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_EXTI11 (6 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ -# define ADC12_CFGR_EXTSEL_T8TRGO (7 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T2TRGO (11 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T6TRGO (13 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC12_CFGR_EXTSEL_T3CC4 (15 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T3CC1 (0 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T2CC3 (1 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T8CC1 (3 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T8TRGO (4 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T20TRGO (5 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T4CC1 (6 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T2TRGO (7 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T3TRGO (11 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T7TRGO (13 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC34_CFGR_EXTSEL_T2CC1 (15 << ADC_CFGR_EXTSEL_SHIFT) -#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ -#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT) -# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */ -# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */ -# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */ -# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */ -#define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ -#define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ -#define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ -#define ADC_CFGR_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ -#define ADC_CFGR_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */ -#define ADC_CFGR_DISCNUM_MASK (7 << ADC_CFGR_DISCNUM_SHIFT) -# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT) /* n = 1..8 channels */ -#define ADC_CFGR_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */ -#define ADC_CFGR_JQM (1 << 21) /* Bit 21: JSQR queue mode */ -#define ADC_CFGR_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ -#define ADC_CFGR_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */ -#define ADC_CFGR_JAWD1EN (1 << 22) /* Bit 22: Analog watchdog enable 1 injected channels */ -#define ADC_CFGR_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */ -#define ADC_CFGR_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ -#define ADC_CFGR_AWD1CH_MASK (31 << ADC_CFGR_AWD1CH_SHIFT) -# define ADC_CFGR_AWD1CH_DISABLED (0 << ADC_CFGR_AWD1CH_SHIFT) - -/* ADC sample time register 1 */ - -#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ -#define ADC_SMPR_2p5 1 /* 001: 2.5 cycles */ -#define ADC_SMPR_4p5 2 /* 010: 4.5 cycles */ -#define ADC_SMPR_7p5 3 /* 011: 7.5 cycles */ -#define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */ -#define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */ -#define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */ -#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */ - -#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -#define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT) -#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -#define ADC_SMPR1_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT) -#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -#define ADC_SMPR1_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT) -#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -#define ADC_SMPR1_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT) -#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -#define ADC_SMPR1_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT) -#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -#define ADC_SMPR1_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT) -#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -#define ADC_SMPR1_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT) -#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -#define ADC_SMPR1_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT) -#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -#define ADC_SMPR1_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT) - -/* ADC sample time register 2 */ - -#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) -#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) -#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) -#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) -#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) -#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) -#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) -#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) -#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) - -/* ADC watchdog threshold register 1 */ - -#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */ -#define ADC_TR1_LT_MASK (0x0fff << ADC_TR1_LT_SHIFT) -#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */ -#define ADC_TR1_HT_MASK (0x0fff << ADC_TR1_HT_SHIFT) - -/* ADC watchdog threshold register 2 */ - -#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */ -#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT) -#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */ -#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT) - -/* ADC watchdog threshold register 3 */ - -#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */ -#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT) -#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ -#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) - -/* Offset between SQ bits */ - -#define ADC_SQ_OFFSET (6) - -/* ADC regular sequence register 1 */ - -#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) -#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 13th conversion in regular sequence */ -#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT) -#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */ -#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT) -#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */ -#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) -#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ -#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) -#define ADC_SQR1_RESERVED (0xe0820830) -#define ADC_SQR1_FIRST (1) -#define ADC_SQR1_LAST (4) -#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET) - -/* ADC regular sequence register 2 */ - -#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 4-0: 5th conversion in regular sequence */ -#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT) -#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */ -#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT) -#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -#define ADC_SQR2_RESERVED (0xe0820820) -#define ADC_SQR2_FIRST (5) -#define ADC_SQR2_LAST (9) -#define ADC_SQR2_SQ_OFFSET (0) - -/* ADC regular sequence register 3 */ - -#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 4-0: 10th conversion in regular sequence */ -#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT) -#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */ -#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT) -#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */ -#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT) -#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ -#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) -#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) -#define ADC_SQR3_RESERVED (0xe0820820) -#define ADC_SQR3_FIRST (10) -#define ADC_SQR3_LAST (14) -#define ADC_SQR3_SQ_OFFSET (0) - -/* ADC regular sequence register 4 */ - -#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */ -#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) -#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ -#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) -#define ADC_SQR4_RESERVED (0xfffff820) -#define ADC_SQR4_FIRST (15) -#define ADC_SQR4_LAST (16) -#define ADC_SQR4_SQ_OFFSET (0) - -/* ADC regular data register */ - -#define ADC_DR_RDATA_SHIFT (0) -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/* ADC injected sequence register */ - -#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) -# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ -#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ -#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */ -# define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT) -# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_JSQR_JEXTEN_RISING (1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_JSQR_JEXTEN_FALLING (2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_JSQR_JEXTEN_BOTH (3 << ADC_JSQR_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ -#define ADC_JSQR_JSQ1_SHIFT (8) /* Bits 8-12: 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK) -# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_MASK) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ4_SHIFT (26) /* Bits 26-30: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT) /* Channel number 1..18 */ - -/* ADC offset register 1, 2, 3, and 4 */ - -#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */ -#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT) -# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT) -#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */ -#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT) -# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT) -#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */ - -/* ADC injected data register 1, 2, 3, and 4 */ - -#define ADC_JDR_JDATA_SHIFT (0) -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC analog watchdog 2 configuration register */ - -#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) -# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ - -/* ADC analog watchdog 3 configuration register */ - -#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) -# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ - -/* ADC differential mode selection register 2 */ -#define ADC_DIFSEL_ - -#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) -# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ - -/* ADC calibration factors */ - -#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ -#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) -#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ -#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) - -/* Common status register */ - -#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ -#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ -#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ -#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ -#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ -#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ -#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ -#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ -#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ -#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ -#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ -#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ -#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ -#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ -#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ -#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ -#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ -#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ -#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ -#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ - -/* Common control register */ - -#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ -#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) -# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ -# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */ -# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */ -# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */ -# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */ -# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */ -# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */ -# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */ -#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ -#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ -#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ -#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT) -# define ADC_CCR_MDMA_DISABLED (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ -# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ -# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ -#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ -#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT) -# define ADC_CCR_CKMODE_ASYNCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ -# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ -# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ -# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ -#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ -#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ -#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ - -/* Common regular data register for dual mode */ - -#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ -#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) -#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ -#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Data - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Function Prototypes - ****************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_ADC_H */ diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h index 30308dd93b..831b0e1ac2 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h @@ -145,12 +145,8 @@ /* AHB3 Base Addresses **************************************************************/ -#define STM32_ADC1_BASE 0x50000000 /* 0x5000004c-0x5000004c: Master ADC1 */ -#define STM32_ADC2_BASE 0x50000100 /* 0x5000014c-0x500001ff: Slave ADC2 */ -#define STM32_ADC12_BASE 0x50000300 /* 0x50000300-0x50000308: ADC12 Common */ -#define STM32_ADC3_BASE 0x50000400 /* 0x5000044c-0x5000044c: Master ADC3 */ -#define STM32_ADC4_BASE 0x50000500 /* 0x5000054c-0x500005ff: Slave ADC4 */ -#define STM32_ADC34_BASE 0x50000700 /* 0x50000700-0x50000708: ADC34 Common */ +#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 Base */ +#define STM32_ADC34_BASE 0x50000400 /* 0x50000400-0x500007ff: ADC34 Base */ /* Cortex-M4 Base Addresses *********************************************************/ /* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h index 90af97f036..8c85ff6af3 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h @@ -137,7 +137,7 @@ /* AHB3 Base Addresses **************************************************************/ -#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 */ +#define STM32_ADC12_BASE 0x50000000 /* 0x50000000-0x500003ff: ADC12 Base */ /* Cortex-M4 Base Addresses *********************************************************/ /* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_adc.h b/arch/arm/src/stm32/chip/stm32f37xxx_adc.h deleted file mode 100644 index c8dcbbccb4..0000000000 --- a/arch/arm/src/stm32/chip/stm32f37xxx_adc.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/stm32/chip/stm32f30xxx_adc.h - * - * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. - * Copyright (C) 2016 Studelec SA. All rights reserved. - * Authors: Gregory Nutt - * Marc Rechté - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ - -/* Register Offsets *********************************************************************************/ - -#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register */ -#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 */ -#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 */ -#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 */ -#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 */ -#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 */ -#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 */ -#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 */ -#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 */ -#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register */ -#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register */ -#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 */ -#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 */ -#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 */ -#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register */ -#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 */ -#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 2 */ -#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 3 */ -#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 4 */ -#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register */ - -/* Register Addresses *******************************************************************************/ - -#define STM32_ADC_SR (STM32_ADC_BASE+STM32_ADC_SR_OFFSET) -#define STM32_ADC_CR1 (STM32_ADC_BASE+STM32_ADC_CR1_OFFSET) -#define STM32_ADC_CR2 (STM32_ADC_BASE+STM32_ADC_CR2_OFFSET) -#define STM32_ADC_SMPR1 (STM32_ADC_BASE+STM32_ADC_SMPR1_OFFSET) -#define STM32_ADC_SMPR2 (STM32_ADC_BASE+STM32_ADC_SMPR2_OFFSET) -#define STM32_ADC_JOFR1 (STM32_ADC_BASE+STM32_ADC_JOFR1_OFFSET) -#define STM32_ADC_JOFR2 (STM32_ADC_BASE+STM32_ADC_JOFR2_OFFSET) -#define STM32_ADC_JOFR3 (STM32_ADC_BASE+STM32_ADC_JOFR3_OFFSET) -#define STM32_ADC_JOFR4 (STM32_ADC_BASE+STM32_ADC_JOFR4_OFFSET) -#define STM32_ADC_HTR (STM32_ADC_BASE+STM32_ADC_HTR_OFFSET) -#define STM32_ADC_LTR (STM32_ADC_BASE+STM32_ADC_LTR_OFFSET) -#define STM32_ADC_SQR1 (STM32_ADC_BASE+STM32_ADC_SQR1_OFFSET) -#define STM32_ADC_SQR2 (STM32_ADC_BASE+STM32_ADC_SQR2_OFFSET) -#define STM32_ADC_SQR3 (STM32_ADC_BASE+STM32_ADC_SQR3_OFFSET) -#define STM32_ADC_JSQR (STM32_ADC_BASE+STM32_ADC_JSQR_OFFSET) -#define STM32_ADC_JDR1 (STM32_ADC_BASE+STM32_ADC_JDR1_OFFSET) -#define STM32_ADC_JDR2 (STM32_ADC_BASE+STM32_ADC_JDR2_OFFSET) -#define STM32_ADC_JDR3 (STM32_ADC_BASE+STM32_ADC_JDR3_OFFSET) -#define STM32_ADC_JDR4 (STM32_ADC_BASE+STM32_ADC_JDR4_OFFSET) -#define STM32_ADC_DR (STM32_ADC_BASE+STM32_ADC_DR_OFFSET) - -/* Register Bitfield Definitions ********************************************************************/ -/* ADC status register (SR) */ - -#define ADC_SR_AWD (1 << 0) /* Bit 0: Analog wtchdog flag */ -#define ADC_SR_EOC (1 << 1) /* Bit 1: End of conversion */ -#define ADC_SR_JEOC (1 << 2) /* Bit 2: Injected channel end of conversion */ -#define ADC_SR_JSTRT (1 << 3) /* Bit 3: Injected channel start flag */ -#define ADC_SR_RSTRT (1 << 4) /* Bit 4: Regular channel start flag */ - -/* ADC control register 1 */ - -#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 0-4: Analog watchdog channel select bits */ -#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) -#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable EOC */ -#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog watchdog interrupt enable */ -#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ -#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ -#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ -#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ -#define ADC_CR1_DISNUM_SHIFT (13) /* Bit 13-15: Discontinuous mode channel count */ -#define ADC_CR1_DISNUM_MASK (0x7 << ADC_CR1_DISNUM_SHIFT) -#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ - -/* ADC control register 2 */ - -#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D converter ON / OFF */ -#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous conversion */ -#define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */ -#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset calibration */ -#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct memory access mode */ -#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data alignment */ -#define ADC_CR2_JEXTSEL_SHIFT (12) /* Bit 12-14: External event select for injected group */ -#define ADC_CR2_JEXTSEL_MASK (0x7 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_TIM19_CC1 (0 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_TIM19_CC2 (1 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_TIM2_TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_TIM2_CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_TIM3_CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_TIM4_TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) -#define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External trigger conversion mode for injected channels */ -#define ADC_CR2_EXTSEL_SHIFT (17) /* Bit 17-19: External event select for regular group */ -#define ADC_CR2_EXTSEL_MASK (0x7 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_TIM19_TRGO (0 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_TIM19_CC3 (1 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_TIM19_CC4 (2 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_TIM2_CC2 (3 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_TIM3_TRGO (4 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_TIM4_CC4 (5 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External trigger conversion mode for regular channels */ -#define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start conversion of injected channels */ -#define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start conversion of regular channels */ -#define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and V REFINT enable */ - -/* ADC sample time register 1 */ - -#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ -#define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */ -#define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */ -#define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */ -#define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */ -#define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */ -#define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */ -#define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */ - -#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) -#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) -#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) -#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) -#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) -#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) -#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) -#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) -#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT) - -/* ADC sample time register 2 */ - -#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ -#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) -#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) -#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) -#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) -#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) -#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) -#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) -#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) -#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) -#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) - -/* ADC injected channel data offset register 1, 2, 3, and 4 */ - -#define ADC_JOFR_OFFSETX_SHIFT (0) /* Bits 0-11: Data offset for injected channel x */ -#define ADC_JOFR_OFFSETX_MASK (0x0fff << ADC_JOFR_OFFSETX_SHIFT) - -/* ADC watchdog high threshold register */ - -#define ADC_HTR_HT_SHIFT (0) /* Bits 0-11: Analog watchdog high threshold */ -#define ADC_HTR_HT_MASK (0xfff << ADC_HTR_HT_SHIFT) - -/* ADC watchdog low threshold register */ - -#define ADC_LTR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog low threshold */ -#define ADC_LTR_LT_MASK (0xfff << ADC_LTR_LT_SHIFT) - -/* Offset between SQ bits */ - -#define ADC_SQ_OFFSET (5) - -/* ADC regular sequence register 1 */ - -#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 0-4: 13th conversion in regular sequence */ -#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) -#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 5-9: 14th conversion in regular sequence */ -#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) -#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 10-14: 15th conversion in regular sequence */ -#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) -#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 15-19: 16th conversion in regular sequence */ -#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) -#define ADC_SQR1_L_SHIFT (20) /* Bits 20-23: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0xf << ADC_SQR1_L_SHIFT) -#define ADC_SQR1_RESERVED (0xff000000) -#define ADC_SQR1_FIRST (13) -#define ADC_SQR1_LAST (16) -#define ADC_SQR1_SQ_OFFSET (0) - -/* ADC regular sequence register 2 */ - -#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 0-4: 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 5-9: 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 10-14: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 15-19: 10th conversion in regular sequence */ -#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) -#define ADC_SQR2_SQ11_SHIFT (15) /* Bits 20-24: 11th conversion in regular sequence */ -#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT) -#define ADC_SQR2_SQ12_SHIFT (15) /* Bits 25-29: 12th conversion in regular sequence */ -#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) -#define ADC_SQR2_RESERVED (0xc0000000) -#define ADC_SQR2_FIRST (7) -#define ADC_SQR2_LAST (12) -#define ADC_SQR2_SQ_OFFSET (0) - -/* ADC regular sequence register 3 */ - -#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in regular sequence */ -#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) -#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in regular sequence */ -#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) -#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in regular sequence */ -#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) -#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 15-19: 4th conversion in regular sequence */ -#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) -#define ADC_SQR3_SQ5_SHIFT (15) /* Bits 20-24: 5th conversion in regular sequence */ -#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT) -#define ADC_SQR3_SQ6_SHIFT (15) /* Bits 25-29: 6th conversion in regular sequence */ -#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) -#define ADC_SQR3_RESERVED (0xc0000000) -#define ADC_SQR3_FIRST (1) -#define ADC_SQR3_LAST (6) -#define ADC_SQR3_SQ_OFFSET (0) - -/* ADC injected sequence register */ - -#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) -#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 15-19: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -#define ADC_JSQR_JL_SHIFT (20) /* Bits 20-21: Injected sequence length */ -#define ADC_JSQR_JL_MASK (0x3 << ADC_JSQR_JL_SHIFT) - -/* ADC injected data register 1, 2, 3, and 4 */ - -#define ADC_JDR_JDATA_SHIFT (0) -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC regular data register */ - -#define ADC_DR_RDATA_SHIFT (0) -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Data - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Function Prototypes - ****************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h index 2089ad0be8..10daaaae18 100644 --- a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h @@ -117,7 +117,7 @@ #define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */ #define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */ -#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ +#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ #define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ #define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ @@ -128,8 +128,6 @@ #define STM32_SDADC2_BASE 0x40016400 /* 0x40016000-0x400167ff SDADC2 */ #define STM32_SDADC3_BASE 0x40016800 /* 0x40016000-0x40016bff SDADC3 */ -#define STM32_ADC1_BASE STM32_ADC_BASE - /* AHB1 Base Addresses **************************************************************/ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h index 1e1f6daf6a..59d5d0c269 100644 --- a/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h +++ b/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h @@ -206,6 +206,7 @@ #define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers reset */ #define RCC_APB2RSTR_ADCRST (1 << 9) /* Bit 9: ADC reset */ +#define RCC_APB2RSTR_ADC1RST (1 << 9) /* for compatibility with ADC driver */ #define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */ #define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ #define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h index 8bd7d5e16a..97340e4d4e 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h @@ -158,10 +158,6 @@ #define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */ #define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */ #define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1-3 */ -# define STM32_ADC1_BASE 0x40012000 /* ADC1 */ -# define STM32_ADC2_BASE 0x40012100 /* ADC2 */ -# define STM32_ADC3_BASE 0x40012200 /* ADC3 */ -# define STM32_ADCCMN_BASE 0x40012300 /* Common */ #define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDIO */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */ #define STM32_SPI4_BASE 0x40013400 /* 0x40013000-0x400137ff: SPI4 */ diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h index 21d064bc31..ef9321156b 100644 --- a/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h @@ -113,7 +113,6 @@ #define STM32_TIM10_BASE 0x40010c00 /* 0x40010c00-0x40010fff TIM10 */ #define STM32_TIM11_BASE 0x40011000 /* 0x40011000-0x400113ff TIM11 */ #define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ -#define STM32_ADCCMN_BASE (STM32_ADC_BASE+0x300) /* ADC Common */ #define STM32_SDIO_BASE 0x40012c00 /* 0x40012c00-0x40012fff SDIO */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ #define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h b/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h index 026d50ec08..29925e56e4 100644 --- a/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h @@ -258,6 +258,7 @@ #define RCC_APB2RSTR_TIM11RST (1 << 4) /* Bit 4: TIM11 timer reset */ /* Bits 5-8: Reserved */ #define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC1 interface reset */ +#define RCC_APB2RSTR_ADCRST (1 << 9) /* for compatibility with ADC driver */ /* Bit 10: Reserved */ #define RCC_APB2RSTR_SDIORST (1 << 11) /* Bit 11: SDIO reset */ #define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */ diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index d2c35395db..dd15c7e0f8 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -1,11 +1,12 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_adc.c * - * Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. * Authors: Gregory Nutt * Diego Sanchez * Paul Alexander Patience + * Mateusz Szafoni * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -77,11 +78,33 @@ #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) -/* This implementation is for the STM32 F1, F2, F3, F4 and STM32L15XX only */ +/* This implementation is for the STM32 ADC IP version 1 and STM32 ADC IP version 2 */ -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) +#if !defined(HAVE_IP_ADC_V1) && !defined(HAVE_IP_ADC_V2) +# error "STM32 ADC IP version not specified" +#endif + +/* At this moment only support for the STM32 ADC IPv2 looks fully functional: + * - noDMA + * - DMA + * - TIM trg + * - TIM trg + DMA + * + * Support for the STM32 ADC IPv1 works fine only for: + * - noDMA (but only with 1 sample) + * - TIM trg + * - TIM trg + DMA + * + * (tested with ADC example app from Nuttx apps repo). + */ + +#ifdef HAVE_IP_ADC_V1 +# if defined(ADC_HAVE_DMA) && !defined(ADC_HAVE_TIMER) +# warning "ADC DMA mode without hardware trigger may not work properly!" +# elif !defined(ADC_HAVE_DMA) && !defined(ADC_HAVE_TIMER) +# warning "ADC without hardware trigger and without DMA may not work properly!" +# endif +#endif /* At the moment there is no proper implementation for timers external * trigger in STM32L15XX May be added latter @@ -91,55 +114,43 @@ # warning "There is no proper implementation for TIMER TRIGGERS at the moment" #endif +/* If ADC use HSI as clock-source and HSI is not used for PLL and system clock, + * then we can control it directly from ADC driver. + */ + +#if defined(HAVE_ADC_CLOCK_HSI) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) + # define HAVE_HSI_CONTROL +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* RCC reset ****************************************************************/ -#if defined(CONFIG_STM32_STM32F10XX) -# define STM32_RCC_RSTR STM32_RCC_APB2RSTR -# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST -# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADC2RST -# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADC3RST -# define RCC_RSTR_ADC4RST RCC_APB2RSTR_ADC4RST -#elif defined(CONFIG_STM32_STM32F30XX) +#if defined(HAVE_IP_ADC_V1) +# ifdef HAVE_BASIC_ADC +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST +# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADC2RST +# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADC3RST +# else +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADCRST +# endif +#elif defined(HAVE_IP_ADC_V2) # define STM32_RCC_RSTR STM32_RCC_AHBRSTR # define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST # define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST # define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST # define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST -#elif defined(CONFIG_STM32_STM32F37XX) -# define STM32_RCC_RSTR STM32_RCC_APB2RSTR -# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_RCC_RSTR STM32_RCC_APB2RSTR -# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST -# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADCRST -# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADCRST -# define RCC_RSTR_ADC4RST RCC_APB2RSTR_ADCRST -#elif defined(CONFIG_STM32_STM32L15XX) -# define STM32_RCC_RSTR STM32_RCC_APB2RSTR -# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST #endif /* ADC interrupts ***********************************************************/ -#if defined(CONFIG_STM32_STM32F30XX) -# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET -# define ADC_DMAREG_DMA ADC_CFGR_DMAEN -# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET -# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR_EXTSEL_MASK -# define ADC_EXTREG_EXTEN_MASK ADC_CFGR_EXTEN_MASK -# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR_EXTEN_RISING -# define ADC_ISR_EOC ADC_INT_EOC -# define ADC_IER_EOC ADC_INT_EOC -# define ADC_ISR_AWD ADC_INT_AWD1 -# define ADC_IER_AWD ADC_INT_AWD1 -# define ADC_ISR_JEOC ADC_INT_JEOC -# define ADC_IER_JEOC ADC_INT_JEOC -# define ADC_ISR_OVR ADC_INT_OVR -# define ADC_IER_OVR ADC_INT_OVR -#else +#if defined(HAVE_IP_ADC_V1) # define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET # define ADC_DMAREG_DMA ADC_CR2_DMA # define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET @@ -152,7 +163,7 @@ # define ADC_IER_AWD ADC_CR1_AWDIE # define ADC_ISR_JEOC ADC_SR_JEOC # define ADC_IER_JEOC ADC_CR1_JEOCIE -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F37XX) +# ifdef HAVE_BASIC_ADC # define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG # define ADC_EXTREG_EXTEN_NONE 0 # define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG @@ -165,6 +176,21 @@ # define ADC_ISR_OVR ADC_SR_OVR # define ADC_IER_OVR ADC_CR1_OVRIE # endif +#elif defined(HAVE_IP_ADC_V2) +# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET +# define ADC_DMAREG_DMA ADC_CFGR1_DMAEN +# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET +# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK +# define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING +# define ADC_ISR_EOC ADC_INT_EOC +# define ADC_IER_EOC ADC_INT_EOC +# define ADC_ISR_AWD ADC_INT_AWD1 +# define ADC_IER_AWD ADC_INT_AWD1 +# define ADC_ISR_JEOC ADC_INT_JEOC +# define ADC_IER_JEOC ADC_INT_JEOC +# define ADC_ISR_OVR ADC_INT_OVR +# define ADC_IER_OVR ADC_INT_OVR #endif #define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \ @@ -193,20 +219,26 @@ # endif #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +/* DMA channels and interface values differs according to STM32 DMA IP core version */ + +#if defined(HAVE_IP_DMA_V2) # define ADC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ DMA_SCR_PSIZE_16BITS | \ DMA_SCR_MINC | \ DMA_SCR_CIRC | \ DMA_SCR_DIR_P2M) -#else +#elif defined(HAVE_IP_DMA_V1) # define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ DMA_CCR_PSIZE_16BITS | \ DMA_CCR_MINC | \ DMA_CCR_CIRC) #endif -/* DMA channels and interface values differ for the F1 and F4 families */ +/* Sample time default configuration + * + * REVISIT: simplify this, use adc_write_sample_time_registers() function. + * REVISIT: default SMPR configurable from Kconfig + */ #if defined(CONFIG_STM32_STM32F10XX) # define ADC_SMPR_DEFAULT ADC_SMPR_55p5 @@ -234,7 +266,6 @@ # else /* Slow down sampling frequency */ # define ADC_SMPR_DEFAULT ADC_SMPR_601p5 # endif - # define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ @@ -280,15 +311,85 @@ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) #elif defined(CONFIG_STM32_STM32L15XX) -# define ADC_CHANNELS_NUMBER 32 # define ADC_SMPR_DEFAULT ADC_SMPR_384 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP20_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP21_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP22_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP23_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP24_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP25_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP26_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP27_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP28_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP29_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP19_SHIFT)) +# define ADC_SMPR3_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR3_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR3_SMP9_SHIFT)) +# define ADC_SMPR0_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR0_SMP30_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR0_SMP31_SHIFT)) +#endif + +/* Number of channels per ADC: + * - F0, L0 - 19, but singe SMP for all channels + * - F1 - 18 + * - F2,F3,F4,F7,L4,L4+ - 19 + * - H7 - 20 + * - L1 - 32 + * + * NOTE: this value can be obtained from SMPRx register description (ST manual) + */ + +#if defined(CONFIG_STM32_STM32F10XX) +# define ADC_CHANNELS_NUMBER 18 +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F4XXX) +# define ADC_CHANNELS_NUMBER 19 +#elif defined(CONFIG_STM32_STM32L15XX) +# define ADC_CHANNELS_NUMBER 32 +#else +# error "Not supported" +#endif + +/* ADC resolution. Not supported for basic STM32 ADC IPv1 */ + +#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +# define HAVE_ADC_RESOLUTION +#else +# undef HAVE_ADC_RESOLUTION +#endif + +/* ADCs have common registers */ + +#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +# undef HAVE_ADC_CMN_REGS +#else +# define HAVE_ADC_CMN_REGS #endif /**************************************************************************** * Private Types ****************************************************************************/ -/* This structure describes the state of one ADC block */ +/* This structure describes the state of one ADC block + * REVISIT: save some space with bit fields. + */ struct stm32_dev_s { @@ -298,14 +399,20 @@ struct stm32_dev_s uint8_t cchannels; /* Number of configured channels */ uint8_t intf; /* ADC interface number */ uint8_t current; /* Current ADC channel being converted */ +#ifdef HAVE_ADC_RESOLUTION + uint8_t resolution; /* ADC resolution (0-3) */ +#endif #ifdef ADC_HAVE_DMA uint8_t dmachan; /* DMA channel needed by this ADC */ bool hasdma; /* True: This channel supports DMA */ #endif -#ifdef CONFIG_STM32_STM32L15XX - /* Sample time selection. These bits must be written only when ADON=0 */ +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + /* Sample time selection. These bits must be written only when ADON=0. + * REVISIT: this takes too much space. We need only 3 bits per channel. + */ uint8_t sample_rate[ADC_CHANNELS_NUMBER]; + uint8_t adc_channels; /* ADC channels number */ #endif #ifdef ADC_HAVE_TIMER uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, @@ -339,9 +446,7 @@ struct stm32_dev_s /* ADC Register access */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) +#ifndef HAVE_BASIC_ADC static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits); #endif @@ -350,6 +455,14 @@ static void adc_putreg(FAR struct stm32_dev_s *priv, int offset, uint32_t value); static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset, uint32_t clrbits, uint32_t setbits); +#ifndef HAVE_ADC_CMN_REGS +static uint32_t adccmn_base_get(FAR struct stm32_dev_s *priv); +static void adccmn_modifyreg(FAR struct stm32_dev_s *priv, uint32_t offset, + uint32_t clrbits, uint32_t setbits); +# ifdef CONFIG_DEBUG_ANALOG_INFO +static uint32_t adccmn_getreg(FAR struct stm32_dev_s *priv, uint32_t offset); +# endif +#endif #ifdef ADC_HAVE_TIMER static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset); static void tim_putreg(FAR struct stm32_dev_s *priv, int offset, @@ -395,24 +508,37 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable); static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, int offset); -static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); +static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); -#ifdef CONFIG_STM32_STM32L15XX +static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, + bool arg); + +#ifdef HAVE_ADC_RESOLUTION +static int adc_resolution_set(FAR struct adc_dev_s *dev, uint8_t res); +#endif +#ifdef HAVE_ADC_VBAT +static void adc_enable_vbat_channel(FAR struct adc_dev_s *dev, bool enable); +#endif +#ifdef HAVE_ADC_POWERDOWN +static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev, + int cmd, bool arg); static void adc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high); static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high); +#endif + +#ifdef CONFIG_STM32_STM32L15XX static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, uint32_t delay); static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, bool chb_selected); -static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, - bool arg); -#if STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI +#endif + +#ifdef HAVE_HSI_CONTROL static void adc_enable_hsi(bool enable); static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev); #endif -#endif #ifdef ADC_HAVE_TIMER static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable); @@ -435,8 +561,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); static const struct adc_ops_s g_adcops = { .ao_bind = adc_bind, -#if defined(CONFIG_STM32_STM32L15XX) && \ - (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) +#ifdef HAVE_HSI_CONTROL .ao_reset = adc_reset_hsi_disable, #else .ao_reset = adc_reset, @@ -465,6 +590,9 @@ static struct stm32_dev_s g_adcpriv1 = # error "No STM32_IRQ_ADC1 STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC1" #endif .intf = 1, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC1_RESOLUTION, +#endif .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_TIMER .trigger = CONFIG_STM32_ADC1_TIMTRIG, @@ -501,6 +629,9 @@ static struct stm32_dev_s g_adcpriv2 = # error "No STM32_IRQ_ADC12 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC2" #endif .intf = 2, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC2_RESOLUTION, +#endif .base = STM32_ADC2_BASE, #ifdef ADC2_HAVE_TIMER .trigger = CONFIG_STM32_ADC2_TIMTRIG, @@ -537,6 +668,9 @@ static struct stm32_dev_s g_adcpriv3 = # error "No STM32_IRQ_ADC3 or STM32_IRQ_ADC defined for CONFIG_STM32_ADC3" #endif .intf = 3, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC3_RESOLUTION, +#endif .base = STM32_ADC3_BASE, #ifdef ADC3_HAVE_TIMER .trigger = CONFIG_STM32_ADC3_TIMTRIG, @@ -566,6 +700,9 @@ static struct stm32_dev_s g_adcpriv4 = .irq = STM32_IRQ_ADC4, .isr = adc4_interrupt, .intf = 4, +#ifdef HAVE_ADC_RESOLUTION + .resolution = CONFIG_STM32_ADC4_RESOLUTION, +#endif .base = STM32_ADC4_BASE, #ifdef ADC4_HAVE_TIMER .trigger = CONFIG_STM32_ADC4_TIMTRIG, @@ -607,9 +744,7 @@ static struct adc_dev_s g_adcdev4 = * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) +#ifndef HAVE_BASIC_ADC static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits) { @@ -682,6 +817,71 @@ static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset, adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits); } +#ifndef HAVE_ADC_CMN_REGS + +/**************************************************************************** + * Name: adccmn_base_get + ****************************************************************************/ + +static uint32_t adccmn_base_get(FAR struct stm32_dev_s *priv) +{ + uint32_t base; + +#if defined(HAVE_IP_ADC_V2) + if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) + { + base = STM32_ADC12CMN_BASE; + } + else + { + base = STM32_ADC34CMN_BASE; + } +#elif defined(HAVE_IP_ADC_V1) + base = STM32_ADCCMN_BASE; + UNUSED(priv); +#endif + + return base; +} + +/**************************************************************************** + * Name: adccmn_modifyreg + ****************************************************************************/ + +static void adccmn_modifyreg(FAR struct stm32_dev_s *priv, uint32_t offset, + uint32_t clrbits, uint32_t setbits) +{ + uint32_t base = 0; + + /* Get base address for ADC common register */ + + base = adccmn_base_get(priv); + + /* Modify register */ + + stm32_modifyreg32(offset + base, clrbits, setbits); +} + +/**************************************************************************** + * Name: adccmn_getreg + ****************************************************************************/ + +# ifdef CONFIG_DEBUG_ANALOG_INFO +static uint32_t adccmn_getreg(FAR struct stm32_dev_s *priv, uint32_t offset) +{ + uint32_t base = 0; + + /* Get base address for ADC common register */ + + base = adccmn_base_get(priv); + + /* Return register value */ + + return getreg32(base+offset); +} +# endif +#endif /* HAVE_ADC_CMN_REGS */ + /**************************************************************************** * Name: tim_getreg * @@ -790,7 +990,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#ifndef CONFIG_STM32_STM32L15XX +#if STM32_NATIM > 0 if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -800,12 +1000,12 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else +#endif { ainfo(" DCR: %04x DMAR: %04x\n", tim_getreg(priv, STM32_GTIM_DCR_OFFSET), tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } -#endif } #endif @@ -980,7 +1180,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Clear the advanced timers repetition counter in TIM1 */ -#ifndef CONFIG_STM32_STM32L15XX +#if STM32_NATIM > 0 if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); @@ -1132,26 +1332,18 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; -#ifndef CONFIG_STM32_STM32L15XX + /* TODO: revisit and simplify logic below */ +#if STM32_NATIM > 0 if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { /* Reset output N polarity level, output N state, output compare state, * output compare N idle state. */ -# if defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | - ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | - ATIM_CCER_CC4NP); -# else ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); -# endif /* Reset the output compare and output compare N IDLE State */ @@ -1160,16 +1352,14 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | ATIM_CR2_OIS4); } -# if defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) +# if defined(HAVE_GTIM_CCXNP) else { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | GTIM_CCER_CC4NP); } # endif -#else +#else /* No ADV TIM */ /* For the STM32L15XX family only these timers can be used: 2-4, 6, 7, 9, 10 * Reset the output compare and output compare N IDLE State @@ -1181,10 +1371,10 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * output compare N idle state. */ - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | - ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | - ATIM_CCER_CC4NP); + ccer &= ~(GTIM_CCER_CC1NE | GTIM_CCER_CC1NP | + GTIM_CCER_CC2NE | GTIM_CCER_CC2NP | + GTIM_CCER_CC3NE | GTIM_CCER_CC3NP | + GTIM_CCER_CC4NP); } #endif @@ -1224,27 +1414,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F10XX) -static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) -{ - ainfo("enable: %d\n", enable ? 1 : 0); - - if (!enable) - { - /* Clear ADON to stop the conversion and put the ADC in the - * power down state. - */ - - adc_enable(priv, false); - } - - /* If the ADC is already on, set ADON again to start the conversion. - * Otherwise, set ADON once to wake up the ADC from the power down state. - */ - - adc_enable(priv, true); -} -#elif defined(CONFIG_STM32_STM32F30XX) +#if defined(HAVE_IP_ADC_V2) static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; @@ -1275,7 +1445,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) } } } -#else +#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) { ainfo("enable: %d\n", enable ? 1 : 0); @@ -1293,6 +1463,26 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_SWSTART, 0); } } +#else /* ADV IPv1 BASIC */ +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) +{ + ainfo("enable: %d\n", enable ? 1 : 0); + + if (!enable) + { + /* Clear ADON to stop the conversion and put the ADC in the + * power down state. + */ + + adc_enable(priv, false); + } + + /* If the ADC is already on, set ADON again to start the conversion. + * Otherwise, set ADON once to wake up the ADC from the power down state. + */ + + adc_enable(priv, true); +} #endif /**************************************************************************** @@ -1318,6 +1508,8 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset) * For the STM32 F1, there is an individual bit to reset each ADC, * but for the STM32 F2/F4, there is one common reset for all ADCs. * THIS will probably cause some problems! + * + * REVISIT: this is correct only for F1! */ switch (priv->intf) @@ -1526,7 +1718,7 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(HAVE_IP_ADC_V2) static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; @@ -1560,7 +1752,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0); } } -#else +#else /* HAVE_IP_ADC_V1 */ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) { #ifdef ADC_SR_ADONS @@ -1586,8 +1778,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) * Name: adc_write_sample_time_registers * * Description: - * Writes previously defined values into ADC_SMPR0, ADC_SMPR1, ADC_SMPR2 - * and ADC_SMPR3 registers + * Writes previously defined values into ADC_SMPRx registers. * * Input Parameters: * @@ -1595,7 +1786,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; @@ -1603,49 +1794,73 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev) uint8_t i; uint8_t shift; - /* Sampling time individually for each channel - * 000: 4 cycles - * 001: 9 cycles - * 010: 16 cycles - * 011: 24 cycles - * 100: 48 cycles - * 101: 96 cycles - * 110: 192 cycles - * 111: 384 cycles - selected for all channels + /* Sampling time individually for each channel. + * It's different for families. */ - for (i = 0, shift = 0; i < 32; i++) + for (i = 0, shift = 0; i < priv->adc_channels; i++) { value |= priv->sample_rate[i] << (shift * 3); switch (i) { +#if defined(STM32_ADC_SMPR0_OFFSET) && defined(STM32_ADC_SMPR3_OFFSET) case 9: - adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, value); - shift = 0; - value = 0; - break; + { + adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, value); + shift = 0; + value = 0; + break; + } case 19: - adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, value); - shift = 0; - value = 0; - break; + { + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, value); + shift = 0; + value = 0; + break; + } case 29: - adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, value); - shift = 0; - value = 0; - break; + { + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, value); + shift = 0; + value = 0; + break; + } - case 31: - adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, value); - shift = 0; - value = 0; - break; + case (ADC_CHANNELS_NUMBER - 1): + { + adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, value); + shift = 0; + value = 0; + break; + } + +#elif defined(STM32_ADC_SMPR1_OFFSET) && defined(STM32_ADC_SMPR2_OFFSET) + case (ADC_CHANNELS_NUMBER - 1): + { + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, value); + shift = 0; + value = 0; + break; + } + + case 9: + { + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, value); + shift = 0; + value = 0; + break; + } +#else +# error "Not supported SMPRx configuration" +#endif default: - shift++; - break; + { + shift++; + break; + } } } } @@ -1683,7 +1898,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) for (i = 0; i < priv->nchannels; i++) { - priv->cb->au_receive(dev, priv->chanlist[priv->current], priv->dmabuffer[priv->current]); + priv->cb->au_receive(dev, priv->chanlist[priv->current], + priv->dmabuffer[priv->current]); priv->current++; if (priv->current >= priv->nchannels) { @@ -1746,9 +1962,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) ainfo("intf: %d\n", priv->intf); flags = enter_critical_section(); -#if defined(CONFIG_STM32_STM32L15XX) && \ - (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) - +#ifdef HAVE_HSI_CONTROL /* The STM32L15XX family uses HSI as an independent clock-source * for the ADC */ @@ -1757,7 +1971,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) #endif -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(HAVE_IP_ADC_V2) /* Turn off the ADC so we can write the RCC bits */ @@ -1773,7 +1987,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_rccreset(priv, false); -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(HAVE_IP_ADC_V2) /* Set voltage regular enable to intermediate state */ @@ -1805,7 +2019,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_putreg(priv, STM32_ADC_TR1_OFFSET, 0x0fff0000); -#else +#else /* HAVE_IP_ADC_V1 */ /* Initialize the watchdog high threshold register */ @@ -1821,51 +2035,52 @@ static void adc_reset(FAR struct adc_dev_s *dev) * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32_STM32L15XX +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME adc_write_sample_time_registers(dev); #else adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); +# ifdef STM32_ADC_SMPR3_OFFSET + adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, ADC_SMPR3_DEFAULT); +# endif +# ifdef STM32_ADC_SMPR0_OFFSET + adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, ADC_SMPR0_DEFAULT); +# endif #endif -#if defined(CONFIG_STM32_STM32F30XX) +#ifdef HAVE_IP_ADC_V2 /* Enable the analog watchdog */ - clrbits = ADC_CFGR_AWD1CH_MASK; - setbits = ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | - (priv->chanlist[0] << ADC_CFGR_AWD1CH_SHIFT); - - /* Set the resolution of the conversion */ - - clrbits |= ADC_CFGR_RES_MASK; - setbits |= ADC_CFGR_RES_12BIT; + clrbits = ADC_CFGR1_AWD1CH_MASK; + setbits = ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | + (priv->chanlist[0] << ADC_CFGR1_AWD1CH_SHIFT); #ifdef ADC_HAVE_DMA if (priv->hasdma) { /* Set DMA one shot mode */ - clrbits |= ADC_CFGR_DMACFG; + clrbits |= ADC_CFGR1_DMACFG; /* Enable DMA */ - setbits |= ADC_CFGR_DMAEN; + setbits |= ADC_CFGR1_DMAEN; } #endif /* Disable continuous mode and set align to right */ - clrbits |= ADC_CFGR_CONT | ADC_CFGR_ALIGN; + clrbits |= ADC_CFGR1_CONT | ADC_CFGR1_ALIGN; /* Disable external trigger for regular channels */ - clrbits |= ADC_CFGR_EXTEN_MASK; - setbits |= ADC_CFGR_EXTEN_NONE; + clrbits |= ADC_CFGR1_EXTEN_MASK; + setbits |= ADC_CFGR1_EXTEN_NONE; /* Set CFGR configuration */ - adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); /* Enable interrupt flags, but disable overrun interrupt */ @@ -1876,67 +2091,48 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits); -#else /* CONFIG_STM32_STM32F30XX */ +#else /* HAVE_IP_ADC_V1 */ /* Enable the analog watchdog */ clrbits = ADC_CR1_AWDCH_MASK; setbits = ADC_CR1_AWDEN | (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT); -#ifdef CONFIG_STM32_STM32F10XX - +# ifdef HAVE_BASIC_ADC /* Set independent mode */ clrbits |= ADC_CR1_DUALMOD_MASK; setbits |= ADC_CR1_IND; +# endif -#elif (! defined(CONFIG_STM32_STM32F37XX)) - - /* Set the resolution of the conversion */ - - clrbits |= ADC_CR1_RES_MASK; - setbits |= ADC_CR1_RES_12BIT; - -#endif - -#ifdef ADC_HAVE_DMA +# ifdef ADC_HAVE_DMA if (priv->hasdma) { setbits |= ADC_CR1_SCAN; } -#endif - - /* Enable interrupt flags, but disable overrun interrupt: TODO this is - * done later by upper half when opening device by adc_rxint(). - */ - -#ifndef CONFIG_STM32_STM32F37XX - clrbits |= ADC_IER_OVR; - setbits |= ADC_IER_ALLINTS & ~ADC_IER_OVR; -#else - /* TODO NON DMA mode */ -#endif +# endif /* Set CR1 configuration */ adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits); -#ifdef CONFIG_STM32_STM32L15XX - - /* Disables power down during the delay phase */ - - adc_power_down_idle(priv, false); - adc_power_down_delay(priv, false); +# ifdef CONFIG_STM32_STM32L15XX /* REVISIT: */ /* Select the bank of channels A */ adc_select_ch_bank(priv, false); +# ifdef HAVE_ADC_POWERDOWN + /* Disables power down during the delay phase */ + + adc_power_down_idle(priv, false); + adc_power_down_delay(priv, false); +# endif + /* Delay until the converted data has been read */ adc_dels_after_conversion(priv, ADC_CR2_DELS_TILLRD); - -#endif +# endif /* Disable continuous mode and set align to right */ @@ -1948,19 +2144,21 @@ static void adc_reset(FAR struct adc_dev_s *dev) clrbits |= ADC_EXTREG_EXTEN_MASK; setbits |= ADC_EXTREG_EXTEN_NONE; - /* Enable software trigger for regular channels */ + /* Enable software trigger for regular channels + * REVISIT: SWSTART must be set if no EXT trigger and basic ADC IPv1 + */ -#ifdef CONFIG_STM32_STM32F37XX +# ifdef CONFIG_STM32_STM32F37XX clrbits |= ADC_CR2_EXTSEL_MASK; setbits |= ADC_CR2_EXTSEL_SWSTART | ADC_CR2_EXTTRIG; /* SW is considered as external trigger */ -#endif +# endif -#ifdef ADC_HAVE_DMA +# ifdef ADC_HAVE_DMA if (priv->hasdma) { setbits |= ADC_CR2_DMA; } -#endif +# endif /* Set CR2 configuration */ @@ -1972,36 +2170,30 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_set_ch(dev, 0); - /* ADC CCR configuration */ + /* ADC CCR configuration + * REVISIT: simplify this + */ -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(HAVE_IP_ADC_V2) clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG | ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN; setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(0) | ADC_CCR_MDMA_DISABLED | ADC_CCR_CKMODE_ASYNCH; - if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) - { - stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits); - } - else - { - stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits); - } -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); + +#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE; setbits = ADC_CCR_ADCPRE_DIV2; -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if !defined(CONFIG_STM32_STM32L15XX) clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | - ADC_CCR_DMA_MASK | ADC_CCR_VBATE; + ADC_CCR_DMA_MASK | ADC_CCR_VBATEN; setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED; -#endif +# endif /* !defined(CONFIG_STM32_STM32L15XX) */ - stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits); + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits); #endif #ifdef ADC_HAVE_DMA @@ -2031,7 +2223,13 @@ static void adc_reset(FAR struct adc_dev_s *dev) #endif - /* Set ADON to wake up the ADC from the power down state */ +#ifdef HAVE_ADC_RESOLUTION + /* Configure ADC resolution */ + + (void)adc_resolution_set(dev, priv->resolution); +#endif + + /* Enable ADC */ adc_enable(priv, true); @@ -2043,6 +2241,12 @@ static void adc_reset(FAR struct adc_dev_s *dev) { aerr("ERROR: adc_timinit failed: %d\n", ret); } + + /* NOTE: for ADC IPv2 ADSTART bit must be set to start ADC conversion + * even if hardware trigger is selected. + * This is not done here, and you probably have to call ioctl + * with ANIOC_TRIGGER before reading from ADC! + */ } #ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV else @@ -2056,11 +2260,11 @@ static void adc_reset(FAR struct adc_dev_s *dev) leave_critical_section(flags); -#if defined(CONFIG_STM32_STM32F30XX) - ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n", +#if defined(HAVE_IP_ADC_V2) + ainfo("ISR: 0x%08x CR: 0x%08x CFGR1: 0x%08x\n", adc_getreg(priv, STM32_ADC_ISR_OFFSET), adc_getreg(priv, STM32_ADC_CR_OFFSET), - adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); + adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); #else ainfo("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n", adc_getreg(priv, STM32_ADC_SR_OFFSET), @@ -2073,27 +2277,16 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); -#if defined(CONFIG_STM32_STM32F30XX) - ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); -#elif defined(CONFIG_STM32_STM32L15XX) +#if defined(STM32_ADC_SQR5_OFFSET) ainfo("SQR4: 0x%08x SQR5: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET) adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); +#elif defined(STM32_ADC_SQR4_OFFSET) + ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); #endif -#if defined(CONFIG_STM32_STM32F30XX) - if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) - { - ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR)); - } - else - { - ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR)); - } -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) - ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR)); +#if defined(HAVE_IP_ADC_V2) || (defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)) + ainfo("CCR: 0x%08x\n", adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); #endif } @@ -2112,8 +2305,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) && \ - (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) +#ifdef HAVE_HSI_CONTROL static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev) { adc_reset(dev); @@ -2180,8 +2372,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; adc_enable(priv, false); -#if defined(CONFIG_STM32_STM32L15XX) && \ - (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) +#ifdef HAVE_HSI_CONTROL adc_enable_hsi(false); #endif @@ -2256,30 +2447,14 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F4XXX) +#if defined(HAVE_IP_ADC_V1) static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, bool enable) { - if (enable) - { - stm32_modifyreg32(STM32_ADC_CCR, 0, ADC_CCR_TSVREFE); - } - else - { - stm32_modifyreg32(STM32_ADC_CCR, ADC_CCR_TSVREFE, 0); - } - - ainfo("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR)); -} - -#elif defined(CONFIG_STM32_STM32F10XX) -static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, - bool enable) -{ -#if defined(CONFIG_STM32_ADC1) FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; +#ifdef HAVE_BASIC_ADC +# if defined(CONFIG_STM32_ADC1) /* TSVREF bit is only available in the STM32_ADC1_CR2 register. */ if (priv->intf == 1) @@ -2296,7 +2471,52 @@ static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, ainfo("STM32_ADC_CR2 value: 0x%08x\n", adc_getreg(priv, STM32_ADC_CR2_OFFSET)); -#endif /* CONFIG_STM32_ADC1 */ +# endif /* CONFIG_STM32_ADC1 */ +#else /* !HAVE_BASIC_ADC */ + if (enable) + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_TSVREFE); + } + else + { + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_TSVREFE, 0); + } + + ainfo("STM32_ADC_CCR value: 0x%08x\n", adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); +#endif +} +#endif /* HAVE_IP_ADC_V1 */ + +/**************************************************************************** + * Name: adc_resolution_set + ****************************************************************************/ + +#ifdef HAVE_ADC_RESOLUTION +static int adc_resolution_set(FAR struct adc_dev_s *dev, uint8_t res) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + /* Check input */ + + if (res > 3) + { + ret = -EINVAL; + goto errout; + } + + /* Modify appropriate register */ + +#if defined(HAVE_IP_ADC_V1) + adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, ADC_CR1_RES_MASK, + res << ADC_CR1_RES_SHIFT); +#elif defined(HAVE_IP_ADC_V2) + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, ADC_CFGR1_RES_MASK, + res << ADC_CFGR1_RES_SHIFT); +#endif + +errout: + return ret; } #endif @@ -2316,19 +2536,21 @@ static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#ifdef HAVE_ADC_VBAT static void adc_enable_vbat_channel(FAR struct adc_dev_s *dev, bool enable) { + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + if (enable) { - stm32_modifyreg32(STM32_ADC_CCR, 0, ADC_CCR_VBATE); + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_VBATEN); } else { - stm32_modifyreg32(STM32_ADC_CCR, ADC_CCR_VBATE, 0); + adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_VBATEN, 0); } - ainfo("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR)); + ainfo("STM32_ADC_CCR value: 0x%08x\n", adccmn_getreg(priv, STM32_ADC_CCR_OFFSET)); } #endif @@ -2347,7 +2569,7 @@ static void adc_enable_vbat_channel(FAR struct adc_dev_s *dev, bool enable) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX +#ifdef HAVE_ADC_POWERDOWN static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev, int cmd, bool arg) { @@ -2397,7 +2619,6 @@ static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable) { if (enable) @@ -2409,7 +2630,6 @@ static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0); } } -#endif /**************************************************************************** * Name: adc_ioc_enable_eoc_int @@ -2426,7 +2646,6 @@ static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable) { if (enable) @@ -2438,7 +2657,6 @@ static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0); } } -#endif /**************************************************************************** * Name: adc_ioc_enable_jeoc_int @@ -2455,7 +2673,6 @@ static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_jeoc_int(FAR struct stm32_dev_s *priv, bool enable) { if (enable) @@ -2467,7 +2684,6 @@ static void adc_ioc_enable_jeoc_int(FAR struct stm32_dev_s *priv, bool enable) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_JEOC, 0); } } -#endif /**************************************************************************** * Name: adc_ioc_enable_ovr_int @@ -2484,7 +2700,6 @@ static void adc_ioc_enable_jeoc_int(FAR struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_ovr_int(FAR struct stm32_dev_s *priv, bool enable) { if (enable) @@ -2496,7 +2711,6 @@ static void adc_ioc_enable_ovr_int(FAR struct stm32_dev_s *priv, bool enable) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0); } } -#endif /**************************************************************************** * Name: adc_ioc_change_ints @@ -2513,7 +2727,6 @@ static void adc_ioc_enable_ovr_int(FAR struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, bool arg) { int ret = OK; @@ -2551,7 +2764,6 @@ static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, bool arg) return ret; } -#endif /**************************************************************************** * Name: adc_ioc_wait_rcnr_zeroed @@ -2598,8 +2810,7 @@ static int adc_ioc_wait_rcnr_zeroed(FAR struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) && \ - (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) +#ifdef HAVE_HSI_CONTROL static void adc_enable_hsi(bool enable) { if (enable) @@ -2693,8 +2904,8 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); - bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT | - adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); + bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT; + bits |= adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); return OK; @@ -2718,56 +2929,81 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - int ret = OK; + int ret = OK; switch (cmd) { case ANIOC_TRIGGER: - adc_startconv(priv, true); - break; - -#if defined(CONFIG_STM32_STM32F10XX) - case IO_ENABLE_TEMPER_VOLT_CH: - adc_ioc_enable_tvref_register(dev, *(bool *)arg); - break; - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - case IO_ENABLE_TEMPER_VOLT_CH: - adc_ioc_enable_tvref_register(dev, *(bool *)arg); - break; - - case IO_ENABLE_DISABLE_VBAT_CH: - adc_enable_vbat_channel(dev, *(bool *)arg); - break; - -#elif defined(CONFIG_STM32_STM32L15XX) - case IO_ENABLE_TEMPER_VOLT_CH: - adc_ioc_enable_tvref_register(dev, *(bool *)arg); - break; - - case IO_ENABLE_DISABLE_PDI: - case IO_ENABLE_DISABLE_PDD: - case IO_ENABLE_DISABLE_PDD_PDI: - adc_ioc_change_sleep_between_opers(dev, cmd, *(bool *)arg); - break; + { + adc_startconv(priv, true); + break; + } case IO_ENABLE_DISABLE_AWDIE: case IO_ENABLE_DISABLE_EOCIE: case IO_ENABLE_DISABLE_JEOCIE: case IO_ENABLE_DISABLE_OVRIE: case IO_ENABLE_DISABLE_ALL_INTS: - adc_ioc_change_ints(dev, cmd, *(bool *)arg); - break; + { + adc_ioc_change_ints(dev, cmd, *(bool *)arg); + break; + } + +#if defined(HAVE_IP_ADC_V1) + case IO_ENABLE_TEMPER_VOLT_CH: + { + adc_ioc_enable_tvref_register(dev, *(bool *)arg); + break; + } +#endif + +#ifdef HAVE_ADC_VBAT + case IO_ENABLE_DISABLE_VBAT_CH: + { + adc_enable_vbat_channel(dev, *(bool *)arg); + break; + } +#endif + +#ifdef HAVE_ADC_POWERDOWN + case IO_ENABLE_DISABLE_PDI: + case IO_ENABLE_DISABLE_PDD: + case IO_ENABLE_DISABLE_PDD_PDI: + { + adc_ioc_change_sleep_between_opers(dev, cmd, *(bool *)arg); + break; + } +#endif + + case IO_STOP_ADC: + { + adc_enable(priv, false); +#ifdef HAVE_HSI_CONTROL + adc_enable_hsi(false); +#endif + break; + } + + case IO_START_ADC: + { +#ifdef HAVE_HSI_CONTROL + adc_enable_hsi(true); +#endif + adc_enable(priv, true); + break; + } case IO_START_CONV: { uint8_t ch = ((uint8_t)arg); +#ifdef CONFIG_STM32_STM32L15XX ret = adc_ioc_wait_rcnr_zeroed(priv); if (ret < 0) { return ret; } +#endif ret = adc_set_ch(dev, ch); if (ret < 0) @@ -2784,26 +3020,15 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) } adc_startconv(priv, true); + break; } - break; - -#if STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI - case IO_STOP_ADC: - adc_enable(priv, false); - adc_enable_hsi(false); - break; - - case IO_START_ADC: - adc_enable_hsi(true); - adc_enable(priv, true); - break; -#endif -#endif /* CONFIG_STM32_STM32L15XX */ default: - aerr("ERROR: Unknown cmd: %d\n", cmd); - ret = -ENOTTY; - break; + { + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } } return ret; @@ -3042,7 +3267,7 @@ static int adc123_interrupt(int irq, FAR void *context, FAR void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev, FAR struct adc_sample_time_s *time_samples) { @@ -3143,12 +3368,11 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, priv = (FAR struct stm32_dev_s *)dev->ad_priv; -#if defined(CONFIG_STM32_STM32L15XX) - +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Assign default values for the sample time table */ memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); - + priv->adc_channels = ADC_CHANNELS_NUMBER; #endif DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES); @@ -3161,10 +3385,6 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || - * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX || - * CONFIG_STM32_STM32F4XXX || CONFIG_STM32_STM32L15XX - */ #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 */ diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h index b77113be16..2a06971080 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/stm32/stm32_adc.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_adc.h * - * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. * Authors: Gregory Nutt * Paul Alexander Patience @@ -46,15 +46,7 @@ #include "chip.h" -#if defined(CONFIG_STM32_STM32F30XX) -# include "chip/stm32f30xxx_adc.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "chip/stm32f33xxx_adc.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "chip/stm32f37xxx_adc.h" -#else -# include "chip/stm32_adc.h" -#endif +#include "chip/stm32_adc.h" #include @@ -564,250 +556,250 @@ */ #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define ADC1_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1 -# define ADC1_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2 -# define ADC1_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3 -# define ADC1_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4 -# define ADC1_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO -# define ADC2_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1 -# define ADC2_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2 -# define ADC2_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3 -# define ADC2_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4 -# define ADC2_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO -# define ADC3_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1 -# define ADC3_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2 -# define ADC3_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3 -# define ADC3_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4 -# define ADC3_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO -# define ADC4_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1 -# define ADC4_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2 -# define ADC4_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3 -# define ADC4_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4 -# define ADC4_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO -# define ADC1_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1 -# define ADC1_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2 -# define ADC1_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3 -# define ADC1_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4 -# define ADC1_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO -# define ADC2_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1 -# define ADC2_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2 -# define ADC2_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3 -# define ADC2_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4 -# define ADC2_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO -# define ADC3_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1 -# define ADC3_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2 -# define ADC3_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3 -# define ADC3_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4 -# define ADC3_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO -# define ADC4_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1 -# define ADC4_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2 -# define ADC4_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3 -# define ADC4_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4 -# define ADC4_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO -# define ADC1_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1 -# define ADC1_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2 -# define ADC1_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3 -# define ADC1_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4 -# define ADC1_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO -# define ADC2_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1 -# define ADC2_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2 -# define ADC2_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3 -# define ADC2_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4 -# define ADC2_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO -# define ADC3_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1 -# define ADC3_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2 -# define ADC3_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3 -# define ADC3_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4 -# define ADC3_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO -# define ADC4_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1 -# define ADC4_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2 -# define ADC4_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3 -# define ADC4_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4 -# define ADC4_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO -# define ADC1_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1 -# define ADC1_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2 -# define ADC1_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3 -# define ADC1_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4 -# define ADC1_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO -# define ADC2_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1 -# define ADC2_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2 -# define ADC2_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3 -# define ADC2_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4 -# define ADC2_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO -# define ADC3_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1 -# define ADC3_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2 -# define ADC3_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3 -# define ADC3_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4 -# define ADC3_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO -# define ADC4_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1 -# define ADC4_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2 -# define ADC4_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3 -# define ADC4_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4 -# define ADC4_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO -# define ADC1_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1 -# define ADC1_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2 -# define ADC1_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3 -# define ADC1_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4 -# define ADC1_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO -# define ADC2_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1 -# define ADC2_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2 -# define ADC2_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3 -# define ADC2_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4 -# define ADC2_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO -# define ADC3_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1 -# define ADC3_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2 -# define ADC3_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3 -# define ADC3_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4 -# define ADC3_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO -# define ADC4_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1 -# define ADC4_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2 -# define ADC4_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3 -# define ADC4_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4 -# define ADC4_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO -# define ADC1_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1 -# define ADC1_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2 -# define ADC1_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3 -# define ADC1_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4 -# define ADC1_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO -# define ADC2_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1 -# define ADC2_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2 -# define ADC2_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3 -# define ADC2_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4 -# define ADC2_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO -# define ADC3_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1 -# define ADC3_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2 -# define ADC3_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3 -# define ADC3_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4 -# define ADC3_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO -# define ADC4_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1 -# define ADC4_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2 -# define ADC4_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3 -# define ADC4_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4 -# define ADC4_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO -# define ADC1_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1 -# define ADC1_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2 -# define ADC1_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3 -# define ADC1_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4 -# define ADC1_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO -# define ADC2_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1 -# define ADC2_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2 -# define ADC2_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3 -# define ADC2_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4 -# define ADC2_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO -# define ADC3_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1 -# define ADC3_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2 -# define ADC3_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3 -# define ADC3_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4 -# define ADC3_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO -# define ADC4_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1 -# define ADC4_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2 -# define ADC4_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3 -# define ADC4_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4 -# define ADC4_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO -# define ADC1_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1 -# define ADC1_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2 -# define ADC1_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3 -# define ADC1_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4 -# define ADC1_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO -# define ADC2_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1 -# define ADC2_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2 -# define ADC2_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3 -# define ADC2_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4 -# define ADC2_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO -# define ADC3_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1 -# define ADC3_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2 -# define ADC3_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3 -# define ADC3_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4 -# define ADC3_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO -# define ADC4_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1 -# define ADC4_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2 -# define ADC4_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3 -# define ADC4_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4 -# define ADC4_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO -# define ADC1_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1 -# define ADC1_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2 -# define ADC1_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3 -# define ADC1_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4 -# define ADC1_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO -# define ADC2_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1 -# define ADC2_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2 -# define ADC2_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3 -# define ADC2_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4 -# define ADC2_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO -# define ADC3_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1 -# define ADC3_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2 -# define ADC3_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3 -# define ADC3_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4 -# define ADC3_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO -# define ADC4_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1 -# define ADC4_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2 -# define ADC4_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3 -# define ADC4_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4 -# define ADC4_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO -# define ADC1_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1 -# define ADC1_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2 -# define ADC1_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3 -# define ADC1_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4 -# define ADC1_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO -# define ADC2_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1 -# define ADC2_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2 -# define ADC2_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3 -# define ADC2_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4 -# define ADC2_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO -# define ADC3_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1 -# define ADC3_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2 -# define ADC3_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3 -# define ADC3_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4 -# define ADC3_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO -# define ADC4_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1 -# define ADC4_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2 -# define ADC4_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3 -# define ADC4_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4 -# define ADC4_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO -# define ADC1_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1 -# define ADC1_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2 -# define ADC1_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3 -# define ADC1_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4 -# define ADC1_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO -# define ADC2_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1 -# define ADC2_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2 -# define ADC2_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3 -# define ADC2_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4 -# define ADC2_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO -# define ADC3_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1 -# define ADC3_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2 -# define ADC3_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3 -# define ADC3_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4 -# define ADC3_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO -# define ADC4_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1 -# define ADC4_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2 -# define ADC4_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3 -# define ADC4_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4 -# define ADC4_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO -# define ADC1_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1 -# define ADC1_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2 -# define ADC1_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3 -# define ADC1_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4 -# define ADC1_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO -# define ADC2_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1 -# define ADC2_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2 -# define ADC2_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3 -# define ADC2_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4 -# define ADC2_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO -# define ADC3_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1 -# define ADC3_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2 -# define ADC3_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3 -# define ADC3_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4 -# define ADC3_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO -# define ADC4_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1 -# define ADC4_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2 -# define ADC4_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3 -# define ADC4_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4 -# define ADC4_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO -# define ADC1_EXTSEL_HRTTRG1 ADC12_CFGR_EXTSEL_HRT1TRG1 -# define ADC1_EXTSEL_HRTTRG3 ADC12_CFGR_EXTSEL_HRT1TRG3 -# define ADC2_EXTSEL_HRTTRG1 ADC12_CFGR_EXTSEL_HRT1TRG1 -# define ADC2_EXTSEL_HRTTRG3 ADC12_CFGR_EXTSEL_HRT1TRG3 +# define ADC1_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1 +# define ADC1_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2 +# define ADC1_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4 +# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO +# define ADC2_EXTSEL_T1CC1 ADC12_CFGR1_EXTSEL_T1CC1 +# define ADC2_EXTSEL_T1CC2 ADC12_CFGR1_EXTSEL_T1CC2 +# define ADC2_EXTSEL_T1CC3 ADC12_CFGR1_EXTSEL_T1CC3 +# define ADC2_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_T1CC4 +# define ADC2_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_T1TRGO +# define ADC3_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1 +# define ADC3_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2 +# define ADC3_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3 +# define ADC3_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4 +# define ADC3_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO +# define ADC4_EXTSEL_T1CC1 ADC34_CFGR1_EXTSEL_T1CC1 +# define ADC4_EXTSEL_T1CC2 ADC34_CFGR1_EXTSEL_T1CC2 +# define ADC4_EXTSEL_T1CC3 ADC34_CFGR1_EXTSEL_T1CC3 +# define ADC4_EXTSEL_T1CC4 ADC34_CFGR1_EXTSEL_T1CC4 +# define ADC4_EXTSEL_T1TRGO ADC34_CFGR1_EXTSEL_T1TRGO +# define ADC1_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1 +# define ADC1_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2 +# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3 +# define ADC1_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO +# define ADC2_EXTSEL_T2CC1 ADC12_CFGR1_EXTSEL_T2CC1 +# define ADC2_EXTSEL_T2CC2 ADC12_CFGR1_EXTSEL_T2CC2 +# define ADC2_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_T2CC3 +# define ADC2_EXTSEL_T2CC4 ADC12_CFGR1_EXTSEL_T2CC4 +# define ADC2_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_T2TRGO +# define ADC3_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1 +# define ADC3_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2 +# define ADC3_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3 +# define ADC3_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4 +# define ADC3_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO +# define ADC4_EXTSEL_T2CC1 ADC34_CFGR1_EXTSEL_T2CC1 +# define ADC4_EXTSEL_T2CC2 ADC34_CFGR1_EXTSEL_T2CC2 +# define ADC4_EXTSEL_T2CC3 ADC34_CFGR1_EXTSEL_T2CC3 +# define ADC4_EXTSEL_T2CC4 ADC34_CFGR1_EXTSEL_T2CC4 +# define ADC4_EXTSEL_T2TRGO ADC34_CFGR1_EXTSEL_T2TRGO +# define ADC1_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1 +# define ADC1_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2 +# define ADC1_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3 +# define ADC1_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO +# define ADC2_EXTSEL_T3CC1 ADC12_CFGR1_EXTSEL_T3CC1 +# define ADC2_EXTSEL_T3CC2 ADC12_CFGR1_EXTSEL_T3CC2 +# define ADC2_EXTSEL_T3CC3 ADC12_CFGR1_EXTSEL_T3CC3 +# define ADC2_EXTSEL_T3CC4 ADC12_CFGR1_EXTSEL_T3CC4 +# define ADC2_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_T3TRGO +# define ADC3_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1 +# define ADC3_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2 +# define ADC3_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3 +# define ADC3_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4 +# define ADC3_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO +# define ADC4_EXTSEL_T3CC1 ADC34_CFGR1_EXTSEL_T3CC1 +# define ADC4_EXTSEL_T3CC2 ADC34_CFGR1_EXTSEL_T3CC2 +# define ADC4_EXTSEL_T3CC3 ADC34_CFGR1_EXTSEL_T3CC3 +# define ADC4_EXTSEL_T3CC4 ADC34_CFGR1_EXTSEL_T3CC4 +# define ADC4_EXTSEL_T3TRGO ADC34_CFGR1_EXTSEL_T3TRGO +# define ADC1_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1 +# define ADC1_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2 +# define ADC1_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3 +# define ADC1_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4 +# define ADC1_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO +# define ADC2_EXTSEL_T4CC1 ADC12_CFGR1_EXTSEL_T4CC1 +# define ADC2_EXTSEL_T4CC2 ADC12_CFGR1_EXTSEL_T4CC2 +# define ADC2_EXTSEL_T4CC3 ADC12_CFGR1_EXTSEL_T4CC3 +# define ADC2_EXTSEL_T4CC4 ADC12_CFGR1_EXTSEL_T4CC4 +# define ADC2_EXTSEL_T4TRGO ADC12_CFGR1_EXTSEL_T4TRGO +# define ADC3_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1 +# define ADC3_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2 +# define ADC3_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3 +# define ADC3_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4 +# define ADC3_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO +# define ADC4_EXTSEL_T4CC1 ADC34_CFGR1_EXTSEL_T4CC1 +# define ADC4_EXTSEL_T4CC2 ADC34_CFGR1_EXTSEL_T4CC2 +# define ADC4_EXTSEL_T4CC3 ADC34_CFGR1_EXTSEL_T4CC3 +# define ADC4_EXTSEL_T4CC4 ADC34_CFGR1_EXTSEL_T4CC4 +# define ADC4_EXTSEL_T4TRGO ADC34_CFGR1_EXTSEL_T4TRGO +# define ADC1_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1 +# define ADC1_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2 +# define ADC1_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3 +# define ADC1_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4 +# define ADC1_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO +# define ADC2_EXTSEL_T5CC1 ADC12_CFGR1_EXTSEL_T5CC1 +# define ADC2_EXTSEL_T5CC2 ADC12_CFGR1_EXTSEL_T5CC2 +# define ADC2_EXTSEL_T5CC3 ADC12_CFGR1_EXTSEL_T5CC3 +# define ADC2_EXTSEL_T5CC4 ADC12_CFGR1_EXTSEL_T5CC4 +# define ADC2_EXTSEL_T5TRGO ADC12_CFGR1_EXTSEL_T5TRGO +# define ADC3_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1 +# define ADC3_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2 +# define ADC3_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3 +# define ADC3_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4 +# define ADC3_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO +# define ADC4_EXTSEL_T5CC1 ADC34_CFGR1_EXTSEL_T5CC1 +# define ADC4_EXTSEL_T5CC2 ADC34_CFGR1_EXTSEL_T5CC2 +# define ADC4_EXTSEL_T5CC3 ADC34_CFGR1_EXTSEL_T5CC3 +# define ADC4_EXTSEL_T5CC4 ADC34_CFGR1_EXTSEL_T5CC4 +# define ADC4_EXTSEL_T5TRGO ADC34_CFGR1_EXTSEL_T5TRGO +# define ADC1_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1 +# define ADC1_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2 +# define ADC1_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3 +# define ADC1_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4 +# define ADC1_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO +# define ADC2_EXTSEL_T6CC1 ADC12_CFGR1_EXTSEL_T6CC1 +# define ADC2_EXTSEL_T6CC2 ADC12_CFGR1_EXTSEL_T6CC2 +# define ADC2_EXTSEL_T6CC3 ADC12_CFGR1_EXTSEL_T6CC3 +# define ADC2_EXTSEL_T6CC4 ADC12_CFGR1_EXTSEL_T6CC4 +# define ADC2_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_T6TRGO +# define ADC3_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1 +# define ADC3_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2 +# define ADC3_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3 +# define ADC3_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4 +# define ADC3_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO +# define ADC4_EXTSEL_T6CC1 ADC34_CFGR1_EXTSEL_T6CC1 +# define ADC4_EXTSEL_T6CC2 ADC34_CFGR1_EXTSEL_T6CC2 +# define ADC4_EXTSEL_T6CC3 ADC34_CFGR1_EXTSEL_T6CC3 +# define ADC4_EXTSEL_T6CC4 ADC34_CFGR1_EXTSEL_T6CC4 +# define ADC4_EXTSEL_T6TRGO ADC34_CFGR1_EXTSEL_T6TRGO +# define ADC1_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1 +# define ADC1_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2 +# define ADC1_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3 +# define ADC1_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4 +# define ADC1_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO +# define ADC2_EXTSEL_T7CC1 ADC12_CFGR1_EXTSEL_T7CC1 +# define ADC2_EXTSEL_T7CC2 ADC12_CFGR1_EXTSEL_T7CC2 +# define ADC2_EXTSEL_T7CC3 ADC12_CFGR1_EXTSEL_T7CC3 +# define ADC2_EXTSEL_T7CC4 ADC12_CFGR1_EXTSEL_T7CC4 +# define ADC2_EXTSEL_T7TRGO ADC12_CFGR1_EXTSEL_T7TRGO +# define ADC3_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1 +# define ADC3_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2 +# define ADC3_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3 +# define ADC3_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4 +# define ADC3_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO +# define ADC4_EXTSEL_T7CC1 ADC34_CFGR1_EXTSEL_T7CC1 +# define ADC4_EXTSEL_T7CC2 ADC34_CFGR1_EXTSEL_T7CC2 +# define ADC4_EXTSEL_T7CC3 ADC34_CFGR1_EXTSEL_T7CC3 +# define ADC4_EXTSEL_T7CC4 ADC34_CFGR1_EXTSEL_T7CC4 +# define ADC4_EXTSEL_T7TRGO ADC34_CFGR1_EXTSEL_T7TRGO +# define ADC1_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1 +# define ADC1_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2 +# define ADC1_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3 +# define ADC1_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4 +# define ADC1_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO +# define ADC2_EXTSEL_T8CC1 ADC12_CFGR1_EXTSEL_T8CC1 +# define ADC2_EXTSEL_T8CC2 ADC12_CFGR1_EXTSEL_T8CC2 +# define ADC2_EXTSEL_T8CC3 ADC12_CFGR1_EXTSEL_T8CC3 +# define ADC2_EXTSEL_T8CC4 ADC12_CFGR1_EXTSEL_T8CC4 +# define ADC2_EXTSEL_T8TRGO ADC12_CFGR1_EXTSEL_T8TRGO +# define ADC3_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1 +# define ADC3_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2 +# define ADC3_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3 +# define ADC3_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4 +# define ADC3_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO +# define ADC4_EXTSEL_T8CC1 ADC34_CFGR1_EXTSEL_T8CC1 +# define ADC4_EXTSEL_T8CC2 ADC34_CFGR1_EXTSEL_T8CC2 +# define ADC4_EXTSEL_T8CC3 ADC34_CFGR1_EXTSEL_T8CC3 +# define ADC4_EXTSEL_T8CC4 ADC34_CFGR1_EXTSEL_T8CC4 +# define ADC4_EXTSEL_T8TRGO ADC34_CFGR1_EXTSEL_T8TRGO +# define ADC1_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1 +# define ADC1_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2 +# define ADC1_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3 +# define ADC1_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4 +# define ADC1_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO +# define ADC2_EXTSEL_T9CC1 ADC12_CFGR1_EXTSEL_T9CC1 +# define ADC2_EXTSEL_T9CC2 ADC12_CFGR1_EXTSEL_T9CC2 +# define ADC2_EXTSEL_T9CC3 ADC12_CFGR1_EXTSEL_T9CC3 +# define ADC2_EXTSEL_T9CC4 ADC12_CFGR1_EXTSEL_T9CC4 +# define ADC2_EXTSEL_T9TRGO ADC12_CFGR1_EXTSEL_T9TRGO +# define ADC3_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1 +# define ADC3_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2 +# define ADC3_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3 +# define ADC3_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4 +# define ADC3_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO +# define ADC4_EXTSEL_T9CC1 ADC34_CFGR1_EXTSEL_T9CC1 +# define ADC4_EXTSEL_T9CC2 ADC34_CFGR1_EXTSEL_T9CC2 +# define ADC4_EXTSEL_T9CC3 ADC34_CFGR1_EXTSEL_T9CC3 +# define ADC4_EXTSEL_T9CC4 ADC34_CFGR1_EXTSEL_T9CC4 +# define ADC4_EXTSEL_T9TRGO ADC34_CFGR1_EXTSEL_T9TRGO +# define ADC1_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1 +# define ADC1_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2 +# define ADC1_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3 +# define ADC1_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4 +# define ADC1_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO +# define ADC2_EXTSEL_T10CC1 ADC12_CFGR1_EXTSEL_T10CC1 +# define ADC2_EXTSEL_T10CC2 ADC12_CFGR1_EXTSEL_T10CC2 +# define ADC2_EXTSEL_T10CC3 ADC12_CFGR1_EXTSEL_T10CC3 +# define ADC2_EXTSEL_T10CC4 ADC12_CFGR1_EXTSEL_T10CC4 +# define ADC2_EXTSEL_T10TRGO ADC12_CFGR1_EXTSEL_T10TRGO +# define ADC3_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1 +# define ADC3_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2 +# define ADC3_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3 +# define ADC3_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4 +# define ADC3_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO +# define ADC4_EXTSEL_T10CC1 ADC34_CFGR1_EXTSEL_T10CC1 +# define ADC4_EXTSEL_T10CC2 ADC34_CFGR1_EXTSEL_T10CC2 +# define ADC4_EXTSEL_T10CC3 ADC34_CFGR1_EXTSEL_T10CC3 +# define ADC4_EXTSEL_T10CC4 ADC34_CFGR1_EXTSEL_T10CC4 +# define ADC4_EXTSEL_T10TRGO ADC34_CFGR1_EXTSEL_T10TRGO +# define ADC1_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1 +# define ADC1_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2 +# define ADC1_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3 +# define ADC1_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO +# define ADC2_EXTSEL_T15CC1 ADC12_CFGR1_EXTSEL_T15CC1 +# define ADC2_EXTSEL_T15CC2 ADC12_CFGR1_EXTSEL_T15CC2 +# define ADC2_EXTSEL_T15CC3 ADC12_CFGR1_EXTSEL_T15CC3 +# define ADC2_EXTSEL_T15CC4 ADC12_CFGR1_EXTSEL_T15CC4 +# define ADC2_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_T15TRGO +# define ADC3_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1 +# define ADC3_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2 +# define ADC3_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3 +# define ADC3_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4 +# define ADC3_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO +# define ADC4_EXTSEL_T15CC1 ADC34_CFGR1_EXTSEL_T15CC1 +# define ADC4_EXTSEL_T15CC2 ADC34_CFGR1_EXTSEL_T15CC2 +# define ADC4_EXTSEL_T15CC3 ADC34_CFGR1_EXTSEL_T15CC3 +# define ADC4_EXTSEL_T15CC4 ADC34_CFGR1_EXTSEL_T15CC4 +# define ADC4_EXTSEL_T15TRGO ADC34_CFGR1_EXTSEL_T15TRGO +# define ADC1_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1 +# define ADC1_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2 +# define ADC1_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3 +# define ADC1_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4 +# define ADC1_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO +# define ADC2_EXTSEL_T20CC1 ADC12_CFGR1_EXTSEL_T20CC1 +# define ADC2_EXTSEL_T20CC2 ADC12_CFGR1_EXTSEL_T20CC2 +# define ADC2_EXTSEL_T20CC3 ADC12_CFGR1_EXTSEL_T20CC3 +# define ADC2_EXTSEL_T20CC4 ADC12_CFGR1_EXTSEL_T20CC4 +# define ADC2_EXTSEL_T20TRGO ADC12_CFGR1_EXTSEL_T20TRGO +# define ADC3_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1 +# define ADC3_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2 +# define ADC3_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3 +# define ADC3_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4 +# define ADC3_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO +# define ADC4_EXTSEL_T20CC1 ADC34_CFGR1_EXTSEL_T20CC1 +# define ADC4_EXTSEL_T20CC2 ADC34_CFGR1_EXTSEL_T20CC2 +# define ADC4_EXTSEL_T20CC3 ADC34_CFGR1_EXTSEL_T20CC3 +# define ADC4_EXTSEL_T20CC4 ADC34_CFGR1_EXTSEL_T20CC4 +# define ADC4_EXTSEL_T20TRGO ADC34_CFGR1_EXTSEL_T20TRGO +# define ADC1_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1 +# define ADC1_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3 +# define ADC2_EXTSEL_HRTTRG1 ADC12_CFGR1_EXTSEL_HRT1TRG1 +# define ADC2_EXTSEL_HRTTRG3 ADC12_CFGR1_EXTSEL_HRT1TRG3 #else # define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 # define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 @@ -1856,13 +1848,6 @@ * Public Types ************************************************************************************/ -#if defined(CONFIG_STM32_STM32F10XX) -enum adc_io_cmds_e -{ - IO_ENABLE_TEMPER_VOLT_CH = 0, -}; - -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) /* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are connected * to the same ADC internal channel (ADC1_IN18). Only one conversion, either * temperature sensor or VBAT, must be selected at a time. When both conversion are @@ -1871,27 +1856,39 @@ enum adc_io_cmds_e enum adc_io_cmds_e { - IO_ENABLE_TEMPER_VOLT_CH = 0, +#if defined(HAVE_IP_ADC_V1) + IO_ENABLE_TEMPER_VOLT_CH, +#endif +#ifdef HAVE_ADC_VBAT IO_ENABLE_DISABLE_VBAT_CH, -}; - -#elif defined(CONFIG_STM32_STM32L15XX) -enum adc_io_cmds_e -{ - IO_ENABLE_TEMPER_VOLT_CH = 0, - IO_ENABLE_DISABLE_PDI, - IO_ENABLE_DISABLE_PDD, - IO_ENABLE_DISABLE_PDD_PDI, +#endif IO_ENABLE_DISABLE_AWDIE, IO_ENABLE_DISABLE_EOCIE, IO_ENABLE_DISABLE_JEOCIE, - IO_ENABLE_DISABLE_OVRIE = 7, + IO_ENABLE_DISABLE_OVRIE, IO_ENABLE_DISABLE_ALL_INTS, - IO_START_CONV, IO_STOP_ADC, IO_START_ADC, + IO_START_CONV, +#ifdef HAVE_ADC_POWERDOWN + IO_ENABLE_DISABLE_PDI, + IO_ENABLE_DISABLE_PDD, + IO_ENABLE_DISABLE_PDD_PDI +#endif }; +/* ADC resolution can be reduced in order to perform faster conversion */ + +enum stm32_adc_resoluton_e +{ + ADC_RESOLUTION_12BIT = 0, /* 12 bit */ + ADC_RESOLUTION_10BIT = 1, /* 10 bit */ + ADC_RESOLUTION_8BIT = 2, /* 8 bit */ + ADC_RESOLUTION_6BIT = 3 /* 6 bit */ +}; + +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME + /* Channel and sample time pair */ typedef struct adc_channel_s @@ -1920,27 +1917,16 @@ struct adc_sample_time_s { adc_channel_t *channel; /* Array of channels */ uint8_t channels_nbr:5; /* Number of channels in array */ - bool all_same:1; /* All 32 channels will get the + bool all_same:1; /* All channels will get the * same value of the sample time */ - uint8_t all_ch_sample_time:3; /* Sample time for all 32 channels */ + uint8_t all_ch_sample_time:3; /* Sample time for all channels */ }; - #endif #ifdef CONFIG_STM32_STM32F33XX /* At this moment only for STM32F33XX family */ -/* ADC resolution can be reduced in order to perform faster conversion */ - -enum stm32_adc_resoluton_e -{ - ADC_RESOLUTION_12BIT = 0, /* 12 bit, 15 ADCCLK cycles */ - ADC_RESOLUTION_10BIT = 1, /* 10 bit, 12 ADCCLK cycles */ - ADC_RESOLUTION_8BIT = 2, /* 8 bit, 10 ADCCLK cycles */ - ADC_RESOLUTION_6BIT = 3 /* 6 bit, 8 ADCCLK cycles */ -}; - #ifdef CONFIG_STM32_ADC_NOIRQ /* This structure provides the publicly visable representation of the @@ -2024,7 +2010,7 @@ struct adc_dev_s; struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, int nchannels); -#ifdef CONFIG_STM32_STM32L15XX +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev, FAR struct adc_sample_time_s *time_samples); #endif diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h index e9878d1157..96ce90c4be 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/stm32/stm32_dma.h @@ -60,6 +60,26 @@ # error "Unknown STM32 DMA" #endif +/* Support for STM32 DMA IP version 1 - F0, F1, F3, L0, L1 + * REVISIT: move this to Kconfig + */ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# define HAVE_IP_DMA_V1 +#endif + +/* Support for STM32 DMA IP version 2 - F2, F4, F7, H7 */ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# define HAVE_IP_DMA_V2 +#endif + +#if !defined(HAVE_IP_DMA_V1) && !defined(HAVE_IP_DMA_V2) +# error Unknown STM32 DMA IP version +#endif + /* These definitions provide the bit encoding of the 'status' parameter passed to the * DMA callback function (see dma_callback_t). */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index ec521ee881..ed39ad3bda 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -61,6 +61,10 @@ /* This module then only compiles if there is at least one enabled timer * intended for use with the PWM upper half driver. + * + * It implements support for both: + * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 + * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ */ #if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ @@ -3148,7 +3152,6 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev) ret = pwm_soft_break(dev, false); if (ret < 0) - { goto errout; } diff --git a/arch/arm/src/stm32/stm32f33xxx_adc.c b/arch/arm/src/stm32/stm32f33xxx_adc.c index 77d326ccb5..6c9653a0fd 100644 --- a/arch/arm/src/stm32/stm32f33xxx_adc.c +++ b/arch/arm/src/stm32/stm32f33xxx_adc.c @@ -119,10 +119,6 @@ # define ADC2_HAVE_JEXTSEL #endif -#if defined(CONFIG_STM32_ADC_NOIRQ) && defined(ADC_HAVE_DMA) -# error "ADC DMA support requires common ADC interrupts" -#endif - /* RCC reset ****************************************************************/ #define STM32_RCC_RSTR STM32_RCC_AHBRSTR @@ -132,12 +128,12 @@ /* ADC interrupts ***********************************************************/ -#define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET -#define ADC_DMAREG_DMA ADC_CFGR_DMAEN -#define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET -#define ADC_EXTREG_EXTSEL_MASK ADC_CFGR_EXTSEL_MASK -#define ADC_EXTREG_EXTEN_MASK ADC_CFGR_EXTEN_MASK -#define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR_EXTEN_RISING +#define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET +#define ADC_DMAREG_DMA ADC_CFGR1_DMAEN +#define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET +#define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK +#define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK +#define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING #define STM32_ADC_JEXTREG_OFFSET STM32_ADC_JSQR_OFFSET #define ADC_JEXTREG_JEXTSEL_MASK ADC_JSQR_JEXTSEL_MASK #define ADC_JEXTREG_JEXTEN_MASK ADC_JSQR_JEXTEN_MASK @@ -374,10 +370,10 @@ /* Default ADC DMA configuration */ #ifndef ADC1_DMA_CFG -# define ADC1_DMA_CFG ADC_CFGR_DMACFG +# define ADC1_DMA_CFG ADC_CFGR1_DMACFG #endif #ifndef ADC2_DMA_CFG -# define ADC2_DMA_CFG ADC_CFGR_DMACFG +# define ADC2_DMA_CFG ADC_CFGR1_DMACFG #endif /**************************************************************************** @@ -1591,42 +1587,42 @@ static void adc_reset(FAR struct adc_dev_s *dev) /* Enable the analog watchdog */ - clrbits = ADC_CFGR_AWD1CH_MASK; - setbits = ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | - (priv->r_chanlist[0] << ADC_CFGR_AWD1CH_SHIFT); + clrbits = ADC_CFGR1_AWD1CH_MASK; + setbits = ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | + (priv->r_chanlist[0] << ADC_CFGR1_AWD1CH_SHIFT); /* Set the resolution of the conversion */ - clrbits |= ADC_CFGR_RES_MASK; - setbits |= priv->resolution << ADC_CFGR_RES_SHIFT; + clrbits |= ADC_CFGR1_RES_MASK; + setbits |= priv->resolution << ADC_CFGR1_RES_SHIFT; #ifdef ADC_HAVE_DMA if (priv->hasdma) { /* Set DMA mode */ - clrbits |= ADC_CFGR_DMACFG; + clrbits |= ADC_CFGR1_DMACFG; setbits |= priv->dmacfg; /* Enable DMA */ - setbits |= ADC_CFGR_DMAEN; + setbits |= ADC_CFGR1_DMAEN; } #endif /* Disable continuous mode and set align to right */ - clrbits |= ADC_CFGR_CONT | ADC_CFGR_ALIGN; + clrbits |= ADC_CFGR1_CONT | ADC_CFGR1_ALIGN; /* Disable external trigger for regular channels */ - clrbits |= ADC_CFGR_EXTEN_MASK; - setbits |= ADC_CFGR_EXTEN_NONE; + clrbits |= ADC_CFGR1_EXTEN_MASK; + setbits |= ADC_CFGR1_EXTEN_NONE; /* Set CFGR configuration */ - adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits); #ifndef CONFIG_STM32_ADC_NOIRQ /* Enable interrupt flags, but disable overrun interrupt */ @@ -1752,7 +1748,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n", adc_getreg(priv, STM32_ADC_ISR_OFFSET), adc_getreg(priv, STM32_ADC_CR_OFFSET), - adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); + adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR1_OFFSET), diff --git a/configs/nucleo-f303ze/adc/defconfig b/configs/nucleo-f303ze/adc/defconfig new file mode 100644 index 0000000000..1145714683 --- /dev/null +++ b/configs/nucleo-f303ze/adc/defconfig @@ -0,0 +1,55 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303ze" +CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_ADC3_RESOLUTION=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSLOG_NONE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=1 diff --git a/configs/nucleo-f303ze/include/board.h b/configs/nucleo-f303ze/include/board.h index 3bc5e94e5d..4bc4ee1e1a 100644 --- a/configs/nucleo-f303ze/include/board.h +++ b/configs/nucleo-f303ze/include/board.h @@ -198,4 +198,9 @@ #define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */ #define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */ +/* DMA **********************************************************************/ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 +#define ADC3_DMA_CHAN DMACHAN_ADC3 + #endif /* __CONFIG_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-f303ze/src/Makefile b/configs/nucleo-f303ze/src/Makefile index bef6f33efc..9f6c5cb074 100644 --- a/configs/nucleo-f303ze/src/Makefile +++ b/configs/nucleo-f303ze/src/Makefile @@ -52,4 +52,8 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/nucleo-f303ze/src/nucleo-f303ze.h b/configs/nucleo-f303ze/src/nucleo-f303ze.h index 1c794b26f8..8e0f4cfa8f 100644 --- a/configs/nucleo-f303ze/src/nucleo-f303ze.h +++ b/configs/nucleo-f303ze/src/nucleo-f303ze.h @@ -92,4 +92,18 @@ * Public Function Prototypes ****************************************************************************/ +int stm32_bringup(void); + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F303ZE_SRC_NUCLEO_F303ZE_H */ diff --git a/configs/nucleo-f303ze/src/stm32_adc.c b/configs/nucleo-f303ze/src/stm32_adc.c new file mode 100644 index 0000000000..35bc9caf52 --- /dev/null +++ b/configs/nucleo-f303ze/src/stm32_adc.c @@ -0,0 +1,253 @@ +/**************************************************************************** + * configs/nucleo-f303ze/src/stm32_adc.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC3_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 4, + 6, + 9 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN4, /* PA3/A0 */ + GPIO_ADC1_IN6, /* PC0/A1 */ + GPIO_ADC1_IN9, /* PC3/A2 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN8, /* PD11/A3 */ + GPIO_ADC3_IN9, /* PD12/A4 */ + GPIO_ADC3_IN10, /* PD13/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN8, /* PD11/A3 */ + GPIO_ADC3_IN9, /* PD12/A4 */ + GPIO_ADC3_IN10, /* PD13/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + FAR struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/configs/nucleo-f303ze/src/stm32_bringup.c b/configs/nucleo-f303ze/src/stm32_bringup.c index 18f9eff74e..134939e9df 100644 --- a/configs/nucleo-f303ze/src/stm32_bringup.c +++ b/configs/nucleo-f303ze/src/stm32_bringup.c @@ -74,5 +74,15 @@ int stm32_bringup(void) UNUSED(ret); +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + return OK; } diff --git a/configs/stm32f429i-disco/adc/defconfig b/configs/stm32f429i-disco/adc/defconfig new file mode 100644 index 0000000000..a4ba9b84d9 --- /dev/null +++ b/configs/stm32f429i-disco/adc/defconfig @@ -0,0 +1,65 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_CCMEXCLUDE is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=3 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_FSMC_SRAM=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/stm32f429i-disco/include/board.h b/configs/stm32f429i-disco/include/board.h index c6db54ba9d..9b177c6062 100644 --- a/configs/stm32f429i-disco/include/board.h +++ b/configs/stm32f429i-disco/include/board.h @@ -443,4 +443,9 @@ #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) #endif /* CONFIG_STM32_LTDC */ + +/* DMA *************************************************************************/ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + #endif /* __CONFIG_STM32F429I_DISCO_INCLUDE_BOARD_H */ diff --git a/configs/stm32f429i-disco/src/Makefile b/configs/stm32f429i-disco/src/Makefile index d00fe9fa79..802a39ea6d 100644 --- a/configs/stm32f429i-disco/src/Makefile +++ b/configs/stm32f429i-disco/src/Makefile @@ -91,4 +91,8 @@ ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f429i-disco/src/stm32_adc.c b/configs/stm32f429i-disco/src/stm32_adc.c new file mode 100644 index 0000000000..f8319d4118 --- /dev/null +++ b/configs/stm32f429i-disco/src/stm32_adc.c @@ -0,0 +1,247 @@ +/**************************************************************************** + * configs/nucleo-f303ze/src/stm32_adc.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ +/* TODO DMA */ + +#define ADC1_NCHANNELS 2 +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[2] = +{ + 5, + 13, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[2] = +{ + GPIO_ADC1_IN5, /* PA5 */ + GPIO_ADC1_IN13, /* PC3 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[1] = +{ + 4, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[1] = +{ + GPIO_ADC3_IN4, /* PF6 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN8, /* PD11/A3 */ + GPIO_ADC3_IN9, /* PD12/A4 */ + GPIO_ADC3_IN10, /* PD13/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + FAR struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/configs/stm32f429i-disco/src/stm32_bringup.c b/configs/stm32f429i-disco/src/stm32_bringup.c index 5d8bdc223d..9e84f471b4 100644 --- a/configs/stm32f429i-disco/src/stm32_bringup.c +++ b/configs/stm32f429i-disco/src/stm32_bringup.c @@ -376,6 +376,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC device. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/stm32f429i-disco/src/stm32f429i-disco.h b/configs/stm32f429i-disco/src/stm32f429i-disco.h index 8fc6be2966..d7f2e95297 100644 --- a/configs/stm32f429i-disco/src/stm32f429i-disco.h +++ b/configs/stm32f429i-disco/src/stm32f429i-disco.h @@ -403,5 +403,17 @@ int stm32_l3gd20initialize(FAR const char *devpath); int stm32_pwm_setup(void); #endif +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC device. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F429I_DISCO_SRC_STM32F429I_DISCO_H */