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armv7-a: icache also need SMP cache coherency configuration

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This can fixes the random crash happened sometime during boot.

Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit is contained in:
ligd 2022-08-25 22:19:14 +08:00 committed by Xiang Xiao
parent 69feebe48c
commit bedd5d382d
4 changed files with 5 additions and 5 deletions
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4
arch/arm/src/armv7-a/arm_cpuhead.S
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@ -318,7 +318,7 @@ __cpu3_start:
* after SMP cache coherency has been setup. * after SMP cache coherency has been setup.
*/ */
#if 0 /* !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) */ #if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP)
/* Dcache enable /* Dcache enable
* *
* SCTLR_C Bit 2: DCache enable * SCTLR_C Bit 2: DCache enable
@ -327,7 +327,7 @@ __cpu3_start:
orr r0, r0, #(SCTLR_C) orr r0, r0, #(SCTLR_C)
#endif #endif
#ifndef CPU_ICACHE_DISABLE #if !defined(CPU_ICACHE_DISABLE) && !defined(CONFIG_SMP)
/* Icache enable /* Icache enable
* *
* SCTLR_I Bit 12: ICache enable * SCTLR_I Bit 12: ICache enable

2
arch/arm/src/armv7-a/arm_head.S
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@ -452,7 +452,7 @@ __start:
orr r0, r0, #(SCTLR_C) orr r0, r0, #(SCTLR_C)
#endif #endif
#ifndef CPU_ICACHE_DISABLE #if !defined(CPU_ICACHE_DISABLE) && !defined(CONFIG_SMP)
/* Icache enable /* Icache enable
* *
* SCTLR_I Bit 12: ICache enable * SCTLR_I Bit 12: ICache enable

2
arch/arm/src/armv7-a/arm_pghead.S
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@ -434,7 +434,7 @@ __start:
orr r0, r0, #(SCTLR_C) orr r0, r0, #(SCTLR_C)
#endif #endif
#ifndef CPU_ICACHE_DISABLE #if !defined(CPU_ICACHE_DISABLE) && !defined(CONFIG_SMP)
/* Icache enable /* Icache enable
* *
* SCTLR_I Bit 12: ICache enable * SCTLR_I Bit 12: ICache enable

2
arch/arm/src/armv7-a/arm_scu.c
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@ -203,6 +203,6 @@ void arm_enable_smp(int cpu)
arm_set_actlr(regval); arm_set_actlr(regval);
regval = arm_get_sctlr(); regval = arm_get_sctlr();
regval |= SCTLR_C; regval |= SCTLR_C | SCTLR_I;
arm_set_sctlr(regval); arm_set_sctlr(regval);
} }