risc-v/esp32c3: Add driver for General Purpose SPI Master

arch/risc-v/src/esp32c3/Kconfig

@@ -178,8 +178,13 @@ config ESP32C3_WDT
 	bool
 	default n
 
+config ESP32C3_SPI
+	bool
+	default n
+
 config ESP32C3_GPIO_IRQ
 	bool "GPIO pin interrupts"
+	default n
 	---help---
 		Enable support for interrupting GPIO pins
 
@@ -230,6 +235,12 @@ config ESP32C3_SPIFLASH
 	select MTD_BYTE_WRITE
 	select MTD_PARTITION
 
+config ESP32C3_SPI2
+	bool "SPI 2"
+	default n
+	select ESP32C3_SPI
+	select SPI
+
 config ESP32C3_MWDT0
 	bool "Main System Watchdog Timer (Group 0)"
 	default n
@@ -288,6 +299,48 @@ endif # ESP32C3_I2C0
 
 endmenu # I2C configuration
 
+menu "SPI configuration"
+	depends on ESP32C3_SPI
+
+config ESP32C3_SPI_SWCS
+	bool "SPI software CS"
+	default n
+	---help---
+		Use SPI software CS.
+
+config ESP32C3_SPI_UDCS
+	bool "User defined CS"
+	default n
+	depends on ESP32C3_SPI_SWCS
+	---help---
+		Use user-defined CS.
+
+if ESP32C3_SPI2
+
+config ESP32C3_SPI2_CSPIN
+	int "SPI2 CS Pin"
+	default 10
+	range 0 21
+
+config ESP32C3_SPI2_CLKPIN
+	int "SPI2 CLK Pin"
+	default 6
+	range 0 21
+
+config ESP32C3_SPI2_MOSIPIN
+	int "SPI2 MOSI Pin"
+	default 7
+	range 0 21
+
+config ESP32C3_SPI2_MISOPIN
+	int "SPI2 MISO Pin"
+	default 2
+	range 0 21
+
+endif # ESP32C3_SPI2
+
+endmenu # SPI configuration
+
 menu "UART configuration"
 	depends on ESP32C3_UART
 

arch/risc-v/src/esp32c3/Make.defs

@@ -63,6 +63,10 @@ ifeq ($(CONFIG_ESP32C3_I2C),y)
 CHIP_CSRCS += esp32c3_i2c.c
 endif
 
+ifeq ($(CONFIG_ESP32C3_SPI),y)
+CHIP_CSRCS += esp32c3_spi.c
+endif
+
 ifeq ($(CONFIG_ESP32C3_SPIFLASH),y)
 CHIP_CSRCS += esp32c3_spiflash.c
 endif

arch/risc-v/src/esp32c3/esp32c3_spi.h

@@ -0,0 +1,137 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/esp32c3_spi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPI_H
+#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#ifdef CONFIG_ESP32C3_SPI
+
+#include <nuttx/spi/spi.h>
+
+#ifdef CONFIG_ESP32C3_SPI2
+#  define ESP32C3_SPI2 2
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_spibus_initialize
+ *
+ * Description:
+ *   Initialize the selected SPI bus.
+ *
+ * Input Parameters:
+ *   port     - Port number (for hardware that has multiple SPI interfaces)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on success; NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *esp32c3_spibus_initialize(int port);
+
+/****************************************************************************
+ * Name:  esp32c3_spi[0|1]_select and esp32c3_spi[0|1]_status
+ *
+ * Description:
+ *   The external functions, esp32c3_spi[0|1]_select,
+ *   esp32c3_spi[0|1]_status, and esp32c3_spi[0|1]_cmddata must be provided
+ *   by board-specific logic.
+ *   These are implementations of the select, status, and cmddata methods of
+ *   the SPI interface defined by struct spi_ops_s (include/nuttx/spi/spi.h).
+ *   All other methods (including esp32c3_spibus_initialize()) are provided
+ *   by common ESP32-C3 logic. To use this common SPI logic on your board:
+ *
+ *   1. Provide logic in esp32c3_board_initialize() to configure SPI chip
+ *      select pins.
+ *   2. Provide esp32c3_spi[0|1]_select() and esp32c3_spi[0|1]_status()
+ *      functions in your board-specific logic. These functions will perform
+ *      chip selection and status operations using GPIOs in the way your
+ *      board is configured.
+ *   3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
+ *      then provide esp32c3_spi[0|1]_cmddata() functions in your
+ *      board-specific logic. These functions will perform cmd/data selection
+ *      operations using GPIOs in the way your board is configured.
+ *   4. Add a call to esp32c3_spibus_initialize() in your low level
+ *      application initialization logic.
+ *   5. The handle returned by esp32c3_spibus_initialize() may then be used
+ *      to bind the SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_SPI2
+void esp32c3_spi2_select(FAR struct spi_dev_s *dev, uint32_t devid,
+                         bool selected);
+uint8_t esp32c3_spi2_status(FAR struct spi_dev_s *dev, uint32_t devid);
+int esp32c3_spi2_cmddata(FAR struct spi_dev_s *dev,
+                         uint32_t devid,
+                         bool cmd);
+#endif
+
+/****************************************************************************
+ * Name: esp32c3_spibus_uninitialize
+ *
+ * Description:
+ *   Uninitialize an SPI bus.
+ *
+ * Input Parameters:
+ *   dev      - Device-specific state data
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success.  Otherwise -1 (ERROR).
+ *
+ ****************************************************************************/
+
+int esp32c3_spibus_uninitialize(FAR struct spi_dev_s *dev);
+
+#endif /* CONFIG_ESP32C3_SPI */
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPI_H */

arch/risc-v/src/esp32c3/hardware/esp32c3_pinmap.h

@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/hardware/esp32c3_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_PINMAP_H
+#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_PINMAP_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Peripheral's fixed mapped pins by IOMUX, these GPIO pins can have better
+ * speed performance.
+ */
+
+/* SPI2 */
+
+#define SPI2_IOMUX_MISOPIN      (2)
+#define SPI2_IOMUX_MOSIPIN      (7)
+#define SPI2_IOMUX_CLKPIN       (6)
+#define SPI2_IOMUX_CSPIN        (10)
+#define SPI2_IOMUX_WPPIN        (5)
+#define SPI2_IOMUX_HDPIN        (4)
+
+#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_PINMAP_H */

arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h

@@ -76,17 +76,18 @@
 /* Registers Operation */
 
 #define REG_UHCI_BASE(i)      (DR_REG_UHCI0_BASE - (i) * 0x8000)
-#define REG_UART_BASE( i )    (DR_REG_UART_BASE + (i) * 0x10000 + \
+#define REG_UART_BASE(i)      (DR_REG_UART_BASE + (i) * 0x10000 + \
                                ( (i) > 1 ? 0xe000 : 0 ) )
 #define REG_UART_AHB_BASE(i)  (0x60000000 + (i) * 0x10000 + \
                                ( (i) > 1 ? 0xe000 : 0 ) )
 #define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE( i )     (DR_REG_I2S_BASE + (i) * 0x1E000)
+#define REG_I2S_BASE(i)       (DR_REG_I2S_BASE + (i) * 0x1E000)
 #define REG_TIMG_BASE(i)      (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)   (DR_REG_SPI0_BASE - (i) * 0x1000)
+#define REG_SPI_BASE(i)       (DR_REG_SPI2_BASE)
 #define REG_I2C_BASE(i)       (DR_REG_I2C_EXT_BASE + (i) * 0x14000)
 
-/* Periheral Clock */
+/* Peripheral Clock */
 
 #define APB_CLK_FREQ_ROM        (40 * 1000000)
 #define CPU_CLK_FREQ_ROM        APB_CLK_FREQ_ROM