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photon: porting wlan device

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This commit is contained in:
Simon Piriou 2017-03-14 21:06:19 +01:00
parent dc674e24c3
commit bf9391a1fe
8 changed files with 2085 additions and 43 deletions
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81
arch/arm/src/stm32/stm32_sdio.c
View File

@ -300,6 +300,8 @@
# endif
#endif
#define STM32_SDIO_USE_DEFAULT_BLOCK_SIZE ((uint8_t)-1)
/****************************************************************************
* Private Types
****************************************************************************/
@ -333,6 +335,12 @@ struct stm32_dev_s
size_t remaining; /* Number of bytes remaining in the transfer */
uint32_t xfrmask; /* Interrupt enables for data transfer */
/* Fixed transfer block size support */
#ifdef CONFIG_SDIO_BLOCKSETUP
uint8_t block_size;
#endif
/* DMA data transfer support */
bool widebus; /* Required for DMA support */
@ -443,6 +451,10 @@ static int stm32_attach(FAR struct sdio_dev_s *dev);
static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
uint32_t arg);
#ifdef CONFIG_SDIO_BLOCKSETUP
static void stm32_blocksetup(FAR struct sdio_dev_s *dev,
unsigned int blocklen, unsigned int nblocks);
#endif
static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
size_t nbytes);
static int stm32_sendsetup(FAR struct sdio_dev_s *dev,
@ -507,7 +519,7 @@ struct stm32_dev_s g_sdiodev =
.attach = stm32_attach,
.sendcmd = stm32_sendcmd,
#ifdef CONFIG_SDIO_BLOCKSETUP
.blocksetup = stm32_blocksetup, /* Not implemented yet */
.blocksetup = stm32_blocksetup,
#endif
.recvsetup = stm32_recvsetup,
.sendsetup = stm32_sendsetup,
@ -516,8 +528,8 @@ struct stm32_dev_s g_sdiodev =
.recvR1 = stm32_recvshortcrc,
.recvR2 = stm32_recvlong,
.recvR3 = stm32_recvshort,
.recvR4 = stm32_recvnotimpl,
.recvR5 = stm32_recvnotimpl,
.recvR4 = stm32_recvshort,
.recvR5 = stm32_recvshortcrc,
.recvR6 = stm32_recvshortcrc,
.recvR7 = stm32_recvshort,
.waitenable = stm32_waitenable,
@ -1865,6 +1877,34 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
return OK;
}
/****************************************************************************
* Name: stm32_blocksetup
*
* Description:
* Configure block size and the number of blocks for next transfer
*
* Input Parameters:
* dev - An instance of the SDIO device interface
* blocklen - The selected block size.
* nblocklen - The number of blocks to transfer
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SDIO_BLOCKSETUP
static void stm32_blocksetup(FAR struct sdio_dev_s *dev,
unsigned int blocklen, unsigned int nblocks)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
/* Configure block size for next transfer */
priv->block_size = stm32_log2(blocklen);
}
#endif
/****************************************************************************
* Name: stm32_recvsetup
*
@ -1911,7 +1951,17 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Then set up the SDIO data path */
dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
#ifdef CONFIG_SDIO_BLOCKSETUP
if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
{
dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
}
else
#endif
{
dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
}
stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize | SDIO_DCTRL_DTDIR);
/* And enable interrupts */
@ -1965,7 +2015,17 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer
/* Then set up the SDIO data path */
dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
#ifdef CONFIG_SDIO_BLOCKSETUP
if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
{
dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
}
else
#endif
{
dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
}
stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize);
/* Enable TX interrupts */
@ -2061,15 +2121,13 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
case MMCSD_R1_RESPONSE:
case MMCSD_R1B_RESPONSE:
case MMCSD_R2_RESPONSE:
case MMCSD_R4_RESPONSE:
case MMCSD_R5_RESPONSE:
case MMCSD_R6_RESPONSE:
events = SDIO_RESPDONE_STA;
timeout = SDIO_LONGTIMEOUT;
break;
case MMCSD_R4_RESPONSE:
case MMCSD_R5_RESPONSE:
return -ENOSYS;
case MMCSD_R3_RESPONSE:
case MMCSD_R7_RESPONSE:
events = SDIO_RESPDONE_STA;
@ -2161,6 +2219,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
{
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
@ -2201,6 +2260,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
*rshort = getreg32(STM32_SDIO_RESP1);
mcinfo("data: %08x %08x\n", *rshort, respcmd);
return ret;
}
@ -2276,6 +2336,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
#ifdef CONFIG_DEBUG_MEMCARD_INFO
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
@ -2300,7 +2361,9 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
if (rshort)
{
*rshort = getreg32(STM32_SDIO_RESP1);
mcinfo("data: %08x\n", *rshort);
}
return ret;
}

1355
config_wlan Normal file
View File

File diff suppressed because it is too large Load Diff

20
configs/photon/src/stm32_wlan.c
View File

@ -95,6 +95,26 @@ void bcmf_board_initialize(int minor)
bcmf_board_reset(minor, true);
}
/****************************************************************************
* Name: bcmf_board_setup_oob_irq
****************************************************************************/
void bcmf_board_setup_oob_irq(int minor)
{
if (minor != SDIO_WLAN0_MINOR)
{
return;
}
/* Configure reset pin */
stm32_configgpio(GPIO_WLAN0_RESET);
/* Put wlan chip in reset state */
bcmf_board_reset(minor, true);
}
/****************************************************************************
* Name: photon_wlan_initialize
****************************************************************************/

1
drivers/wireless/ieee80211/Make.defs
View File

@ -42,6 +42,7 @@ ifeq ($(CONFIG_DRIVERS_IEEE80211),y)
ifeq ($(CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO),y)
CSRCS += bcmf_sdio.c
CSRCS += mmc_sdio.c
endif
# Include IEEE 802.11 build support

252
drivers/wireless/ieee80211/bcmf_sdio.c
View File

@ -50,6 +50,7 @@
#include <nuttx/sdio.h>
#include <nuttx/arch.h>
#include <nuttx/wireless/ieee80211/mmc_sdio.h>
#include <nuttx/wireless/ieee80211/bcmf_sdio.h>
#include <nuttx/wireless/ieee80211/bcmf_board.h>
@ -59,7 +60,19 @@
#define BCMF_DEVICE_RESET_DELAY_MS 10
#define BCMF_DEVICE_START_DELAY_MS 10
#define BCMF_DEVICE_IDLE_DELAY_MS 50
#define BCMF_CLOCK_SETUP_DELAY_MS 500
#define SDIO_FN1_CHIPCLKCSR 0x1000E /* Clock Control Source Register */
#define SDIO_FN1_PULLUP 0x1000F /* Pull-up Control Register for cmd, D0-2 lines */
#define SDIO_FN1_CHIPCLKCSR_FORCE_ALP 0x01
#define SDIO_FN1_CHIPCLKCSR_FORCE_HT 0x02
#define SDIO_FN1_CHIPCLKCSR_FORCE_ILP 0x04
#define SDIO_FN1_CHIPCLKCSR_ALP_AVAIL_REQ 0x08
#define SDIO_FN1_CHIPCLKCSR_HT_AVAIL_REQ 0x10
#define SDIO_FN1_CHIPCLKCSR_FORCE_HW_CLKREQ_OFF 0x20
#define SDIO_FN1_CHIPCLKCSR_ALP_AVAIL 0x40
#define SDIO_FN1_CHIPCLKCSR_HT_AVAIL 0x80
/****************************************************************************
* Private Types
@ -77,8 +90,17 @@ struct bcmf_dev_s
* Private Function Prototypes
****************************************************************************/
static int bcmf_sendcmdpoll(FAR struct bcmf_dev_s *priv,
uint32_t cmd, uint32_t arg);
static int bcmf_transfer_bytes(FAR struct bcmf_dev_s *priv, bool write,
uint8_t function, uint32_t address,
uint8_t *buf, unsigned int len);
static int bcmf_read_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t *reg,
unsigned int len);
static int bcmf_write_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint32_t reg,
unsigned int len);
static int bcmf_probe(FAR struct bcmf_dev_s *priv);
static int bcmf_hwinitialize(FAR struct bcmf_dev_s *priv);
@ -93,29 +115,50 @@ static void bcmf_hwuninitialize(FAR struct bcmf_dev_s *priv);
****************************************************************************/
/****************************************************************************
* Name: bcmf_sendcmdpoll
* Name: bcmf_transfer_bytes
****************************************************************************/
int bcmf_sendcmdpoll(FAR struct bcmf_dev_s *priv, uint32_t cmd, uint32_t arg)
int bcmf_transfer_bytes(FAR struct bcmf_dev_s *priv, bool write,
uint8_t function, uint32_t address,
uint8_t *buf, unsigned int len)
{
int ret;
/* Use rw_io_direct method if len is 1 */
/* Send the command */
ret = SDIO_SENDCMD(priv->sdio_dev, cmd, arg);
if (ret == OK)
if (len == 1)
{
/* Then poll-wait until the response is available */
ret = SDIO_WAITRESPONSE(priv->sdio_dev, cmd);
if (ret != OK)
{
_err("ERROR: Wait for response to cmd: %08x failed: %d\n",
cmd, ret);
}
return sdio_io_rw_direct(priv->sdio_dev, write,
function, address, *buf, buf);
}
return ret;
// return sdio_io_rw_extended(priv->sdio_dev, write,
// function, address, *buf, buf);
return -EINVAL;
}
/****************************************************************************
* Name: bcmf_read_reg
****************************************************************************/
int bcmf_read_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint8_t *reg, unsigned int len)
{
return bcmf_transfer_bytes(priv, false, function, address, reg, len);
}
/****************************************************************************
* Name: bcmf_write_reg
****************************************************************************/
int bcmf_write_reg(FAR struct bcmf_dev_s *priv, uint8_t function,
uint32_t address, uint32_t reg, unsigned int len)
{
if (len > 4)
{
return -EINVAL;
}
return bcmf_transfer_bytes(priv, true, function, address,
(uint8_t*)&reg, len);
}
/****************************************************************************
@ -125,39 +168,88 @@ int bcmf_sendcmdpoll(FAR struct bcmf_dev_s *priv, uint32_t cmd, uint32_t arg)
int bcmf_probe(FAR struct bcmf_dev_s *priv)
{
int ret;
uint32_t data = 0;
uint8_t value;
int loops;
/* Set device state from reset to idle */
bcmf_sendcmdpoll(priv, MMCSD_CMD0, 0);
up_mdelay(BCMF_DEVICE_START_DELAY_MS);
/* Send IO_SEND_OP_COND command */
ret = bcmf_sendcmdpoll(priv, SDIO_CMD5, 0);
/* Probe sdio card compatible device */
ret = sdio_probe(priv->sdio_dev);
if (ret != OK)
{
goto exit_error;
}
/* Receive R4 response */
ret = SDIO_RECVR4(priv->sdio_dev, SDIO_CMD5, &data);
/* Enable bus FN1 */
ret = sdio_enable_function(priv->sdio_dev, 1);
if (ret != OK)
{
goto exit_error;
}
/* Broadcom chips have 2 additional functions and wide voltage range */
/* Set FN0 / FN1 / FN2 default block size */
if ((((data >> 28) & 7) != 2) ||
(((data >> 8) & 0xff80) != 0xff80))
ret = sdio_set_blocksize(priv->sdio_dev, 0, 64);
if (ret != OK)
{
goto exit_error;
}
ret = sdio_set_blocksize(priv->sdio_dev, 1, 64);
if (ret != OK)
{
goto exit_error;
}
ret = sdio_set_blocksize(priv->sdio_dev, 2, 64);
if (ret != OK)
{
goto exit_error;
}
/* Enable device interrupts for FN0, FN1 and FN2 */
ret = sdio_io_rw_direct(priv->sdio_dev, true, 0, SDIO_CCCR_INTEN,
(1 << 0) | (1 << 1) | (1 << 2), NULL);
if (ret != OK)
{
goto exit_error;
}
/* Default device clock speed is up to 25 Mhz
* We could set EHS bit to operate at a clock rate up to 50 Mhz */
SDIO_CLOCK(priv->sdio_dev, CLOCK_SD_TRANSFER_4BIT);
up_mdelay(BCMF_CLOCK_SETUP_DELAY_MS);
/* Wait for function 1 to be ready */
loops = 10;
while (--loops > 0)
{
up_mdelay(1);
ret = sdio_io_rw_direct(priv->sdio_dev, false, 0, SDIO_CCCR_IORDY, 0, &value);
if (ret != OK)
{
return ret;
}
if (value & (1 << 1))
{
/* Function 1 is ready */
break;
}
}
if (loops <= 0)
{
return -ETIMEDOUT;
}
_info("sdio fn1 ready\n");
return OK;
exit_error:
@ -166,6 +258,89 @@ exit_error:
return ret;
}
/****************************************************************************
* Name: bcmf_businitialize
****************************************************************************/
int bcmf_businitialize(FAR struct bcmf_dev_s *priv)
{
int ret;
int loops;
/* Send Active Low-Power clock request */
ret = bcmf_write_reg(priv, 1, SDIO_FN1_CHIPCLKCSR,
SDIO_FN1_CHIPCLKCSR_FORCE_HW_CLKREQ_OFF |
SDIO_FN1_CHIPCLKCSR_ALP_AVAIL_REQ |
SDIO_FN1_CHIPCLKCSR_FORCE_ALP, 1);
if (ret != OK)
{
return ret;;
}
loops = 10;
while (--loops > 0)
{
uint8_t value;
up_mdelay(10);
ret = bcmf_read_reg(priv, 1, SDIO_FN1_CHIPCLKCSR, &value, 1);
if (ret != OK)
{
return ret;
}
if (value & SDIO_FN1_CHIPCLKCSR_ALP_AVAIL)
{
/* Active Low-Power clock is ready */
break;
}
}
if (loops <= 0)
{
_err("failed to enable ALP\n");
return -ETIMEDOUT;
}
/* Clear Active Low-Power clock request */
ret = bcmf_write_reg(priv, 1, SDIO_FN1_CHIPCLKCSR, 0, 1);
if (ret != OK)
{
return ret;
}
/* Disable pull-ups on SDIO cmd, d0-2 lines */
ret = bcmf_write_reg(priv, 1, SDIO_FN1_PULLUP, 0, 1);
if (ret != OK)
{
return ret;
}
/* Enable oob gpio interrupt */
// bcmf_board_setup_oob_irq(priv->minor, bcmf_oob_irq, (void*)priv);
/* Enable F2 interrupt only */
/* Upload firmware */
/* Enable function 2 */
// ret = sdio_enable_function(priv->sdio_dev, 2);
// if (ret != OK)
// {
// goto exit_error;
// }
return OK;
}
/****************************************************************************
* Name: bcmf_hwinitialize
****************************************************************************/
@ -253,6 +428,15 @@ int bcmf_sdio_initialize(int minor, FAR struct sdio_dev_s *dev)
ret = bcmf_probe(priv);
if (ret != OK)
{
goto exit_uninit_hw;
}
/* Initialize device */
ret = bcmf_businitialize(priv);
if (ret != OK)
{
goto exit_uninit_hw;

355
drivers/wireless/ieee80211/mmc_sdio.c Normal file
View File

@ -0,0 +1,355 @@
#include <nuttx/wireless/ieee80211/mmc_sdio.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/arch.h>
#define SDIO_CMD53_TIMEOUT_MS 100
#define SDIO_IDLE_DELAY_MS 50
struct __attribute__((packed)) sdio_cmd52 {
uint32_t write_data : 8;
uint32_t reserved_8 : 1;
uint32_t register_address : 17;
uint32_t reserved_26 : 1;
uint32_t raw_flag : 1;
uint32_t function_number : 3;
uint32_t rw_flag : 1;
};
struct __attribute__((packed)) sdio_cmd53 {
uint32_t byte_block_count : 9;
uint32_t register_address : 17;
uint32_t op_code : 1;
uint32_t block_mode : 1;
uint32_t function_number : 3;
uint32_t rw_flag : 1;
};
struct __attribute__((packed)) sdio_resp_R5 {
uint32_t data : 8;
struct {
uint32_t out_of_range : 1;
uint32_t function_number : 1;
uint32_t rfu : 1;
uint32_t error : 1;
uint32_t io_current_state : 2;
uint32_t illegal_command : 1;
uint32_t com_crc_error : 1;
} flags;
uint32_t reserved_16 : 16;
};
union sdio_cmd5x {
uint32_t value;
struct sdio_cmd52 cmd52;
struct sdio_cmd53 cmd53;
};
int sdio_sendcmdpoll(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
{
int ret;
/* Send the command */
ret = SDIO_SENDCMD(dev, cmd, arg);
if (ret == OK)
{
/* Then poll-wait until the response is available */
ret = SDIO_WAITRESPONSE(dev, cmd);
if (ret != OK)
{
_err("ERROR: Wait for response to cmd: %08x failed: %d\n",
cmd, ret);
}
}
return ret;
}
int sdio_io_rw_direct(FAR struct sdio_dev_s *dev, bool write,
uint8_t function, uint32_t address,
uint8_t inb, uint8_t* outb)
{
union sdio_cmd5x arg;
struct sdio_resp_R5 resp;
int ret;
/* Setup CMD52 argument */
arg.cmd52.write_data = inb;
arg.cmd52.register_address = address & 0x1ffff;
arg.cmd52.raw_flag = (write && outb);
arg.cmd52.function_number = function & 7;
arg.cmd52.rw_flag = write;
/* Send CMD52 command */
sdio_sendcmdpoll(dev, SDIO_ACMD52, arg.value);
ret = SDIO_RECVR5(dev, SDIO_ACMD52, (uint32_t*)&resp);
if (ret != OK)
{
_err("ERROR: SDIO_RECVR5 failed %d\n", ret);
return ret;
}
/* Check for errors */
if (resp.flags.error)
{
return -EIO;
}
if (resp.flags.function_number || resp.flags.out_of_range)
{
return -EINVAL;
}
/* Write output byte */
if (outb)
{
*outb = resp.data & 0xff;
}
return OK;
}
// int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
// uint8_t function, uint32_t address,
// bool inc_addr, uint8_t *buf,
// unsigned int blocklen, unsigned int nblocks)
// {
// struct sdio_cmd53 arg;
// struct sdio_resp_R5 resp;
// int ret;
// sdio_eventset_t wkupevent;
//
// /* Setup CMD53 argument */
//
// arg.byte_block_count = blocklen;
// arg.register_address = address & 0x1ff;
// arg.op_code = inc_addr;
// arg.function_number = function & 7;
// arg.rw_flag = write;
//
// if (nblocks <= 1 && blocklen < 512)
// {
// /* Use byte mode */
//
// arg.block_mode = 0;
// nblocks = 1;
// }
// else
// {
// /* Use block mode */
//
// arg.block_mode = 1;
// }
//
// /* Send CMD53 command */
//
// SDIO_BLOCKSETUP(dev, blocklen, nblocks);
// SDIO_WAITENABLE(dev,
// SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR);
//
// sdio_sendcmdpoll(dev, SDIO_ACMD53, (uint32_t)arg);
// ret = SDIO_RECVR5(dev, SDIO_ACMD53, (uint32_t*)&resp);
//
// if (write)
// {
// sdio_sendcmdpoll(dev, SDIO_ACMD53, (uint32_t)arg);
// ret = SDIO_RECVR5(dev, SDIO_ACMD53, (uint32_t*)&resp);
//
// SDIO_SENDSETUP(dev, buf, blocklen * nblocks);
// wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
// }
// else
// {
// SDIO_RECVSETUP(dev, buf, blocklen * nblocks);
// SDIO_SENDCMD(dev, SDIO_ACMD53, (uint32_t)arg);
//
// wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
// ret = SDIO_RECVR5(dev, SDIO_ACMD53, (uint32_t*)&resp);
// }
//
// if (ret != OK)
// {
// _err("ERROR: SDIO_RECVR5 failed %d\n", ret);
// return ret;
// }
//
// /* Check for errors */
//
// if (wkupevent & SDIOWAIT_TIMEOUT)
// {
// return -ETIMEDOUT;
// }
// if (resp.error || (wkupevent & SDIOWAIT_ERROR))
// {
// return -EIO;
// }
// if (resp.function_number || resp.out_of_range)
// {
// return -EINVAL;
// }
//
// return OK;
// }
int sdio_set_wide_bus(struct sdio_dev_s *dev)
{
int ret;
uint8_t value;
/* Read Bus Interface Control register */
ret = sdio_io_rw_direct(dev, false, 0, SDIO_CCCR_BUS_IF, 0, &value);
if (ret != OK)
{
return ret;
}
/* Set 4 bits bus width setting */
value &= ~SDIO_CCCR_BUS_IF_WIDTH_MASK;
value |= SDIO_CCCR_BUS_IF_4_BITS;
ret = sdio_io_rw_direct(dev, true, 0, SDIO_CCCR_BUS_IF, value, NULL);
if (ret != OK)
{
return ret;
}
SDIO_WIDEBUS(dev, true);
return OK;
}
int sdio_probe(FAR struct sdio_dev_s *dev)
{
int ret;
uint32_t data = 0;
/* Set device state from reset to idle */
sdio_sendcmdpoll(dev, MMCSD_CMD0, 0);
up_mdelay(SDIO_IDLE_DELAY_MS);
/* Device is SDIO card compatible so we can send CMD5 instead of ACMD41 */
sdio_sendcmdpoll(dev, SDIO_CMD5, 0);
/* Receive R4 response */
ret = SDIO_RECVR4(dev, SDIO_CMD5, &data);
if (ret != OK)
{
return ret;
}
/* Device is in Card Identification Mode, request device RCA */
sdio_sendcmdpoll(dev, SD_CMD3, 0);
ret = SDIO_RECVR6(dev, SD_CMD3, &data);
if (ret != OK)
{
_err("ERROR: RCA request failed: %d\n", ret);
return ret;
}
_info("rca is %x\n", data >> 16);
/* Send CMD7 with the argument == RCA in order to select the card
* and put it in Transfer State */
sdio_sendcmdpoll(dev, MMCSD_CMD7S, data & 0xffff0000);
ret = SDIO_RECVR1(dev, MMCSD_CMD7S, &data);
if (ret != OK)
{
_err("ERROR: card selection failed: %d\n", ret);
return ret;
}
/* Configure 4 bits bus width */
ret = sdio_set_wide_bus(dev);
if (ret != OK)
{
return ret;
}
return OK;
}
int sdio_set_blocksize(FAR struct sdio_dev_s *dev, uint8_t function,
uint16_t blocksize)
{
int ret;
ret = sdio_io_rw_direct(dev, true, 0,
(function << SDIO_FBR_SHIFT) + SDIO_CCCR_FN0_BLKSIZE_0,
blocksize & 0xff, NULL);
if (ret != OK)
{
return ret;
}
ret = sdio_io_rw_direct(dev, true, 0,
(function << SDIO_FBR_SHIFT) + SDIO_CCCR_FN0_BLKSIZE_1,
(blocksize >> 8), NULL);
if (ret != OK)
{
return ret;
}
return OK;
}
int sdio_enable_function(FAR struct sdio_dev_s *dev, uint8_t function)
{
int ret;
uint8_t value;
/* Read current I/O Enable register */
ret = sdio_io_rw_direct(dev, false, 0, SDIO_CCCR_IOEN, 0, &value);
if (ret != OK)
{
return ret;
}
ret = sdio_io_rw_direct(dev, true, 0, SDIO_CCCR_IOEN, value | (1 << function), NULL);
if (ret != OK)
{
return ret;
}
/* Wait 10ms for function to be enabled */
int loops = 10;
while (loops-- > 0)
{
up_mdelay(1);
ret = sdio_io_rw_direct(dev, false, 0, SDIO_CCCR_IOEN, 0, &value);
if (ret != OK)
{
return ret;
}
if (value & (1 << function))
{
/* Function enabled */
_info("Function %d enabled\n", function);
return OK;
}
}
return -ETIMEDOUT;
}

38
include/nuttx/sdio.h
View File

@ -328,6 +328,44 @@
#define SDIO_ACMD52 (SDIO_ACMDIDX52|MMCSD_R5_RESPONSE |MMCSD_NODATAXFR)
#define SDIO_ACMD53 (SDIO_ACMDIDX53|MMCSD_R5_RESPONSE |MMCSD_NODATAXFR)
/* SDIO Card Common Control Registers definitions
* see https://www.sdcard.org/developers/overview/sdio/
* sdio_spec/Simplified_SDIO_Card_Spec.pdf */
#define SDIO_CCCR_REV 0x00 /* CCCR/SDIO Revision */
#define SDIO_CCCR_SD_SPEC_REV 0x01 /* SD Specification Revision */
#define SDIO_CCCR_IOEN 0x02 /* I/O Enable */
#define SDIO_CCCR_IORDY 0x03 /* I/O Ready */
#define SDIO_CCCR_INTEN 0x04 /* Int Enable */
#define SDIO_CCCR_INTPEND 0x05 /* Int Pending */
#define SDIO_CCCR_IOABORT 0x06 /* I/O Abort */
#define SDIO_CCCR_BUS_IF 0x07 /* Bus Interface Control */
#define SDIO_CCCR_CARD_CAP 0x08 /* Card Capabilitiy */
#define SDIO_CCCR_CCP 0x09 /* Common CIS Pointer */
#define SDIO_CCCR_BUS_SUSP 0x0C /* Bus Suspend */
#define SDIO_CCCR_FUNCSEL 0x0D /* Function Select */
#define SDIO_CCCR_EXEC_FLAGS 0x0E /* Exec Flags */
#define SDIO_CCCR_RDY_FLAGS 0x0F /* Ready Flags */
#define SDIO_CCCR_FN0_BLKSIZE_0 0x10 /* FN0 Block Size */
#define SDIO_CCCR_FN0_BLKSIZE_1 0x11 /* FN0 Block Size */
#define SDIO_CCCR_POWER 0x12 /* Power Control */
#define SDIO_CCCR_HIGHSPEED 0x13 /* High-Speed */
#define SDIO_CCCR_RFU 0x14 /* Reserved for future use */
#define SDIO_CCCR_VENDOR 0xF0 /* Reserved for Vendors */
#define SDIO_CCCR_BUS_IF_WIDTH_MASK 0x03 /* Bus width configuration */
#define SDIO_CCCR_BUS_IF_1_BIT 0x01 /* 1 bit bus width setting */
#define SDIO_CCCR_BUS_IF_4_BITS 0x02 /* 4 bits bus width setting */
#define SDIO_FBR_SHIFT 8 /* FBR bit shift */
#define SDIO_FN1_BR_BASE (1 << SDIO_FBR_SHIFT) /* Func 1 registers base */
#define SDIO_FN2_BR_BASE (2 << SDIO_FBR_SHIFT) /* Func 2 registers base */
#define SDIO_FN3_BR_BASE (3 << SDIO_FBR_SHIFT) /* Func 3 registers base */
#define SDIO_FN4_BR_BASE (4 << SDIO_FBR_SHIFT) /* Func 4 registers base */
#define SDIO_FN5_BR_BASE (5 << SDIO_FBR_SHIFT) /* Func 5 registers base */
#define SDIO_FN6_BR_BASE (6 << SDIO_FBR_SHIFT) /* Func 6 registers base */
#define SDIO_FN7_BR_BASE (7 << SDIO_FBR_SHIFT) /* Func 7 registers base */
/****************************************************************************
* Name: SDIO_LOCK
*

26
include/nuttx/wireless/ieee80211/mmc_sdio.h Normal file
View File

@ -0,0 +1,26 @@
#ifndef caca
#define caca
#include <stdint.h>
#include <nuttx/sdio.h>
int sdio_probe(FAR struct sdio_dev_s *dev);
int sdio_set_wide_bus(struct sdio_dev_s *dev);
int sdio_set_blocksize(FAR struct sdio_dev_s *dev, uint8_t function,
uint16_t blocksize);
int sdio_enable_function(FAR struct sdio_dev_s *dev, uint8_t function);
int sdio_sendcmdpoll(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg);
int sdio_io_rw_direct(FAR struct sdio_dev_s *dev, bool write,
uint8_t function, uint32_t address,
uint8_t inb, uint8_t* outb);
int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
uint8_t function, uint32_t address,
bool inc_addr, uint8_t *buf,
unsigned int blocklen, unsigned int nblocks);
#endif