STM32: Add more complication to STM32 Kconfig so the correct ADC and CAN options presented for the F401RE. There are still invalid peripheral options being presented
This commit is contained in:
Gregory Nutt
parent
27d3a4962a
commit
bfa9df89e2
@ -104,7 +104,7 @@
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/* (2) Comparators */
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# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -142,7 +142,7 @@
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/* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -180,7 +180,7 @@
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/* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -218,7 +218,7 @@
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/* (2) Comparators */
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# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -256,7 +256,7 @@
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/* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -294,7 +294,7 @@
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/* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -332,7 +332,7 @@
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# define STM32_NDAC 2 /* DAC 1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -367,7 +367,7 @@
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# define STM32_NDAC 2 /* DAC 1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -405,7 +405,7 @@
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# define STM32_NDAC 2 /* DAC 1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -441,13 +441,14 @@
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# define STM32_NDAC 2 /* DAC 1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 Low Density Family *************************************************/
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/* STM32F103C4 & STM32F103C6 */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103C4)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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@ -474,7 +475,7 @@
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NTHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -511,7 +512,7 @@
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NTHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -546,7 +547,7 @@
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NTHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -581,7 +582,7 @@
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NTHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -604,7 +605,7 @@
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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@ -620,7 +621,7 @@
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -658,7 +659,7 @@
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NTHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -680,7 +681,7 @@
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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@ -696,7 +697,7 @@
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No Ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -716,7 +717,7 @@
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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@ -750,7 +751,7 @@
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timers TIM1 */
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# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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@ -817,9 +818,9 @@
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# define CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
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@ -1660,7 +1661,6 @@
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#else
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# error "Unsupported STM32 chip"
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#endif
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@ -564,6 +564,10 @@ endchoice
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config STM32_STM32L15XX
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bool
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default n
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config STM32_ENERGYLITE
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bool
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default n
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select STM32_HAVE_USBDEV
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select STM32_HAVE_USART3
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select STM32_HAVE_TIM6
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@ -571,19 +575,7 @@ config STM32_STM32L15XX
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select STM32_HAVE_TIM9
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select STM32_HAVE_TIM10
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select STM32_HAVE_TIM11
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config STM32_ENERGYLITE
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bool
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default n
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select STM32_HAVE_USART3
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select STM32_HAVE_USART4
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select STM32_HAVE_USART5
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select STM32_HAVE_TIM1
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select STM32_HAVE_TIM5
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select STM32_HAVE_TIM6
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select STM32_HAVE_TIM7
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select STM32_HAVE_TIM8
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select STM32_HAVE_TIM10
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select STM32_HAVE_ADC2
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config STM32_STM32F10XX
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bool
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@ -605,6 +597,7 @@ config STM32_VALUELINE
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select STM32_HAVE_TIM15
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select STM32_HAVE_TIM16
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select STM32_HAVE_TIM17
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select STM32_HAVE_ADC2
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config STM32_CONNECTIVITYLINE
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bool
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@ -618,6 +611,9 @@ config STM32_CONNECTIVITYLINE
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select STM32_HAVE_TIM6
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select STM32_HAVE_TIM7
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select STM32_HAVE_TIM8
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select STM32_HAVE_ADC2
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select STM32_HAVE_CAN1
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select STM32_HAVE_CAN2
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config STM32_PERFORMANCELINE
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bool
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@ -631,6 +627,8 @@ config STM32_PERFORMANCELINE
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select STM32_HAVE_TIM6
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select STM32_HAVE_TIM7
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select STM32_HAVE_TIM8
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select STM32_HAVE_ADC2
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select STM32_HAVE_CAN1
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config STM32_HIGHDENSITY
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bool
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@ -644,6 +642,9 @@ config STM32_HIGHDENSITY
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select STM32_HAVE_TIM6
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select STM32_HAVE_TIM7
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select STM32_HAVE_TIM8
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_CAN1
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config STM32_MEDIUMDENSITY
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bool
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@ -656,6 +657,9 @@ config STM32_MEDIUMDENSITY
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select STM32_HAVE_TIM6
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select STM32_HAVE_TIM7
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select STM32_HAVE_TIM8
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_CAN1
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config STM32_LOWDENSITY
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bool
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@ -668,6 +672,8 @@ config STM32_LOWDENSITY
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select STM32_HAVE_TIM6
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select STM32_HAVE_TIM7
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select STM32_HAVE_TIM8
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select STM32_HAVE_ADC2
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select STM32_HAVE_CAN1 if !STM32_VALUELINE
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config STM32_STM32F20XX
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bool
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@ -690,6 +696,10 @@ config STM32_STM32F20XX
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select STM32_HAVE_TIM12
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select STM32_HAVE_TIM13
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select STM32_HAVE_TIM14
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_CAN1
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select STM32_HAVE_CAN2
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config STM32_STM32F30XX
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bool
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@ -703,6 +713,10 @@ config STM32_STM32F30XX
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select STM32_HAVE_TIM15
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select STM32_HAVE_TIM16
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select STM32_HAVE_TIM17
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_ADC4
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select STM32_HAVE_CAN1
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config STM32_STM32F40XX
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bool
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@ -739,6 +753,10 @@ config STM32_STM32F405
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select STM32_HAVE_TIM12
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select STM32_HAVE_TIM13
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select STM32_HAVE_TIM14
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_CAN1
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select STM32_HAVE_CAN2
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config STM32_STM32F407
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bool
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@ -760,6 +778,10 @@ config STM32_STM32F407
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select STM32_HAVE_TIM12
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select STM32_HAVE_TIM13
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select STM32_HAVE_TIM14
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_CAN1
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select STM32_HAVE_CAN2
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# This is really 427/437, but we treat the two the same.
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config STM32_STM32F427
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@ -784,6 +806,10 @@ config STM32_STM32F427
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select STM32_HAVE_TIM12
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select STM32_HAVE_TIM13
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select STM32_HAVE_TIM14
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_CAN1
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select STM32_HAVE_CAN2
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# This is really 429/439, but we treat the two the same.
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config STM32_STM32F429
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@ -807,6 +833,10 @@ config STM32_STM32F429
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select STM32_HAVE_TIM12
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select STM32_HAVE_TIM13
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select STM32_HAVE_TIM14
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select STM32_HAVE_ADC2
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select STM32_HAVE_ADC3
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select STM32_HAVE_CAN1
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select STM32_HAVE_CAN2
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config STM32_DFU
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bool "DFU bootloader"
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@ -917,6 +947,26 @@ config STM32_HAVE_TIM17
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bool
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default n
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config STM32_HAVE_ADC2
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bool
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default n
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config STM32_HAVE_ADC3
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bool
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default n
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config STM32_HAVE_ADC4
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bool
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default n
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config STM32_HAVE_CAN1
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bool
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default n
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config STM32_HAVE_CAN2
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bool
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default n
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# These are the peripheral selections proper
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config STM32_ADC1
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@ -928,19 +978,19 @@ config STM32_ADC2
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bool "ADC2"
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default n
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select STM32_ADC
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depends on !STM32_VALUELINE
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depends on STM32_HAVE_ADC2
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config STM32_ADC3
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bool "ADC3"
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default n
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select STM32_ADC
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depends on !STM32_VALUELINE
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depends on STM32_HAVE_ADC3
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config STM32_ADC4
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bool "ADC4"
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default n
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select STM32_ADC
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depends on STM32_STM32F30XX
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depends on STM32_HAVE_ADC4
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||||
|
||||
config STM32_COMP
|
||||
bool "COMP"
|
||||
@ -962,14 +1012,14 @@ config STM32_CAN1
|
||||
default n
|
||||
select CAN
|
||||
select STM32_CAN
|
||||
depends on !STM32_VALUELINE && !STM32_STM32L15XX
|
||||
depends on STM32_HAVE_CAN1
|
||||
|
||||
config STM32_CAN2
|
||||
bool "CAN2"
|
||||
default n
|
||||
depends on STM32_STM32F20XX || STM32_STM32F40XX
|
||||
select CAN
|
||||
select STM32_CAN
|
||||
depends on STM32_HAVE_CAN2
|
||||
|
||||
config STM32_CCMDATARAM
|
||||
bool "CMD/DATA RAM"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user