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arch/arm: Fix nxstyle warning

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2021-04-06 13:49:35 +08:00 committed by Masayuki Ishikawa
parent eeb8931c04
commit bfbe705e3f
2 changed files with 16 additions and 14 deletions
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10
arch/arm/src/arm/arm_schedulesigaction.c
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@ -122,16 +122,16 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* the signals have been delivered. * the signals have been delivered.
*/ */
tcb->xcp.sigdeliver = sigdeliver; tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pc = CURRENT_REGS[REG_PC]; tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR]; tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
/* Then set up to vector to the trampoline with interrupts /* Then set up to vector to the trampoline with interrupts
* disabled * disabled
*/ */
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver; CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT; CURRENT_REGS[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
/* And make sure that the saved context in the TCB /* And make sure that the saved context in the TCB
* is the same as the interrupt return context. * is the same as the interrupt return context.

20
arch/arm/src/moxart/moxart_irq.c
View File

@ -114,23 +114,23 @@ void up_irqinitialize(void)
(*(volatile uint32_t *)0x98100008) |= 0x4; (*(volatile uint32_t *)0x98100008) |= 0x4;
(*(volatile uint32_t *)0x98800100) = 0xDFF8003F; (*(volatile uint32_t *)0x98800100) = 0xdff8003f;
/* Check board type */ /* Check board type */
/* Mask all interrupts off */ /* Mask all interrupts off */
putreg32(0, IRQ_REG(IRQ__MASK)); putreg32(0, IRQ_REG(IRQ__MASK));
putreg32(0, IRQ_REG(IRQ__MASK+0x20)); putreg32(0, IRQ_REG(IRQ__MASK + 0x20));
putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR)); putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR));
putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR+0x20)); putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR + 0x20));
/* Initial trigger mode and level */ /* Initial trigger mode and level */
putreg32(0, IRQ_REG(IRQ__MODE)); putreg32(0, IRQ_REG(IRQ__MODE));
putreg32(0, IRQ_REG(IRQ__LEVEL)); putreg32(0, IRQ_REG(IRQ__LEVEL));
putreg32(0, IRQ_REG(IRQ__MODE+0x20)); putreg32(0, IRQ_REG(IRQ__MODE + 0x20));
putreg32(0, IRQ_REG(IRQ__LEVEL+0x20)); putreg32(0, IRQ_REG(IRQ__LEVEL + 0x20));
/* currents_regs is non-NULL only while processing an interrupt */ /* currents_regs is non-NULL only while processing an interrupt */
@ -147,10 +147,10 @@ void up_irqinitialize(void)
getreg32(0x98400030), getreg32(0x98400034), getreg32(0x98400038), getreg32(0x98400030), getreg32(0x98400034), getreg32(0x98400038),
getreg32(0x98400004), getreg32(0x98400000), getreg32(0x98400008)); getreg32(0x98400004), getreg32(0x98400000), getreg32(0x98400008));
irqinfo("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", irqinfo("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
getreg32(0x98800014), getreg32(0x98800004), getreg32(0x9880000C), getreg32(0x98800014), getreg32(0x98800004), getreg32(0x9880000c),
getreg32(0x98800010)); getreg32(0x98800010));
irqinfo("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", irqinfo("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
getreg32(0x98800034), getreg32(0x98800024), getreg32(0x9880002C), getreg32(0x98800034), getreg32(0x98800024), getreg32(0x9880002c),
getreg32(0x98800020)); getreg32(0x98800020));
#ifndef CONFIG_SUPPRESS_INTERRUPTS #ifndef CONFIG_SUPPRESS_INTERRUPTS
@ -262,7 +262,8 @@ void up_enable_irq(int irq)
static int ffs(uint32_t word) static int ffs(uint32_t word)
{ {
int t, r; int t;
int r;
if (word == 0) if (word == 0)
{ {
@ -299,7 +300,8 @@ void arm_ack_irq(int irq)
uint32_t *arm_decodeirq(uint32_t *regs) uint32_t *arm_decodeirq(uint32_t *regs)
{ {
uint32_t num, status; uint32_t num;
uint32_t status;
/* Detect & deliver the IRQ */ /* Detect & deliver the IRQ */