From bff341fdfcbaed6cf884647ead12b5a7d8d8b867 Mon Sep 17 00:00:00 2001 From: Juha Niskanen Date: Wed, 5 Apr 2017 07:15:19 -0600 Subject: [PATCH] stm32: stm32l15xx_rcc: add support for using MSI as system clock --- arch/arm/src/stm32/stm32l15xxx_rcc.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/stm32/stm32l15xxx_rcc.c b/arch/arm/src/stm32/stm32l15xxx_rcc.c index 51a163d99a..fce96fa6e6 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rcc.c +++ b/arch/arm/src/stm32/stm32l15xxx_rcc.c @@ -579,12 +579,11 @@ static void stm32_stdclockconfig(void) #endif - /* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. - * NOTE that only PLL, HSE, or HSI are supported for the system clock - * in this implementation - */ + /* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */ + +#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \ + ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)) -#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) /* The PLL is using the HSE, or the HSE is the system clock. In either * case, we need to enable HSE clocking. */ @@ -599,7 +598,9 @@ static void stm32_stdclockconfig(void) return; } -#elif (STM32_CFGR_PLLSRC == 0) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) +#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \ + ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0) + /* The PLL is using the HSI, or the HSI is the system clock. In either * case, we need to enable HSI clocking. */ @@ -616,6 +617,8 @@ static void stm32_stdclockconfig(void) #endif +#if (STM32_SYSCLK_SW != RCC_CFGR_SW_MSI) + /* Increasing the CPU frequency (in the same voltage range): * * After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the @@ -651,6 +654,8 @@ static void stm32_stdclockconfig(void) regval |= FLASH_ACR_PRFTEN; putreg32(regval, STM32_FLASH_ACR); +#endif /* STM32_SYSCLK_SW != RCC_CFGR_SW_MSI */ + /* Set the HCLK source/divider */ regval = getreg32(STM32_RCC_CFGR);