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Added STM32_HAVE_OVERDRIVE option, and made core over-drive to be enabled only when system frequency is > 168MHz.

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This commit is contained in:
Fotis Panagiotopoulos 2020-08-11 12:41:36 +03:00 committed by David Sidrane
parent 0585a8b327
commit c046e56b3b
4 changed files with 24 additions and 17 deletions
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8
arch/arm/src/stm32/Kconfig
View File

@ -1713,6 +1713,7 @@ config STM32_STM32F407
config STM32_STM32F427
bool
default n
select STM32_HAVE_OVERDRIVE
select STM32_HAVE_FMC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
@ -1756,6 +1757,7 @@ config STM32_STM32F427
config STM32_STM32F429
bool
default n
select STM32_HAVE_OVERDRIVE
select STM32_HAVE_FMC
select STM32_HAVE_LTDC
select STM32_HAVE_CCM
@ -1798,6 +1800,7 @@ config STM32_STM32F429
config STM32_STM32F446
bool
default n
select STM32_HAVE_OVERDRIVE
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
@ -1834,6 +1837,7 @@ config STM32_STM32F446
config STM32_STM32F469
bool
default n
select STM32_HAVE_OVERDRIVE
select STM32_HAVE_FMC
select STM32_HAVE_LTDC
select STM32_HAVE_CCM
@ -1988,6 +1992,10 @@ menu "STM32 Peripheral Support"
# These "hidden" settings determine whether a peripheral option is available
# for the selected MCU
config STM32_HAVE_OVERDRIVE
bool
default n
config STM32_HAVE_AES
bool
default n

14
arch/arm/src/stm32/stm32_pwr.c
View File

@ -351,10 +351,10 @@ bool stm32_pwr_getwuf(void)
* Description:
* Enables the Backup regulator, the Backup regulator (used to maintain backup
* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
* regulator is switched off. The backup SRAM can still be used but its content will
* be lost in the Standby and VBAT modes. Once set, the application must wait that
* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
* into the RAM will be maintained in the Standby and VBAT modes.
* regulator is switched off. The backup SRAM can still be used but its content
* will be lost in the Standby and VBAT modes. Once set, the application must wait
* that the Backup Regulator Ready flag (BRR) is set to indicate that the data
* written into the RAM will be maintained in the Standby and VBAT modes.
*
* Input Parameters:
* region - state to set it to
@ -498,11 +498,9 @@ void stm32_pwr_disablepvd(void)
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
#if defined(CONFIG_STM32_HAVE_OVERDRIVE)
void stm32_pwr_enableoverdrive(bool state)
{
/* Switch overdrive state */
if (state)
@ -518,7 +516,7 @@ void stm32_pwr_enableoverdrive(bool state)
while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_ODRDY) == 0);
/* Set ODSWEN to switch to this new state*/
/* Set ODSWEN to switch to this new state */
stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, PWR_CR_ODSWEN);

13
arch/arm/src/stm32/stm32_pwr.h
View File

@ -79,7 +79,7 @@ enum stm32_pwr_wupin_e
};
/************************************************************************************
* Public Functions
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
@ -187,10 +187,10 @@ bool stm32_pwr_getwuf(void);
* Description:
* Enables the Backup regulator, the Backup regulator (used to maintain backup
* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
* regulator is switched off. The backup SRAM can still be used but its content will
* be lost in the Standby and VBAT modes. Once set, the application must wait that
* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
* into the RAM will be maintained in the Standby and VBAT modes.
* regulator is switched off. The backup SRAM can still be used but its content
* will be lost in the Standby and VBAT modes. Once set, the application must wait
* that the Backup Regulator Ready flag (BRR) is set to indicate that the data
* written into the RAM will be maintained in the Standby and VBAT modes.
*
* Input Parameters:
* region - state to set it to
@ -278,8 +278,7 @@ void stm32_pwr_disablepvd(void);
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
#if defined(CONFIG_STM32_HAVE_OVERDRIVE)
void stm32_pwr_enableoverdrive(bool state);
#endif

6
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -41,6 +41,9 @@
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip.h"
#include "stm32_pwr.h"
#include "itm_syslog.h"
@ -755,8 +758,7 @@ static void stm32_stdclockconfig(void)
{
}
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \
defined(CONFIG_STM32_STM32F469)
#if defined(CONFIG_STM32_HAVE_OVERDRIVE) && (STM32_SYSCLK_FREQUENCY > 168000000)
/* Enable the Over-drive to extend the clock frequency to 180 MHz */