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Make sure that every reference to LM4F has corresponding logic for TM4C

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This commit is contained in:
Gregory Nutt 2014-03-10 11:23:50 -06:00
parent 51674e0c51
commit c05ad5ef63
4 changed files with 17 additions and 11 deletions
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2
arch/arm/src/tiva/Kconfig
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@ -48,7 +48,7 @@ config ARCH_CHIP_LM4F120
select ARCH_CHIP_LM4F
select ARCH_HAVE_FPU
config CONFIG_ARCH_CHIP_TM4C123GH6ZRB
config ARCH_CHIP_TM4C123GH6ZRB
bool "TM4C123GH6ZRB"
depends on ARCH_CHIP_TIVA
select ARCH_CORTEXM4

4
arch/arm/src/tiva/tiva_gpio.c
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@ -348,7 +348,7 @@ static void tiva_gpiofunc(uint32_t base, uint32_t pinno,
* isolation circuitry for the corresponding GPIO signal.
*/
#ifdef LM4F
#if defined(LM4F) || defined(TM4C)
setbit = (((uint32_t)func->setbits >> AMSEL_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> AMSEL_SHIFT) & 1) << pinno;
@ -754,7 +754,7 @@ static inline void tiva_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
*
****************************************************************************/
#ifdef LM4F
#if defined(LM4F) || defined(TM4C)
static inline void tiva_portcontrol(uint32_t base, uint32_t pinno,
uint32_t cfgset,
const struct gpio_func_s *func)

14
arch/arm/src/tiva/tiva_gpio.h
View File

@ -59,12 +59,14 @@
*
* LM3S: FFFS SPPP III. .... .... .... VPPP PBBB
* LM4F: FFFS SPPP III. AAAA .... .... VPPP PBBB
* TM4C: FFFS SPPP III. AAAA .... .... VPPP PBBB
*
* TODO: The LM4F also supports configuration of pins to trigger ADC and/or uDMA.
* That configuratin is not addressed in this this encoding.
* TODO: The LM4F/TM4C also support configuration of pins to trigger ADC and/or uDMA.
* That configuration is not addressed in this this encoding.
*/
/* These bits set the primary function of the pin:
*
* FFFn .... .... .... .... .... .... ....
*/
@ -84,6 +86,7 @@
# define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT
/* That primary may be modified by the following options
*
* ...S SPPP .... .... .... .... .... ....
*/
@ -106,6 +109,7 @@
# define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
/* If the pin is an interrupt, then the following options apply
*
* .... .... III. .... .... .... .... ....
*/
@ -117,11 +121,13 @@
# define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
# define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
/* The LM4F120 supports up to 15 alternate functions per pin:
/* The LM4F/TM4C supports up to 15 alternate functions per pin:
*
* LM4F: .... .... .... AAAA .... .... .... ....
* TM4C: .... .... .... AAAA .... .... .... ....
*/
#ifdef LM4F
#if defined(LM4F) || defined(TM4C)
# define GPIO_ALT_SHIFT 16 /* Bits 16-19: Alternate function */
# define GPIO_ALT_MASK (15 << GPIO_ALT_SHIFT)
# define GPIO_ALT(n) ((n) << GPIO_ALT_SHIFT)

8
arch/arm/src/tiva/tiva_syscontrol.c
View File

@ -55,7 +55,7 @@
* Pre-processor Definitions
****************************************************************************/
#ifdef LM4F
#if defined(LM4F) || defined(TM4C)
# define RCC_OSCMASK (SYSCON_RCC_MOSCDIS)
# define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK | SYSCON_RCC_OSCSRC_MASK | \
SYSCON_RCC_PWRDN)
@ -223,7 +223,7 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
* on rest and if that is selected, most likely nothing needs to be done.
*/
#ifdef LM4F
#if defined(LM4F) || defined(TM4C)
if ((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS))
#else
if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) ||
@ -266,7 +266,7 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
* before writing the RCC2 register.
*/
#ifndef LM4F
#if defined(LM4F) || defined(TM4C)
if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
{
putreg32(rcc2, TIVA_SYSCON_RCC2);
@ -314,7 +314,7 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
*/
putreg32(rcc, TIVA_SYSCON_RCC);
#ifdef LM4F
#if defined(LM4F) || defined(TM4C)
rcc = getreg32(TIVA_SYSCON_RCC);
#endif
putreg32(rcc2, TIVA_SYSCON_RCC2);