i.MX6: Add basic memory map tables
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@ -113,7 +113,7 @@
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#define IMX_SATA_PSECTION 0x02200000 /* 02200000-0220bfff 48 KB SATA */
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/* 0220c000-023fffff 2 MB Reserved */
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#define IMX_IPU1_PSECTION 0x02600000 /* 02600000-029fffff 4 MB IPU-1 */
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#define IMX_IPU2MIPIHSI_PSECTION 0x02a00000 /* 02a00000-02dfffff 4 MB IPU-2 */
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#define IMX_IPU2_PSECTION 0x02a00000 /* 02a00000-02dfffff 4 MB IPU-2 */
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#define IMX_EIM_PSECTION 0x08000000 /* 08000000-0fffffff 128 MB EIM - (NOR/SRAM) */
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#define IMX_MMDCDDR_PSECTION 0x10000000 /* 10000000-ffffffff 3840 MB MMDC-DDR Controller */
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/* 10000000-7fffffff 1792 MB */
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@ -461,7 +461,7 @@
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#define IMX_SATA_SIZE (48*1024) /* 02200000-0220bfff 48 KB SATA */
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/* 0220c000-023fffff 2 MB Reserved */
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#define IMX_IPU1_SIZE (4*1024*1024) /* 02600000-029fffff 4 MB IPU-1 */
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#define IMX_IPU2MIPIHSI_SIZE (4*1024*1024) /* 02a00000-02dfffff 4 MB IPU-2 */
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#define IMX_IPU2_SIZE (4*1024*1024) /* 02a00000-02dfffff 4 MB IPU-2 */
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#define IMX_EIM_SIZE MKULONG(CONFIG_IMX_EIM_SIZE) /* 08000000-0fffffff 128 MB EIM - (NOR/SRAM) */
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#define IMX_MMDCDDR_SIZE MKULONG(CONFIG_IMX_DDR_SIZE /* 10000000-ffffffff 3840 MB MMDC-DDR Controller */
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/* 10000000-7fffffff 1792 MB */
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@ -492,7 +492,7 @@
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#define IMX_AIPS2_NSECTIONS _NSECTIONS(IMX_AIPS2_SIZE
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#define IMX_SATA_NSECTIONS _NSECTIONS(IMX_SATA_SIZE
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#define IMX_IPU1_NSECTIONS _NSECTIONS(IMX_IPU1_SIZE
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#define IMX_IPU2MIPIHSI_NSECTIONS _NSECTIONS(IMX_IPU2MIPIHSI_SIZE
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#define IMX_IPU2_NSECTIONS _NSECTIONS(IMX_IPU2_SIZE
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#define IMX_EIM_NSECTIONS _NSECTIONS(IMX_EIM_SIZE
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#define IMX_MMDCDDR_NSECTIONS _NSECTIONS(IMX_MMDCDDR_SIZE
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@ -516,7 +516,7 @@
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#define IMX_AIPS2_MMUFLAGS MMU_IOFLAGS
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#define IMX_SATA_MMUFLAGS MMU_IOFLAGS
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#define IMX_IPU1_MMUFLAGS MMU_IOFLAGS
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#define IMX_IPU2MIPIHSI_MMUFLAGS MMU_IOFLAGS
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#define IMX_IPU2_MMUFLAGS MMU_IOFLAGS
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#define IMX_EIM_MMUFLAGS MMU_ROMFLAGS
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#define IMX_MMDCDDR_MMUFLAGS MMU_MEMFLAGS
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@ -553,7 +553,7 @@
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#define IMX_AIPS2_VSECTION IMX_AIPS2_PSECTION /* 1 MB Peripheral IPs via AIPS-2 */
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#define IMX_SATA_VSECTION IMX_SATA_PSECTION /* 48 KB SATA */
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#define IMX_IPU1_VSECTION IMX_IPU1_PSECTION /* 4 MB IPU-1 */
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#define IMX_IPU2MIPIHSI_VSECTION IMX_IPU2MIPIHSI_PSECTION /* 4 MB IPU-2 */
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#define IMX_IPU2_VSECTION IMX_IPU2_PSECTION /* 4 MB IPU-2 */
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#define IMX_EIM_VSECTION IMX_EIM_PSECTION /* 128 MB EIM - (NOR/SRAM) */
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#define IMX_MMDCDDR_VSECTION IMX_MMDCDDR_PSECTION /* 3840 MB MMDC-DDR Controller */
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@ -743,7 +743,7 @@
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#else /* CONFIG_BOOT_RUNFROMFLASH */
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/* Otherwise we are running from some kind of RAM (SRAM or SDRAM).
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/* Otherwise we are running from some kind of RAM (OCRAM, SRAM, or SDRAM).
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* Setup the RAM region as the NUTTX .txt, .bss, and .data region.
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*/
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@ -787,83 +787,39 @@
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# error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined"
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# endif
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/* We must declare the page table at the bottom or at the top of SRAM or
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* DRAM. First, do we have IEM SRAM?
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/* We must declare the page table at the bottom or at the top of OCRAM. */
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/* Yes.. do the vectors lie in low memory? */
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# ifdef CONFIG_ARCH_LOWVECTORS
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/* In this case, page table must lie at the top 16Kb of OCRAM. */
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# define PGTABLE_BASE_PADDR (IMX_OCRAM_PADDR - PGTABLE_SIZE)
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# define PGTABLE_BASE_VADDR (IMX_OCRAM_VADDR - PGTABLE_SIZE)
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# define PGTABLE_IN_HIGHSRAM 1
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/* We will force the IDLE stack to precede the page table */
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# define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR - CONFIG_IDLETHREAD_STACKSIZE)
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# define IDLE_STACK_VBASE (PGTABLE_BASE_VADDR - CONFIG_IDLETHREAD_STACKSIZE)
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# else /* CONFIG_ARCH_LOWVECTORS */
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/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH,
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* perhaps elsewhere in OCRAM). The page table will then be positioned
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* at the first 16Kb of SRAM.
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*/
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# if defined(CONFIG_IMX_BOOT_SRAM)
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# define PGTABLE_BASE_PADDR IMX_OCRAM_PADDR
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# define PGTABLE_BASE_VADDR IMX_OCRAM_VADDR
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# define PGTABLE_IN_LOWSRAM 1
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/* Yes.. do the vectors lie in low memory? */
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/* We will force the IDLE stack to follow the page table */
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# ifdef (CONFIG_ARCH_LOWVECTORS)
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# define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR + PGTABLE_SIZE)
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# define IDLE_STACK_VBASE (PGTABLE_BASE_VADDR + PGTABLE_SIZE)
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/* In this case, page table must lie at the top 16Kb IEM SRAM.
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*
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* If CONFIG_PAGING is defined, then mmu.h assign the virtual address
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* of the page table.
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*/
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# define PGTABLE_BASE_PADDR (IMX_EIM_SRAM_PADDR-PGTABLE_SIZE)
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# define PGTABLE_BASE_VADDR (IMX_EIM_SRAM_VADDR-PGTABLE_SIZE)
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# define PGTABLE_IN_HIGHSRAM 1
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/* We will always force the IDLE stack to follow the page table */
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# define IDLE_STACK_PBASE (IMX_EIM_SRAM_PADDR + 0x0001000)
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# define IDLE_STACK_VBASE (IMX_EIM_SRAM_VADDR + 0x0001000)
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# else /* CONFIG_ARCH_LOWVECTORS */
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/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps
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* elsewhere in internal SRAM). The page table will then be positioned at
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* the first 16Kb of SRAM.
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*/
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# define PGTABLE_BASE_PADDR IMX_EIM_SRAM_PADDR
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# define PGTABLE_BASE_VADDR IMX_EIM_SRAM_VADDR
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# define PGTABLE_IN_LOWSRAM 1
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/* We will always force the IDLE stack to follow the page table */
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# define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR + PGTABLE_SIZE)
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# define IDLE_STACK_VBASE (PGTABLE_BASE_VADDR + PGTABLE_SIZE)
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# endif /* CONFIG_ARCH_LOWVECTORS */
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/* No SRAM? Then we must have DRAM. */
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# else /* Must be CONFIG_IMX_BOOT_DRAM */
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# ifdef (CONFIG_ARCH_LOWVECTORS)
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/* In this case, page table must lie at the top 16Kb DRAM.
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*
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* If CONFIG_PAGING is defined, then mmu.h assign the virtual address
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* of the page table.
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*/
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# define PGTABLE_BASE_PADDR (IMX_MMDC_DRAM_PADDR-PGTABLE_SIZE)
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# define PGTABLE_BASE_VADDR (IMX_MMDC_DRAM_VADDR-PGTABLE_SIZE)
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# define PGTABLE_IN_HIGHSRAM 1
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# define IDLE_STACK_PBASE (IMX_MMDC_DRAM_PADDR + 0x0001000)
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# define IDLE_STACK_VBASE (IMX_MMDC_DRAM_VADDR + 0x0001000)
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# else /* CONFIG_ARCH_LOWVECTORS */
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/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps
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* elsewhere in internal SRAM). The page table will then be positioned at
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* the first 16Kb of SRAM.
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*/
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# define PGTABLE_BASE_PADDR IMX_MMDC_DRAM_PADDR
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# define PGTABLE_BASE_VADDR IMX_MMDC_DRAM_VADDR
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# define PGTABLE_IN_LOWSRAM 1
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# define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR + PGTABLE_SIZE)
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# define IDLE_STACK_VBASE (PGTABLE_BASE_VADDR + PGTABLE_SIZE)
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# endif /* CONFIG_ARCH_LOWVECTORS */
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# endif /* CONFIG_IMX_BOOT_SRAM/DRAM */
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# endif /* CONFIG_ARCH_LOWVECTORS */
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#else /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */
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/* Sanity check.. if one is defined, both should be defined */
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@ -872,19 +828,18 @@
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# error "One of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is undefined"
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# endif
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/* The page table then lies at the beginning of the boot RAM and
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/* The page table then lies at the beginning of the OSSRAM and
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* the IDLE stack follows immediately.
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*/
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# if defined(CONFIG_IMX_BOOT_SRAM)
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# define PGTABLE_BASE_PADDR IMX_OCRAM_PADDR
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# define PGTABLE_BASE_VADDR IMX_OCRAM_VADDR
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# define PGTABLE_IN_LOWSRAM 1
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# define IDLE_STACK_PBASE (IMX_EIM_SRAM_PADDR + PGTABLE_SIZE)
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# define IDLE_STACK_VBASE (IMX_EIM_SRAM_VADDR + PGTABLE_SIZE)
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/* We will force the IDLE stack to follow the page table */
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#else /* Must be CONFIG_IMX_BOOT_DRAM */
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# define IDLE_STACK_PBASE (IMX_MMDC_DRAM_PADDR + PGTABLE_SIZE)
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# define IDLE_STACK_VBASE (IMX_MMDC_DRAM_VADDR + PGTABLE_SIZE)
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# define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR + PGTABLE_SIZE)
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# define IDLE_STACK_VBASE (PGTABLE_BASE_VADDR + PGTABLE_SIZE)
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#endif /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */
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@ -972,8 +927,8 @@
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#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
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# ifdef CONFIG_IMX_BOOT_SRAM
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# define IMX_VECTOR_PADDR IMX_EIM_SRAM_PADDR
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# define IMX_VECTOR_VSRAM IMX_EIM_SRAM_VADDR
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# define IMX_VECTOR_PADDR IMX_OCRAM_PADDR
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# define IMX_VECTOR_VSRAM IMX_OCRAM_VADDR
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# else /* Must be CONFIG_IMX_BOOT_DRAM */
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# define IMX_VECTOR_PADDR IMX_MMDC_DRAM_PADDR
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# define IMX_VECTOR_VSRAM IMX_MMDC_DRAM_VADDR
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@ -983,8 +938,8 @@
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#else /* Vectors located at 0xffff:0000 -- this probably does not work */
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# ifdef CONFIG_IMX_BOOT_SRAM
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# define IMX_VECTOR_PADDR (IMX_EIM_SRAM_PADDR+IMX_EIM_SRAM_SIZE-VECTOR_TABLE_SIZE)
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# define IMX_VECTOR_VSRAM (IMX_EIM_SRAM_VADDR+IMX_EIM_SRAM_SIZE-VECTOR_TABLE_SIZE)
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# define IMX_VECTOR_PADDR (IMX_OCRAM_PADDR+IMX_EIM_SRAM_SIZE-VECTOR_TABLE_SIZE)
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# define IMX_VECTOR_VSRAM (IMX_OCRAM_VADDR+IMX_EIM_SRAM_SIZE-VECTOR_TABLE_SIZE)
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# else /* Must be CONFIG_IMX_BOOT_DRAM */
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# define IMX_VECTOR_PADDR (IMX_MMDC_DRAM_PADDR+IMX_MMDC_DRAM_SIZE-VECTOR_TABLE_SIZE)
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# define IMX_VECTOR_VSRAM (IMX_MMDC_DRAM_VADDR+IMX_MMDC_DRAM_SIZE-VECTOR_TABLE_SIZE)
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arch/arm/src/imx6/imx_memorymap.c
Normal file
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arch/arm/src/imx6/imx_memorymap.c
Normal file
@ -0,0 +1,224 @@
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/****************************************************************************
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* arch/arm/src/imx6/imx_memorymap.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "mmu.h"
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#include "chip/imx_memorymap.h"
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#include "imx_lcd.h"
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#include "imx_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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/* This table describes how to map a set of 1Mb pages to space the physical
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* address space of the i.MX6.
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*/
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const struct section_mapping_s g_section_mapping[] =
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{
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/* i.MX6 Address Sections Memories */
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are two ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* This is the method used by this logic.
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*
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* The system always boots from the ROM memory at address 0x0. After
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* reset, and until the Remap command is performed, the OCRAM is accessible
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* at address 0x0090 0000.
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*
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* If we are executing from external SDRAM, then a secondary bootloader must
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* have loaded us into SDRAM. In this case, simply set the VBAR register
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* to the address of the vector table (not necessary at the beginning
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* or SDRAM).
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*/
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{ IMX_ROMCP_PSECTION, IMX_ROMCP_VSECTION, /* Boot ROM (ROMCP) */
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IMX_ROMCP_MMUFLAGS, IMX_ROMCP_NSECTIONS
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},
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{ IMX_DMA_PSECTION, IMX_DMA_VSECTION, /* "DMA" sectinon peripherals */
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IMX_DMA_MMUFLAGS, IMX_DMA_NSECTIONS
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},
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{ IMX_GPV2_PSECTION, IMX_GPV2_VSECTION, /* GPV_2 PL301 (per1) configuration port */
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IMX_GPV2_MMUFLAGS, IMX_GPV2_NSECTIONS
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},
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{ IMX_GPV3_PSECTION, IMX_GPV3_VSECTION, /* GPV_3 PL301 (per2) configuration port */
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IMX_GPV3_MMUFLAGS, IMX_GPV3_NSECTIONS
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},
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{ IMX_GPV4_PSECTION, IMX_GPV4_VSECTION, /* GPV_4 PL301 (fast3) configuration port */
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IMX_GPV4_MMUFLAGS, IMX_GPV4_NSECTIONS
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},
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{ IMX_OCRAM_PSECTION, IMX_OCRAM_VSECTION, /* OCRAM */
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IMX_OCRAM_MMUFLAGS, IMX_OCRAM_NSECTIONS
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},
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{ IMX_ARMMP_PSECTION, IMX_ARMMP_VSECTION, /* ARM MP */
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IMX_ARMMP_MMUFLAGS, IMX_ARMMP_NSECTIONS
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},
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{ IMX_GPV0PL301_PSECTION, IMX_GPV0PL301_VSECTION, /* GPV0 PL301 (fast2) configuration port */
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IMX_GPV0PL301_MMUFLAGS, IMX_GPV0PL301_NSECTIONS
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},
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{ IMX_GPV1PL301_PSECTION, IMX_GPV1PL301_VSECTION, /* GPV1 PL301 (fast1) configuration port */
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IMX_GPV1PL301_MMUFLAGS, IMX_GPV1PL301_NSECTIONS
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},
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{ IMX_PCIE_PSECTION, IMX_PCIE_VSECTION, /* PCIe */
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IMX_PCIE_MMUFLAGS, IMX_PCIE_NSECTIONS
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},
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{ IMX_AIPS1_PSECTION, IMX_AIPS1_VSECTION, /* Peripheral IPs via AIPS-1 */
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IMX_AIPS1_MMUFLAGS, IMX_AIPS1_NSECTIONS
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},
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{ IMX_AIPS2_PSECTION, IMX_AIPS2_VSECTION, /* Peripheral IPs via AIPS-2 */
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IMX_AIPS2_MMUFLAGS, IMX_AIPS2_NSECTIONS
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},
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{ IMX_SATA_PSECTION, IMX_SATA_VSECTION, /* SATA */
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IMX_SATA_MMUFLAGS, IMX_SATA_NSECTIONS
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},
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{ IMX_IPU1_PSECTION, IMX_IPU1_VSECTION, /* IPU-1 */
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IMX_IPU1_MMUFLAGS, IMX_IPU1_NSECTIONS
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},
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{ IMX_IPU2_PSECTION, IMX_IPU2_VSECTION, /* IPU-2 */
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IMX_IPU2_MMUFLAGS, IMX_IPU2_NSECTIONS
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},
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#ifdef CONFIG_IMX6_EIM
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{ IMX_EIM_PSECTION, IMX_EIM_VSECTION, /* EIM - (NOR/SRAM) */
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IMX_EIM_MMUFLAGS, IMX_EIM_NSECTIONS
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},
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#endif
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/* i.MX6 External SDRAM Memory. The SDRAM is not usable until it has been
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* initialized. If we are running out of SDRAM now, we can assume that some
|
||||
* second level boot loader has properly configured SRAM for us. In that
|
||||
* case, we set the MMU flags for the final, fully cache-able state.
|
||||
*
|
||||
* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
|
||||
* need not be repeated here.
|
||||
*
|
||||
* If we are running from OCRAM or NOR flash, then we will need to configure
|
||||
* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
|
||||
* ordered, non-cacheable state. We need this direct access to SDRAM in
|
||||
* order to configure it. Once SDRAM has been initialized, it will be re-
|
||||
* configured in its final state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_MAPPING
|
||||
{ IMX_MMDCDDR_PSECTION, IMX_MMDCDDR_VSECTION, /* MMDC-DDR Controller */
|
||||
MMU_STRONGLY_ORDERED, IMX_MMDCDDR_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*
|
||||
* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
|
||||
* until after the SDRAM remapping (since the framebuffer problem resides) in
|
||||
* SDRAM.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_IMX6_LCDC) && !defined(NEED_SDRAM_REMAPPING)
|
||||
{ CONFIG_IMX6_LCDC_FB_PBASE, CONFIG_IMX6_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, IMX6_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the mapping table */
|
||||
|
||||
#define NMAPPINGS \
|
||||
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_mappings = NMAPPINGS;
|
||||
|
||||
#endif /* CONFIG_ARCH_ROMPGTABLE */
|
||||
|
||||
/* i.MX6 External SDRAM Memory. Final configuration. The SDRAM was
|
||||
* configured in a temporary state to support low-level ininitialization.
|
||||
* After the SDRAM has been fully initialized, this structure is used to
|
||||
* set the SDRM in its final, fully cache-able state.
|
||||
*/
|
||||
|
||||
#ifdef NEED_SDRAM_REMAPPING
|
||||
const struct section_mapping_s g_operational_mapping[] =
|
||||
{
|
||||
/* This entry reprograms the SDRAM entry, making it cacheable and
|
||||
* bufferable.
|
||||
*/
|
||||
|
||||
{ IMX_MMDCDDR_PSECTION, IMX_MMDCDDR_VSECTION, /* MMDC-DDR Controller */
|
||||
IMX_MMDCDDR_MMUFLAGS, IMX_MMDCDDR_NSECTIONS
|
||||
},
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_IMX6_LCDC
|
||||
{CONFIG_IMX6_LCDC_FB_PBASE, CONFIG_IMX6_LCDC_FB_VBASE,
|
||||
MMU_IOFLAGS, IMX6_LCDC_FBNSECTIONS
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The number of entries in the operational mapping table */
|
||||
|
||||
#define NREMAPPINGS \
|
||||
(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
|
||||
|
||||
const size_t g_num_opmappings = NREMAPPINGS;
|
||||
|
||||
#endif /* NEED_SDRAM_REMAPPING */
|
Loading…
Reference in New Issue
Block a user