Started then stopped development of the STM32 DAC driver -- I guess it isn't needed afterall
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4187 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
b890380f57
commit
c094e68c14
@ -91,7 +91,11 @@
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#define DAC_CR_TSEL_SHIFT (3) /* Bits 3-5: DAC channel1 trigger selection */
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#define DAC_CR_TSEL_MASK (7 << DAC_CR_TSEL_SHIFT)
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# define DAC_CR_TSEL_TIM6 (0 << DAC_CR_TSEL_SHIFT) /* Timer 6 TRGO event */
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#ifdef CONFIG_STM32_CONNECTIVITYLINE
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# define DAC_CR_TSEL_TIM3 (1 << DAC_CR_TSEL_SHIFT) /* Timer 3 TRGO event */
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#else
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# define DAC_CR_TSEL_TIM8 (1 << DAC_CR_TSEL_SHIFT) /* Timer 8 TRGO event */
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#endif
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# define DAC_CR_TSEL_TIM7 (2 << DAC_CR_TSEL_SHIFT) /* Timer 7 TRGO event */
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# define DAC_CR_TSEL_TIM5 (3 << DAC_CR_TSEL_SHIFT) /* Timer 5 TRGO event */
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# define DAC_CR_TSEL_TIM2 (4 << DAC_CR_TSEL_SHIFT) /* Timer 2 TRGO event */
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@ -68,14 +68,226 @@
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#if STM32_NDAC < 2
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# undef CONFIG_STM32_DAC2
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# undef CONFIG_STM32_DAC2_DMA
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# undef CONFIG_STM32_DAC2_TIMER
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# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY
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#endif
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#if STM32_NDAC < 1
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# undef CONFIG_STM32_DAC1
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# undef CONFIG_STM32_DAC1_DMA
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# undef CONFIG_STM32_DAC1_TIMER
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# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY
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#endif
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#if defined(CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
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/* DMA configuration. */
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#if defined(CONFIG_STM32_DAC1_DMA) || defined(CONFIG_STM32_DAC2_DMA)
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# if defined(CONFIG_STM32_STM32F10XX)
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# ifndef CONFIG_STM32_DMA2
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# warning "STM32 F1 DAC DMA support requires CONFIG_STM32_DMA2"
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# undef CONFIG_STM32_DAC1_DMA
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# undef CONFIG_STM32_DAC2_DMA
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# endif
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# elif defined(CONFIG_STM32_STM32F40XX)
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# ifndef CONFIG_STM32_DMA1
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# warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1"
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# undef CONFIG_STM32_DAC1_DMA
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# undef CONFIG_STM32_DAC2_DMA
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# endif
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# else
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# warning "No DAC DMA information for this STM32 family"
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# undef CONFIG_STM32_DAC1_DMA
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# undef CONFIG_STM32_DAC2_DMA
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# endif
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#endif
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/* If DMA is selected, then a timer and output frequency must also be
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* provided to support the DMA transfer. The DMA transfer could be
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* supported by and EXTI trigger, but this feature is not currently
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* supported by the driver.
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*/
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#ifdef CONFIG_STM32_DAC1_DMA
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# if !defined(CONFIG_STM32_DAC1_TIMER)
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# warning "A timer number must be specificed in CONFIG_STM32_DAC1_TIMER"
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# undef CONFIG_STM32_DAC1_DMA
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# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY
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# elif !defined(CONFIG_STM32_DAC1_TIMER_FREQUENCY)
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# warning "A timer frequency must be specificed in CONFIG_STM32_DAC1_TIMER_FREQUENCY"
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# undef CONFIG_STM32_DAC1_DMA
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# undef CONFIG_STM32_DAC1_TIMER
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# endif
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#endif
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#ifdef CONFIG_STM32_DAC2_DMA
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# if !defined(CONFIG_STM32_DAC2_TIMER)
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# warning "A timer number must be specificed in CONFIG_STM32_DAC2_TIMER"
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# undef CONFIG_STM32_DAC2_DMA
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# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY
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# elif !defined(CONFIG_STM32_DAC2_TIMER_FREQUENCY)
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# warning "A timer frequency must be specificed in CONFIG_STM32_DAC2_TIMER_FREQUENCY"
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# undef CONFIG_STM32_DAC2_DMA
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# undef CONFIG_STM32_DAC2_TIMER
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# endif
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#endif
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/* DMA *********************************************************************/
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/* DMA channels and interface values differ for the F1 and F4 families */
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#undef HAVE_DMA
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#if defined(CONFIG_STM32_DAC1_DMA) || defined(CONFIG_STM32_DAC2_DMA)
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# if defined(CONFIG_STM32_STM32F10XX)
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# define HAVE_DMA 1
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# define DAC_DMA 2
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# define DAC1_DMA_CHAN DMACHAN_DAC_CHAN1
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# define DAC2_DMA_CHAN DMACHAN_DAC_CHAN2
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# elif defined(CONFIG_STM32_STM32F40XX)
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# define HAVE_DMA 1
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# define DAC_DMA 1
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# define DAC1_DMA_CHAN DMAMAP_DAC1
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# define DAC2_DMA_CHAN DMAMAP_DAC2
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# endif
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#endif
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/* Timer configuration. The STM32 supports 8 different trigger for DAC
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* output:
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*
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* TSEL SOURCE DEVICES
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* ---- ----------------------- -------------------------------------
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* 000 Timer 6 TRGO event ALL
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* 001 Timer 3 TRGO event STM32 F1 Connectivity Line
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* Timer 8 TRGO event Other STM32 F1 and all STM32 F4
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* 010 Timer 7 TRGO event ALL
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* 011 Timer 5 TRGO event ALL
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* 100 Timer 2 TRGO event ALL
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* 101 Timer 4 TRGO event ALL
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* 110 EXTI line9 ALL
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* 111 SWTRIG Software control ALL
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*
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* This driver does not support the EXTI trigger.
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*/
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#ifdef CONFIG_STM32_DAC1_DMA
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# if CONFIG_STM32_DAC1_TIMER == 6
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# ifndef CONFIG_STM32_TIM6
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# error "CONFIG_STM32_TIM6 required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6
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# define DAC1_TIMER_BASE STM32_TIM6_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM3
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# error "CONFIG_STM32_TIM3 required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM3
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# define DAC1_TIMER_BASE STM32_TIM3_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM8
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# error "CONFIG_STM32_TIM8 required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8
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# define DAC1_TIMER_BASE STM32_TIM8_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 7
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# ifndef CONFIG_STM32_TIM7
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# error "CONFIG_STM32_TIM7 required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7
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# define DAC1_TIMER_BASE STM32_TIM7_BASE
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# elif CONFIG_STM32_DAC1_TIMER == 5
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# ifndef CONFIG_STM32_TIM5
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# error "CONFIG_STM32_TIM5 required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5
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# define DAC1_TIMER_BASE STM32_TIM5_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 2
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# ifndef CONFIG_STM32_TIM2
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# error "CONFIG_STM32_TIM2 required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2
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# define DAC1_TIMER_BASE STM32_TIM2_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 4
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# ifndef CONFIG_STM32_TIM4
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# error "CONFIG_STM32_TIM4 required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4
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# define DAC1_TIMER_BASE STM32_TIM4_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# else
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# error "Unsupported CONFIG_STM32_DAC1_TIMER"
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# endif
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#else
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_SW
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#endif
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#ifdef CONFIG_STM32_DAC2_DMA
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# if CONFIG_STM32_DAC2_TIMER == 6
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# ifndef CONFIG_STM32_TIM6
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# error "CONFIG_STM32_TIM6 required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6
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# define DAC2_TIMER_BASE STM32_TIM6_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM3
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# error "CONFIG_STM32_TIM3 required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM3
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# define DAC2_TIMER_BASE STM32_TIM3_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM8
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# error "CONFIG_STM32_TIM8 required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8
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# define DAC2_TIMER_BASE STM32_TIM8_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 7
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# ifndef CONFIG_STM32_TIM7
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# error "CONFIG_STM32_TIM7 required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7
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# define DAC2_TIMER_BASE STM32_TIM7_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 5
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# ifndef CONFIG_STM32_TIM5
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# error "CONFIG_STM32_TIM5 required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5
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# define DAC2_TIMER_BASE STM32_TIM5_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 2
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# ifndef CONFIG_STM32_TIM2
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# error "CONFIG_STM32_TIM2 required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2
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# define DAC2_TIMER_BASE STM32_TIM2_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 4
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# ifndef CONFIG_STM32_TIM4
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# error "CONFIG_STM32_TIM4 required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4
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# define DAC2_TIMER_BASE STM32_TIM4_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# else
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# error "Unsupported CONFIG_STM32_DAC2_TIMER"
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# endif
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#else
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_SW
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#endif
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/* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and
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* CONFIG_STM32_DACn_TIMER_FREQUENCY.
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*/
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#warning "Missing Logic"
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -84,15 +296,24 @@
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struct stm32_dac_s
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{
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uint8_t init : 1; /* True, the DAC block has been initialized */
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uint8_t init : 1; /* True, the DAC block has been initialized */
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};
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/* This structure represents the internal state of one STM32 DAC channel */
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struct stm32_chan_s
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{
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uint8_t inuse : 1; /* True, the driver is in use and not available */
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uint8_t intf; /* DAC zero-based interface number (0 or 1) */
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uint8_t inuse : 1; /* True, the driver is in use and not available */
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#ifdef HAVE_DMA
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uint8_t hasdma : 1; /* True, this channel supports DMA */
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#endif
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uint8_t intf; /* DAC zero-based interface number (0 or 1) */
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#ifdef HAVE_DMA
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uint16_t dmachan; /* DMA channel needed by this DAC */
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DMA_HANDLE dma; /* Allocated DMA channel */
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uint32_t tsel; /* CR trigger select value */
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uint32_t tbase; /* Timer base address */
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#endif
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};
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/****************************************************************************
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@ -100,8 +321,10 @@ struct stm32_chan_s
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****************************************************************************/
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/* DAC Register access */
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static uint32_t dac_getreg(struct stm32_chan_s *chan, int offset);
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static void dac_putreg(struct stm32_chan_s *chan, int offset, uint32_t value);
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#ifdef HAVE_DMA
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static uint32_t tim_getreg(struct stm32_chan_s *chan, int offset);
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static void tim_putreg(struct stm32_chan_s *chan, int offset, uint32_t value);
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#endif
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/* Interrupt handler */
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@ -121,6 +344,9 @@ static int dac_interrupt(int irq, void *context);
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/* Initialization */
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#ifdef HAVE_DMA
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static int dac_timinit(struct stm32_chan_s *chan);
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#endif
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static int dac_chaninit(struct stm32_chan_s *chan);
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static int dac_blockinit(void);
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@ -142,6 +368,12 @@ static const struct dac_ops_s g_dacops =
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static struct stm32_chan_s g_dac1priv =
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{
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.intf = 0;
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#ifdef CONFIG_STM32_DAC1_DMA
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.hasdma = 1;
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.dmachan = DAC1_DMA_CHAN,
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.tsel = DAC1_TSEL_VALUE,
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.tbase = DAC1_TIMER_BASE
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#endif
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}
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static struct dac_dev_s g_dac1dev =
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@ -155,6 +387,12 @@ static struct dac_dev_s g_dac1dev =
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static struct stm32_chan_s g_dac2priv =
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{
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.intf = 1;
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#ifdef CONFIG_STM32_DAC2_DMA
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.hasdma = 1;
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.dmachan = DAC2_DMA_CHAN,
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.tsel = DAC2_TSEL_VALUE.
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.tbase = DAC2_TIMER_BASE
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#endif
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}
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static struct dac_dev_s g_dac2dev =
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@ -171,10 +409,10 @@ static struct stm32_dac_s g_dacblock;
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****************************************************************************/
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/****************************************************************************
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* Name: dac_getreg
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* Name: tim_getreg
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*
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* Description:
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* Read the value of an DAC register.
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* Read the value of an DMA timer register.
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*
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* Input Parameters:
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* chan - A reference to the DAC block status
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@ -185,16 +423,18 @@ static struct stm32_dac_s g_dacblock;
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*
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****************************************************************************/
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static uint32_t dac_getreg(struct stm32_chan_s *chan, int offset)
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#ifdef HAVE_DMA
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static uint32_t tim_getreg(struct stm32_chan_s *chan, int offset)
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{
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return getreg32(chan->base + offset);
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return getreg32(chan->tbase + offset);
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}
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#endif
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/****************************************************************************
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* Name: dac_getreg
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* Name: tim_putreg
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*
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* Description:
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* Read the value of an DAC register.
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* Read the value of an DMA timer register.
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*
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* Input Parameters:
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* chan - A reference to the DAC block status
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@ -205,10 +445,11 @@ static uint32_t dac_getreg(struct stm32_chan_s *chan, int offset)
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*
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****************************************************************************/
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static void dac_putreg(struct stm32_chan_s *chan, int offset, uint32_t value)
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static void tim_putreg(struct stm32_chan_s *chan, int offset, uint32_t value)
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{
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putreg32(value, chan->base + offset);
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putreg32(value, chan->tbase + offset);
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}
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#endif
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/****************************************************************************
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* Name: dac_interrupt
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@ -227,6 +468,7 @@ static void dac_putreg(struct stm32_chan_s *chan, int offset, uint32_t value)
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#ifdef CONFIG_STM32_STM32F40XX
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static int dac_interrupt(int irq, void *context)
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{
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#warning "Missing logic"
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return OK;
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}
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#endif
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@ -252,6 +494,10 @@ static void dac_reset(FAR struct dac_dev_s *dev)
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irqstate_t flags;
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uint32_t regval;
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/* Reset only the selected DAC channel; the other DAC channel must remain
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* functional.
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*/
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flags = irqsave();
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#warning "Missing logic"
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@ -333,7 +579,40 @@ static void dac_txint(FAR struct dac_dev_s *dev, bool enable)
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static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
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{
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# warning "Missing logic"
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#ifdef HAVE_DMA
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if (priv->hasdma)
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{
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/* Configure the DMA stream/channel.
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*
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* - Channel number
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* - Peripheral address
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* - Direction: Memory to peripheral
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* - Disable peripheral address increment
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* - Enable memory address increment
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* - Peripheral data size: half word
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* - Mode: circular???
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* - Priority: ?
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* - FIFO mode: disable
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* - FIFO threshold: half full
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* - Memory Burst: single
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* - Peripheral Burst: single
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*/
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#warning "Missing logic"
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/* Enable DMA */
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#warning "Missing logic"
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/* Enable DAC Channel */
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#warning "Missing logic"
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/* Enable DMA for DAC Channel */
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#warning "Missing logic"
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}
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||||
else
|
||||
{
|
||||
/* Non-DMA transfer */
|
||||
#warning "Missing logic"
|
||||
}
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
@ -356,12 +635,44 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: dac_ioctl
|
||||
* Name: dac_timinit
|
||||
*
|
||||
* Description:
|
||||
* All ioctl calls will be routed through this method.
|
||||
* Initialize the timer that drivers the DAC DMA for this channel using
|
||||
* the pre-calculated timer divider definitions.
|
||||
*
|
||||
* Input Parameters:
|
||||
* chan - A reference to the DAC channel state data
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_DMA
|
||||
static int dac_timinit(struct stm32_chan_s *chan)
|
||||
{
|
||||
/* Configure the time base: Timer period, prescaler, clock division,
|
||||
* counter mode (up).
|
||||
*/
|
||||
#warning "Missing Logic"
|
||||
|
||||
/* Selection TRGO selection: update */
|
||||
#warning "Missing Logic"
|
||||
|
||||
/* Enable the counter */
|
||||
#warning "Missing Logic"
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: dac_chaninit
|
||||
*
|
||||
* Description:
|
||||
* Initialize the DAC channel.
|
||||
*
|
||||
* Input Parameters:
|
||||
* chan - A reference to the DAC channel state data
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
@ -379,6 +690,49 @@ static int dac_chaninit(struct stm32_chan_s *chan)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Configure the DAC output pin:
|
||||
*
|
||||
* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
|
||||
* (PA4 or PA5) is automatically connected to the analog converter output
|
||||
* (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
|
||||
* should first be configured to analog (AIN)".
|
||||
*/
|
||||
|
||||
stm32_configgpio(chan->intf ? GPIO_DAC2_OUT : GPIO_DAC1_OUT);
|
||||
|
||||
/* DAC channel configuration:
|
||||
*
|
||||
* - Set the trigger selection based upon the configuration.
|
||||
* - Set wave generation == None.
|
||||
* - Enable the output buffer.
|
||||
*/
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Determine if DMA is supported by this channel */
|
||||
|
||||
#ifdef HAVE_DMA
|
||||
if (priv->hasdma)
|
||||
{
|
||||
/* Yes.. allocate a DMA channel */
|
||||
|
||||
priv->dma = stm32_dmachannel(priv->dmachan);
|
||||
if (!priv->dma)
|
||||
{
|
||||
adbg("Failed to allocate a DMA channel\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Configure the timer that supports the DMA operation */
|
||||
|
||||
ret = dac_timinit(chan);
|
||||
if (ret < 0)
|
||||
{
|
||||
adbg("Failed to initialize the DMA timer: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Mark the DAC channel "in-use" */
|
||||
|
||||
chan->inuse = 1;
|
||||
@ -386,7 +740,7 @@ static int dac_chaninit(struct stm32_chan_s *chan)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: dac_ioctl
|
||||
* Name: dac_blockinit
|
||||
*
|
||||
* Description:
|
||||
* All ioctl calls will be routed through this method.
|
||||
|
||||
@ -298,7 +298,7 @@ static inline void rcc_enableapb1(void)
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
#endif
|
||||
|
||||
#ifdefined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
|
||||
#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
|
||||
/* DAC interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DACEN;
|
||||
|
||||
@ -431,7 +431,7 @@ static inline void rcc_enableapb1(void)
|
||||
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
|
||||
#ifdefined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
|
||||
#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
|
||||
/* DAC interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DACEN;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user