diff --git a/drivers/ioexpander/Kconfig b/drivers/ioexpander/Kconfig index e1818e3cbb..feb5e942b3 100644 --- a/drivers/ioexpander/Kconfig +++ b/drivers/ioexpander/Kconfig @@ -40,15 +40,60 @@ config PCA9555_INT_ENABLE config PCA9555_INT_NCALLBACKS int "Max number of interrupt callbacks" default 4 - depends on IOEXPANDER_INT_ENABLE + depends on PCA9555_INT_ENABLE ---help--- This is the maximum number of interrupt callbacks supported endif # IOEXPANDER_PCA9555 +config IOEXPANDER_TCA64XX + bool "TCA64XX I2C IO expander" + default n + select I2C + depends on EXPERIMENTAL + ---help--- + Enable support for the NXP TCA64XX IO Expander + +if IOEXPANDER_TCA64XX + +config TCA64XX_MULTIPLE + bool "Multiple TCA64XX Devices" + default n + ---help--- + Can be defined to support multiple TCA64XX devices on board. + +config TCA64XX_INT_ENABLE + bool "Enable TCA64XX Interrupt Support" + default n + select IOEXPANDER_INT_ENABLE + ---help--- + Enable driver interrupt functionality + +config TCA64XX_INT_NCALLBACKS + int "Max number of interrupt callbacks" + default 4 + depends on TCA64XX_INT_ENABLE + ---help--- + This is the maximum number of interrupt callbacks supported + +config TCA64XX_INT_POLL + bool "Enable interrupt poll" + default n + ---help--- + Enable polling for missed interrupts. + +config TCA64XX_INT_POLLDELAY + int "Interrupt poll delay (used)" + default 500000 + depends on TCA64XX_INT_POLL + ---help--- + This microsecond delay defines the polling rate for missed interrupts. + +endif # IOEXPANDER_TCA64XX + config IOEXPANDER_INT_ENABLE bool - default y if PCA9555_INT_ENABLE + default n ---help--- This is the global INT supported flag for io expanders diff --git a/drivers/ioexpander/Make.defs b/drivers/ioexpander/Make.defs index 37e669fe94..87114f6e5b 100644 --- a/drivers/ioexpander/Make.defs +++ b/drivers/ioexpander/Make.defs @@ -43,6 +43,10 @@ ifeq ($(CONFIG_IOEXPANDER_PCA9555),y) CSRCS += pca9555.c endif +ifeq ($(CONFIG_IOEXPANDER_TCA64XX),y) + CSRCS += tca64xx.c +endif + endif # CONFIG_IOEXPANDER # GPIO test device driver (independent of IOEXPANDERS) diff --git a/drivers/ioexpander/tca64xx.c b/drivers/ioexpander/tca64xx.c new file mode 100644 index 0000000000..e882bf26d2 --- /dev/null +++ b/drivers/ioexpander/tca64xx.c @@ -0,0 +1,1359 @@ +/**************************************************************************** + * include/nuttx/ioexpander/tca64xx.h + * Supports the following parts: TCA6408, TCA6416, TCA6424 + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * This header file derives, in part, from the Project Ara TCA64xx driver + * which has this copyright: + * + * Copyright (c) 2014-2015 Google Inc. + * All rights reserved. + * Author: Patrick Titiano, Jean Pihet + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "tca64xx.h" + +#ifdef CONFIG_IOEXPANDER_TCA64XX + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MAX +# define MAX(a,b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +# define MIN(a,b) (((a) < (b)) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* TCA64xx Helpers */ + +static void tca64_lock(FAR struct tca64_dev_s *priv); +static FAR const struct tca64_part_s *tca64_getpart(FAR struct tca64_dev_s *priv); +static uint8_t tca64_ngpios(FAR struct tca64_dev_s *priv); +static uint8_t tca64_input_reg(FAR struct tca64_dev_s *priv, uint8_t pin); +static uint8_t tca64_output_reg(FAR struct tca64_dev_s *priv, uint8_t pin); +static uint8_t tca64_polarity_reg(FAR struct tca64_dev_s *priv, uint8_t pin); +static uint8_t tca64_config_reg(FAR struct tca64_dev_s *priv, uint8_t pin); +static int tca64_getreg(FAR struct tca64_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, unsigned int count); +static int tca64_putreg(struct tca64_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, unsigned int count); + +/* I/O Expander Methods */ + +static int tca64_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int dir); +static int tca64_option(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int opt, void *regval); +static int tca64_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + bool value); +static int tca64_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value); +#ifdef CONFIG_IOEXPANDER_MULTIPIN +static int tca64_multiwritepin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, int count); +static int tca64_multireadpin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, int count); +#endif +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +static int tca64_attach(FAR struct ioexpander_dev_s *dev, + ioe_pinset_t pinset, ioe_callback_t callback); +#endif + +#ifdef CONFIG_TCA64XX_INT_ENABLE +static void tca64_int_update(void *handle, ioe_pinset_t input, + ioe_pinset_t mask); +static void tca64_register_update(FAR struct tca64_dev_s *priv); +static void tca64_irqworker(void *arg); +static void tca64_interrupt(FAR void *arg); +#ifdef CONFIG_TCA64XX_INT_POLL +static void tca64_poll_expiry(int argc, wdparm_t arg1, ...); +#endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifndef CONFIG_TCA64XX_MULTIPLE +/* If only a single device is supported, then the driver state structure may + * as well be pre-allocated. + */ + +static struct tca64_dev_s g_tca64; +#endif + +/* I/O expander vtable */ + +static const struct ioexpander_ops_s g_tca64_ops = +{ + tca64_direction, + tca64_option, + tca64_writepin, + tca64_readpin, + tca64_readpin +#ifdef CONFIG_IOEXPANDER_MULTIPIN + , tca64_multiwritepin + , tca64_multireadpin + , tca64_multireadpin +#endif +#ifdef CONFIG_IOEXPANDER_INT_ENABLE + , tca64_attach +#endif +}; + +/* TCA64 part data */ + +static const struct tca64_part_s g_tca64_parts[TCA64_NPARTS] = +{ + { + TCA6408_PART, + MIN(TCA6408_NR_GPIOS, CONFIG_IOEXPANDER_NPINS), + TCA6408_INPUT_REG, + TCA6408_OUTPUT_REG, + TCA6408_POLARITY_REG, + TCA6408_CONFIG_REG, + }, + { + TCA6416_PART, + MIN(TCA6416_NR_GPIOS, CONFIG_IOEXPANDER_NPINS), + TCA6416_INPUT0_REG, + TCA6416_OUTPUT0_REG, + TCA6416_POLARITY0_REG, + TCA6416_CONFIG0_REG, + }, + { + TCA6424_PART, + MIN(TCA6424_NR_GPIOS, CONFIG_IOEXPANDER_NPINS), + TCA6424_INPUT0_REG, + TCA6424_OUTPUT0_REG, + TCA6424_POLARITY0_REG, + TCA6424_CONFIG0_REG, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tca64_lock + * + * Description: + * Get exclusive access to the I/O Expander + * + ****************************************************************************/ + +static void tca64_lock(FAR struct tca64_dev_s *priv) +{ + while (sem_wait(&priv->exclsem) < 0) + { + /* EINTR is the only expected error from sem_wait() */ + + DEBUGASSERT(errno == EINTR); + } +} + +#define tca64_unlock(p) sem_post(&(p)->exclsem) + +/**************************************************************************** + * Name: tca64_getpart + * + * Description: + * Look up information for the selected part + * + ****************************************************************************/ + +static FAR const struct tca64_part_s *tca64_getpart(FAR struct tca64_dev_s *priv) +{ + DEBUGASSERT(priv != NULL && priv->config != NULL && + priv->config->part < TCA64_NPARTS); + + return &g_tca64_parts[priv->config->part]; +} + +/**************************************************************************** + * Name: tca64_ngpios + * + * Description: + * Return the number of GPIOs supported by the selected part + * + ****************************************************************************/ + +static uint8_t tca64_ngpios(FAR struct tca64_dev_s *priv) +{ + FAR const struct tca64_part_s *part = tca64_getpart(priv); + return part->tp_ngpios; +} + +/**************************************************************************** + * Name: tca64_input_reg + * + * Description: + * Return the address of the input register for the specified pin. + * + ****************************************************************************/ + +static uint8_t tca64_input_reg(FAR struct tca64_dev_s *priv, uint8_t pin) +{ + FAR const struct tca64_part_s *part = tca64_getpart(priv); + uint8_t reg = part->tp_output; + + DEBUGASSERT(pin <= part->tp_ngpios); + return reg + (pin >> 3); +} + +/**************************************************************************** + * Name: tca64_output_reg + * + * Description: + * Return the address of the output register for the specified pin. + * + ****************************************************************************/ + +static uint8_t tca64_output_reg(FAR struct tca64_dev_s *priv, uint8_t pin) +{ + FAR const struct tca64_part_s *part = tca64_getpart(priv); + uint8_t reg = part->tp_output; + + DEBUGASSERT(pin <= part->tp_ngpios); + return reg + (pin >> 3); +} + +/**************************************************************************** + * Name: tca64_polarity_reg + * + * Description: + * Return the address of the polarity register for the specified pin. + * + ****************************************************************************/ + +static uint8_t tca64_polarity_reg(FAR struct tca64_dev_s *priv, uint8_t pin) +{ + FAR const struct tca64_part_s *part = tca64_getpart(priv); + uint8_t reg = part->tp_output; + + DEBUGASSERT(pin <= part->tp_ngpios); + return reg + (pin >> 3); +} + +/**************************************************************************** + * Name: tca64_config_reg + * + * Description: + * Return the address of the configuration register for the specified pin. + * + ****************************************************************************/ + +static uint8_t tca64_config_reg(FAR struct tca64_dev_s *priv, uint8_t pin) +{ + FAR const struct tca64_part_s *part = tca64_getpart(priv); + uint8_t reg = part->tp_config; + + DEBUGASSERT(pin <= part->tp_ngpios); + return reg + (pin >> 3); +} + +/**************************************************************************** + * Name: tca64_getreg + * + * Description: + * Read an 8-bit value from a TCA64xx register + * + ****************************************************************************/ + +static int tca64_getreg(FAR struct tca64_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, unsigned int count) +{ + struct i2c_msg_s msg[2]; + int ret; + + DEBUGASSERT(priv != NULL && priv->i2c != NULL && priv->config != NULL); + + /* Set up for the transfer */ + + msg[0].frequency = TCA64XX_I2C_MAXFREQUENCY, + msg[0].addr = priv->config->address, + msg[0].flags = 0, + msg[0].buffer = ®addr, + msg[0].length = 1, + + msg[1].frequency = TCA64XX_I2C_MAXFREQUENCY, + msg[1].addr = priv->config->address, + msg[1].flags = I2C_M_READ, + msg[1].buffer = regval, + msg[1].length = count, + + /* Perform the transfer */ + + ret = I2C_TRANSFER(priv->i2c, msg, 2); + if (ret < 0) + { + gpioerr("ERROR: I2C addr=%02x regaddr=%02x: failed, ret=%d!\n", + priv->config->address, regaddr, ret); + } + else + { + gpioinfo("I2C addr=%02x regaddr=%02x: read %02x\n", + priv->config->address, regaddr, *regval); + } + + return ret; +} + +/**************************************************************************** + * Name: tca64_putreg + * + * Description: + * Write an 8-bit value to a TCA64xx register + * + ****************************************************************************/ + +static int tca64_putreg(struct tca64_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, unsigned int count) +{ + struct i2c_msg_s msg[1]; + uint8_t cmd[2]; + int ret; + int i; + + DEBUGASSERT(priv != NULL && priv->i2c != NULL && priv->config != NULL); + + /* Set up for the transfer */ + + cmd[0] = regaddr; + + for (i = 0; i < count; i++) + { + cmd[i+1] = regval[i]; + } + + msg[0].frequency = TCA64XX_I2C_MAXFREQUENCY, + msg[0].addr = priv->config->address, + msg[0].flags = 0, + msg[0].buffer = cmd, + msg[0].length = count + 1, + + ret = I2C_TRANSFER(priv->i2c, msg, 1); + if (ret < 0) + { + gpioerr("ERROR: claddr=%02x, regaddr=%02x: failed, ret=%d!\n", + priv->config->address, regaddr, ret); + } + else + { + gpioinfo("claddr=%02x, regaddr=%02x, regval=%02x\n", + priv->config->address, regaddr, regval); + } + + return ret; +} + +/**************************************************************************** + * Name: tca64_direction + * + * Description: + * Set the direction of an ioexpander pin. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * dir - One of the IOEXPANDER_DIRECTION_ macros + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int tca64_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int direction) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)dev; + uint8_t regaddr; + uint8_t regval; + int ret; + + DEBUGASSERT(priv != NULL && priv->config != NULL && + pin < CONFIG_IOEXPANDER_NPINS && + (direction == IOEXPANDER_DIRECTION_IN || + direction == IOEXPANDER_DIRECTION_IN)); + + gpioinfo("I2C addr=%02x pin=%u direction=%s\n", + priv->config->address, pin, + (direction == IOEXPANDER_DIRECTION_IN) ? "IN" : "OUT"); + + /* Get exclusive access to the I/O Expander */ + + tca64_lock(priv); + + /* Read the Configuration Register associated with this pin. The + * Configuration Register configures the direction of the I/O pins. + */ + + regaddr = tca64_config_reg(priv, pin); + ret = tca64_getreg(priv, regaddr, ®val, 1); + if (ret < 0) + { + gpioerr("ERROR: Failed to read config register at %u: %d\n", + regaddr, ret); + goto errout_with_lock; + } + + /* Set the pin direction in the I/O Expander */ + + if (direction == IOEXPANDER_DIRECTION_IN) + { + /* Configure pin as input. If a bit in the configuration register is + * set to 1, the corresponding port pin is enabled as an input with a + * high-impedance output driver. + */ + + regval |= (1 << (pin & 7)); + } + else /* if (direction == IOEXPANDER_DIRECTION_OUT) */ + { + /* Configure pin as output. If a bit in this register is cleared to + * 0, the corresponding port pin is enabled as an output. + * + * REVISIT: The value of output has not been selected! This might + * put a glitch on the output. + */ + + regval &= ~(1 << (pin & 7)); + } + + /* Write back the modified register content */ + + ret = tca64_putreg(priv, regaddr, ®val, 1); + if (ret < 0) + { + gpioerr("ERROR: Failed to write config register at %u: %d\n", + regaddr, ret); + } + +errout_with_lock: + tca64_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: tca64_option + * + * Description: + * Set pin options. Required. + * Since all IO expanders have various pin options, this API allows setting + * pin options in a flexible way. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * opt - One of the IOEXPANDER_OPTION_ macros + * val - The option's value + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int tca64_option(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int opt, FAR void *value) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)dev; + int ret = -ENOSYS; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + gpioinfo("I2C addr=%02x pin=%u option=%u\n", + priv->config->address, pin, opt); + + /* Check for pin polarity inversion. The Polarity Inversion Register + * allows polarity inversion of pins defined as inputs by the + * Configuration Register. If a bit in this register is set, the + * corresponding port pin's polarity is inverted. If a bit in this + * register is cleared, the corresponding port pin's original polarity + * is retained. + */ + + if (opt == IOEXPANDER_OPTION_INVERT) + { + unsigned int ival = (unsigned int)((uintptr_t)value); + uint8_t regaddr; + uint8_t polarity; + + /* Get exclusive access to the I/O Expander */ + + tca64_lock(priv); + + /* Read the polarity register */ + + regaddr = tca64_polarity_reg(priv, pin); + ret = tca64_getreg(priv, regaddr, &polarity, 1); + if (ret < 0) + { + gpioerr("ERROR: Failed to read polarity register at %u: %d\n", + regaddr, ret); + tca64_unlock(priv); + return ret; + } + + /* Set/clear the pin option */ + + if (ival == IOEXPANDER_OPTION_INVERT) + { + polarity |= (1 << (pin & 7)); + } + else + { + polarity &= ~(1 << (pin & 7)); + } + + /* Write back the modified register */ + + ret = tca64_putreg(priv, regaddr, &polarity, 1); + if (ret < 0) + { + gpioerr("ERROR: Failed to read polarity register at %u: %d\n", + regaddr, ret); + } + + tca64_unlock(priv); + } + +#ifdef CONFIG_TCA64XX_INT_ENABLE + /* Interrupt configuration */ + + else if (opt == IOEXPANDER_OPTION_INTCFG) + { + unsigned int ival = (unsigned int)((uintptr_t)value); + ioe_pinset_t bit = ((ioe_pinset_t)1 << pin); + + ret = OK; + tca64_lock(priv); + switch (ival) + { + case IOEXPANDER_VAL_HIGH: /* Interrupt on high level */ + priv->trigger &= ~bit; + priv->level[0] |= bit; + priv->level[1] &= ~bit; + break; + + case IOEXPANDER_VAL_LOW: /* Interrupt on low level */ + priv->trigger &= ~bit; + priv->level[0] &= ~bit; + priv->level[1] |= bit; + break; + + case IOEXPANDER_VAL_RISING: /* Interrupt on rising edge */ + priv->trigger |= bit; + priv->level[0] |= bit; + priv->level[1] &= ~bit; + break; + + case IOEXPANDER_VAL_FALLING: /* Interrupt on falling edge */ + priv->trigger |= bit; + priv->level[0] &= ~bit; + priv->level[1] |= bit; + break; + + case IOEXPANDER_VAL_BOTH: /* Interrupt on both edges */ + priv->trigger |= bit; + priv->level[0] |= bit; + priv->level[1] |= bit; + break; + + default: + ret = -EINVAL; + } + + tca64_unlock(priv); + } +#endif + + return ret; +} + +/**************************************************************************** + * Name: tca64_writepin + * + * Description: + * Set the pin level. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * val - The pin level. Usually TRUE will set the pin high, + * except if OPTION_INVERT has been set on this pin. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int tca64_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + bool value) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)dev; + uint8_t regaddr; + uint8_t regval; + int ret; + + DEBUGASSERT(priv != NULL && priv->config != NULL && + pin < CONFIG_IOEXPANDER_NPINS); + + gpioinfo("I2C addr=%02x pin=%u value=%u\n", + priv->config->address, pin, value); + + /* Get exclusive access to the I/O Expander */ + + tca64_lock(priv); + + /* Read the output register. */ + + regaddr = tca64_output_reg(priv, pin); + ret = tca64_getreg(priv, regaddr, ®val, 1); + if (ret < 0) + { + gpioerr("ERROR: Failed to read output register at %u: %d\n", + regaddr, ret); + goto errout_with_lock; + } + + /* Set output pins default value (before configuring it as output) The + * Output Port Register shows the outgoing logic levels of the pins + * defined as outputs by the Configuration Register. + */ + + if (value != 0) + { + regval |= (1 << (pin % 8)); + } + else + { + regval &= ~(1 << (pin % 8)); + } + + /* Write the modified output register value */ + + ret = tca64_putreg(priv, regaddr, ®val, 1); + if (ret < 0) + { + gpioerr("ERROR: Failed to write output register at %u: %d\n", + regaddr, ret); + } + +errout_with_lock: + tca64_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: tca64_readpin + * + * Description: + * Read the actual PIN level. This can be different from the last value written + * to this pin. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin + * valptr - Pointer to a buffer where the pin level is stored. Usually TRUE + * if the pin is high, except if OPTION_INVERT has been set on this pin. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int tca64_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)dev; + uint8_t regaddr; + uint8_t regval; + int ret; + + DEBUGASSERT(priv != NULL && priv->config != NULL && + pin < CONFIG_IOEXPANDER_NPINS && value != NULL); + + gpioinfo("I2C addr=%02x, pin=%u\n", priv->config->address, pin); + + /* Get exclusive access to the I/O Expander */ + + tca64_lock(priv); + + /* Read the input register for this pin + * + * The Input Port Register reflects the incoming logic levels of the pins, + * regardless of whether the pin is defined as an input or an output by + * the Configuration Register. They act only on read operation. + */ + + regaddr = tca64_input_reg(priv, pin); + ret = tca64_getreg(priv, regaddr, ®val, 1); + if (ret < 0) + { + gpioerr("ERROR: Failed to read input register at %u: %d\n", + regaddr, ret); + goto errout_with_lock; + } + +#ifdef CONFIG_TCA64XX_INT_ENABLE + /* Update the input status with the 8 bits read from the expander */ + + tca64_int_update(priv, (ioe_pinset_t)regval << (pin & ~7), + (ioe_pinset_t)0xff << (pin & ~7)); +#endif + + /* Return 0 or 1 to indicate the state of pin */ + + ret = (regval >> (pin & 7)) & 1; + +errout_with_lock: + tca64_unlock(priv); + return ret; +} + +/**************************************************************************** + * Name: tca64_multiwritepin + * + * Description: + * Set the pin level for multiple pins. This routine may be faster than + * individual pin accesses. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * pins - The list of pin indexes to alter in this call + * val - The list of pin levels. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +#ifdef CONFIG_IOEXPANDER_MULTIPIN +static int tca64_multiwritepin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, + int count) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)dev; + ioe_pinset_t pinset; + uint8_t regaddr; + uint8_t ngpios; + uint8_t nregs; + uint8_t pin; + int ret; + int i; + + /* Get exclusive access to the I/O Expander */ + + tca64_lock(priv); + + /* Read the output registers for pin 0 through the number of supported + * pins. + */ + + ngpios = tca64_ngpios(priv); + nregs = (ngpios + 7) >> 3; + pinset = 0; + regaddr = tca64_output_reg(priv, 0); + + ret = tca64_getreg(priv, regaddr, (FAR uint8_t *)&pinset, nregs); + if (ret < 0) + { + gpioerr("ERROR: Failed to read %u ouput registers at %u: %d\n", + nregs, regaddr, ret); + goto errout_with_lock; + } + + /* Apply the user defined changes */ + + for (i = 0; i < count; i++) + { + pin = pins[i]; + DEBUGASSERT(pin < CONFIG_IOEXPANDER_NPINS); + + if (values[i]) + { + pinset |= (1 << pin); + } + else + { + pinset &= ~(1 << pin); + } + } + + /* Now write back the new pins states */ + + ret = tca64_putreg(priv, regaddr, (FAR uint8_t *)&pinset, nregs); + if (ret < 0) + { + gpioerr("ERROR: Failed to write %u output registers at %u: %d\n", + nregs, regaddr, ret); + } + +errout_with_lock: + tca64_unlock(priv); + return ret; +} +#endif + +/**************************************************************************** + * Name: tca64_multireadpin + * + * Description: + * Read the actual level for multiple pins. This routine may be faster than + * individual pin accesses. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The list of pin indexes to read + * valptr - Pointer to a buffer where the pin levels are stored. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +#ifdef CONFIG_IOEXPANDER_MULTIPIN +static int tca64_multireadpin(FAR struct ioexpander_dev_s *dev, + FAR uint8_t *pins, FAR bool *values, + int count) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)dev; + ioe_pinset_t pinset; + uint8_t regaddr; + uint8_t ngpios; + uint8_t nregs; + uint8_t pin; + int ret; + int i; + + DEBUGASSERT(priv != NULL && priv->config != NULL && pins != NULL && + values != NULL && count > 0); + + gpioinfo("I2C addr=%02x, count=%u\n", priv->config->address, count); + + /* Get exclusive access to the I/O Expander */ + + tca64_lock(priv); + + /* Read the input register for pin 0 through the number of supported pins. + * + * The Input Port Register reflects the incoming logic levels of the pins, + * regardless of whether the pin is defined as an input or an output by + * the Configuration Register. They act only on read operation. + */ + + ngpios = tca64_ngpios(priv); + nregs = (ngpios + 7) >> 3; + pinset = 0; + regaddr = tca64_input_reg(priv, 0); + + ret = tca64_getreg(priv, regaddr, (FAR uint8_t *)&pinset, nregs); + if (ret < 0) + { + gpioerr("ERROR: Failed to read input %u registers at %u: %d\n", + nregs, regaddr, ret); + goto errout_with_lock; + } + + /* Update the input status with the 8 bits read from the expander */ + + for (i = 0; i < count; i++) + { + pin = pins[i]; + DEBUGASSERT(pin < CONFIG_IOEXPANDER_NPINS); + + values[i] = ((pinset & (1 << pin)) != 0); + } + +#ifdef CONFIG_TCA64XX_INT_ENABLE + /* Update the input status with the 32 bits read from the expander */ + + tca64_int_update(priv, pinset, ~0); +#endif + +errout_with_lock: + tca64_unlock(priv); + return ret; +} +#endif + +/**************************************************************************** + * Name: tca64_attach + * + * Description: + * Attach a pin interrupt callback function. + * + * Input Parameters: + * dev - Device-specific state data + * pinset - The set of pin events that will generate the callback + * callback - The pointer to callback function. NULL will detach the + * callback. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +#ifdef CONFIG_TCA64XX_INT_ENABLE +static int tca64_attach(FAR struct ioexpander_dev_s *dev, ioe_pinset_t pinset, + ioe_callback_t callback) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)dev; + int ret; + int i; + + /* Get exclusive access to the I/O Expander */ + + tca64_lock(priv); + + /* Find and available in entry in the callback table */ + + ret = -ENOSPC; + for (i = 0; i < CONFIG_TCA64XX_INT_NCALLBACKS; i++) + { + /* Is this entry available (i.e., no callback attached) */ + + if (priv->cb[i].cbfunc == NULL) + { + /* Yes.. use this entry */ + + priv->cb[i].pinset = pinset; + priv->cb[i].cbfunc = callback; + ret = OK; + } + } + + /* Add this callback to the table */ + + tca64_unlock(priv); + return ret; +} +#endif + +/**************************************************************************** + * Name: tca64_int_update + * + * Description: + * Check for pending interrupts. + * + ****************************************************************************/ + +#ifdef CONFIG_TCA64XX_INT_ENABLE +static void tca64_int_update(void *handle, ioe_pinset_t input, + ioe_pinset_t mask) +{ + struct tca64_dev_s *priv = handle; + uint32_t diff, ngios = tca64_ngpios(priv); + irqstate_t flags; + int pin; + + flags = enter_critical_section(); + + /* Check the changed bits from last read */ + + input = (priv->input & ~mask) | (input & mask); + diff = priv->input ^ input; + + if (!diff) + { + leave_critical_section(flags); + return; + } + + priv->input = input; + + /* TCA64XX doesn't support irq trigger, we have to do this in software. */ + + for (pin = 0; pin < ngios; pin++) + { + if (TCA64_EDGE_SENSITIVE(priv, pin) && (diff & 1)) + { + /* Edge triggered. Set interrupt in function of edge type */ + + if (((input & 1) == 0 && TCA64_EDGE_FALLING(priv, pin)) || + ((input & 1) != 0 && TCA64_EDGE_RISING(priv, pin))) + { + priv->intstat |= 1 << pin; + } + } + else /* if (TCA64_LEVEL_SENSITIVE(priv, pin)) */ + { + /* Level triggered. Set intstat if in match level type. */ + + if (((input & 1) != 0 && TCA64_LEVEL_HIGH(priv, pin)) || + ((input & 1) == 0 && TCA64_LEVEL_LOW(priv, pin))) + { + priv->intstat |= 1 << pin; + } + } + + diff >>= 1; + input >>= 1; + } + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: tc64_update_registers + * + * Description: + * Read all pin states and update pending interrupts. + * + * Input Parameters: + * dev - Device-specific state data + * pins - The list of pin indexes to alter in this call + * val - The list of pin levels. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +#ifdef CONFIG_TCA64XX_INT_ENABLE +static void tca64_register_update(FAR struct tca64_dev_s *priv) +{ + ioe_pinset_t pinset; + uint8_t regaddr; + uint8_t ngpios; + uint8_t nregs; + int ret; + + /* Read the input register for pin 0 through the number of supported pins. + * + * The Input Port Register reflects the incoming logic levels of the pins, + * regardless of whether the pin is defined as an input or an output by + * the Configuration Register. They act only on read operation. + */ + + ngpios = tca64_ngpios(priv); + nregs = (ngpios + 7) >> 3; + pinset = 0; + regaddr = tca64_input_reg(priv, 0); + + ret = tca64_getreg(priv, regaddr, (FAR uint8_t *)&pinset, nregs); + if (ret < 0) + { + gpioerr("ERROR: Failed to read input %u registers at %u: %d\n", + nregs, regaddr, ret); + return; + } + + /* Update the input status with the 32 bits read from the expander */ + + tca64_int_update(priv, pinset, ~0); +} +#endif + +/**************************************************************************** + * Name: tca64_irqworker + * + * Description: + * Handle GPIO interrupt events (this function actually executes in the + * context of the worker thread). + * + ****************************************************************************/ + +#ifdef CONFIG_TCA64XX_INT_ENABLE +static void tca64_irqworker(void *arg) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)arg; + ioe_pinset_t pinset; + uint8_t regaddr; + uint8_t ngpios; + uint8_t nregs; + int ret; + int i; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + /* Read the input register for pin 0 through the number of supported pins. + * + * The Input Port Register reflects the incoming logic levels of the pins, + * regardless of whether the pin is defined as an input or an output by + * the Configuration Register. They act only on read operation. + */ + + ngpios = tca64_ngpios(priv); + nregs = (ngpios + 7) >> 3; + pinset = 0; + regaddr = tca64_input_reg(priv, 0); + + ret = tca64_getreg(priv, regaddr, (FAR uint8_t *)&pinset, nregs); + if (ret < 0) + { + gpioerr("ERROR: Failed to read input %u registers at %u: %d\n", + nregs, regaddr, ret); + return; + } + + /* Update the input status with the 32 bits read from the expander */ + + tca64_int_update(priv, pinset, ~0); + + /* Perform pin interrupt callbacks */ + + for (i = 0; i < CONFIG_TCA64XX_INT_NCALLBACKS; i++) + { + /* Is this entry valid (i.e., callback attached)? If so, did andy of + * the requested pin interrupts occur? + */ + + if (priv->cb[i].cbfunc != NULL) + { + /* Did any of the requested pin interrupts occur? */ + + ioe_pinset_t match = priv->intstat & priv->cb[i].pinset; + if (match != 0) + { + /* Yes.. perform the callback */ + + (void)priv->cb[i].cbfunc(&priv->dev, match); + } + } + } + + priv->intstat = 0; + +#ifdef CONFIG_TCA64XX_INT_POLL + /* Check for pending interrupts */ + + tca64_register_update(priv); + + /* Re-start the poll timer */ + + sched_lock(); + ret = wd_start(priv->wdog, TCA64XX_POLLDELAY, (wdentry_t)tca64_poll_expiry, + 1, (wdparm_t)priv); + if (ret < 0) + { + gpioerr("ERROR: Failed to start poll timer\n"); + } +#endif + + /* Re-enable interrupts */ + + priv->config->enable(priv->config, true); + +#ifdef CONFIG_TCA64XX_INT_POLL + sched_unlock(); +#endif +} +#endif + +/**************************************************************************** + * Name: tca64_interrupt + * + * Description: + * Handle GPIO interrupt events (this function executes in the + * context of the interrupt). + * + ****************************************************************************/ + +#ifdef CONFIG_TCA64XX_INT_ENABLE +static void tca64_interrupt(FAR void *arg) +{ + FAR struct tca64_dev_s *priv = (FAR struct tca64_dev_s *)arg; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + /* Defer interrupt processing to the worker thread. This is not only + * much kinder in the use of system resources but is probably necessary + * to access the I/O expander device. + * + * Notice that further GPIO interrupts are disabled until the work is + * actually performed. This is to prevent overrun of the worker thread. + * Interrupts are re-enabled in tca64_irqworker() when the work is + * completed. + */ + + if (work_available(&priv->work)) + { +#ifdef CONFIG_TCA64XX_INT_POLL + /* Cancel the poll timer */ + + (void)wd_cancel(priv->wdog); +#endif + + /* Disable interrupts */ + + priv->config->enable(priv->config, false); + + /* Schedule interrupt related work on the high priority worker thread. */ + + work_queue(HPWORK, &priv->work, tca64_irqworker, + (FAR void *)priv, 0); + } +} +#endif + +/**************************************************************************** + * Name: tca64_poll_expiry + * + * Description: + * The poll timer has expired; check for missed interrupts + * + * Input Parameters: + * Standard wdog expiration arguments. + * + ****************************************************************************/ + +#if defined(CONFIG_TCA64XX_INT_ENABLE) && defined(CONFIG_TCA64XX_INT_POLL) +static void tca64_poll_expiry(int argc, wdparm_t arg1, ...) +{ + FAR struct tca64_dev_s *priv; + + DEBUGASSERT(argc == 1); + priv = (FAR struct tca64_dev_s *)arg1; + DEBUGASSERT(priv != NULL && priv->config != NULL); + + /* Defer interrupt processing to the worker thread. This is not only + * much kinder in the use of system resources but is probably necessary + * to access the I/O expander device. + * + * Notice that further GPIO interrupts are disabled until the work is + * actually performed. This is to prevent overrun of the worker thread. + * Interrupts are re-enabled in tca64_irqworker() when the work is + * completed. + */ + + if (work_available(&priv->work)) + { + /* Disable interrupts */ + + priv->config->enable(priv->config, false); + + /* Schedule interrupt related work on the high priority worker thread. */ + + work_queue(HPWORK, &priv->work, tca64_irqworker, + (FAR void *)priv, 0); + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tca64_initialize + * + * Description: + * Instantiate and configure the TCA64xx device driver to use the provided + * I2C device instance. + * + * Input Parameters: + * i2c - An I2C driver instance + * minor - The device i2c address + * config - Persistent board configuration data + * + * Returned Value: + * an ioexpander_dev_s instance on success, NULL on failure. + * + ****************************************************************************/ + +FAR struct ioexpander_dev_s *tca64_initialize(FAR struct i2c_master_s *i2c, + FAR struct tca64_config_s *config) +{ + FAR struct tca64_dev_s *priv; + int ret; + +#ifdef CONFIG_TCA64XX_MULTIPLE + /* Allocate the device state structure */ + + priv = (FAR struct tca64_dev_s *)kmm_zalloc(sizeof(struct tca64_dev_s)); + if (!priv) + { + gpioerr("ERROR: Failed to allocate driver instance\n"); + return NULL; + } +#else + /* Use the one-and-only I/O Expander driver instance */ + + priv = &g_tca64; +#endif + + /* Initialize the device state structure */ + + priv->dev.ops = &g_tca64_ops; + priv->i2c = i2c; + priv->config = config; + +#ifdef CONFIG_TCA64XX_INT_ENABLE +#ifdef CONFIG_TCA64XX_INT_POLL + /* Set up a timer to poll for missed interrupts */ + + priv->wdog = wd_create(); + DEBUGASSERT(priv->wdog != NULL); + + ret = wd_start(priv->wdog, TCA64XX_POLLDELAY, (wdentry_t)tca64_poll_expiry, + 1, (wdparm_t)priv); + if (ret < 0) + { + gpioerr("ERROR: Failed to start poll timer\n"); + } +#endif + + /* Attach the I/O expander interrupt handler and enable interrupts */ + + priv->config->attach(config, tca64_interrupt, priv); + priv->config->enable(config, true); +#endif + + sem_init(&priv->exclsem, 0, 1); + return &priv->dev; +} + +#endif /* CONFIG_IOEXPANDER_TCA64XX */ diff --git a/drivers/ioexpander/tca64xx.h b/drivers/ioexpander/tca64xx.h new file mode 100644 index 0000000000..b1dd69118b --- /dev/null +++ b/drivers/ioexpander/tca64xx.h @@ -0,0 +1,267 @@ +/******************************************************************************************** + * drivers/ioexpander/tca64.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Sebastien Lorquet + * + * References: + * "16-bit I2C-bus and SMBus I/O port with interrupt product datasheet", + * Rev. 08 - 22 October 2009, NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __DRIVERS_IOEXPANDER_TCA64XX_H +#define __DRIVERS_IOEXPANDER_TCA64XX_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#if defined(CONFIG_IOEXPANDER) && defined(CONFIG_IOEXPANDER_TCA64XX) + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Configuration ****************************************************************************/ +/* Prerequisites: + * CONFIG_I2C + * I2C support is required + * CONFIG_IOEXPANDER + * Enables I/O expander support + * + * Other settings that effect the driver: CONFIG_DISABLE_POLL + * + * CONFIG_IOEXPANDER_TCA64XX + * Enables support for the TCA64XX driver (Needs CONFIG_INPUT) + * CONFIG_TCA64XX_MULTIPLE + * Can be defined to support multiple TCA64XX devices on board. + * CONFIG_TCA64XX_INT_NCALLBACKS + * Maximum number of supported pin interrupt callbacks. + * CONFIG_TCA64XX_INT_POLL + * Enables a poll for missed interrupts + * CONFIG_TCA64XX_INT_POLLDELAY + * If CONFIG_TCA64XX_INT_POLL=y, then this is the delay in microseconds + * between polls for missed interrupts. + */ + +#ifndef CONFIG_I2C +# error "CONFIG_I2C is required by TCA64XX" +#endif + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +# ifndef CONFIG_TCA64XX_INT_NCALLBACKS +# define CONFIG_TCA64XX_INT_NCALLBACKS 4 +# endif +#endif + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +# ifndef CONFIG_SCHED_WORKQUEUE +# error Work queue support required. CONFIG_SCHED_WORKQUEUE must be selected. +# endif +#endif + +#ifndef CONFIG_TCA64XX_INT_POLLDELAY +# define CONFIG_TCA64XX_INT_POLLDELAY 500000 +#endif + +/* TCA64XX Definitions **********************************************************************/ + +/* I2C frequency */ + +#define TCA64XX_I2C_MAXFREQUENCY 400000 /* 400KHz */ + +/* TCA64XX Parts ****************************************************************************/ + +#define TCA6408_INPUT_REG 0x00 +#define TCA6408_OUTPUT_REG 0x01 +#define TCA6408_POLARITY_REG 0x02 +#define TCA6408_CONFIG_REG 0x03 + +#define TCA6408_NR_GPIOS 8 + +#define TCA6416_INPUT0_REG 0x00 +#define TCA6416_INPUT1_REG 0x01 +#define TCA6416_OUTPUT0_REG 0x02 +#define TCA6416_OUTPUT1_REG 0x03 +#define TCA6416_POLARITY0_REG 0x04 +#define TCA6416_POLARITY1_REG 0x05 +#define TCA6416_CONFIG0_REG 0x06 +#define TCA6416_CONFIG1_REG 0x07 + +#define TCA6416_NR_GPIOS 16 + +#define TCA6424_INPUT0_REG 0x00 +#define TCA6424_INPUT1_REG 0x01 +#define TCA6424_INPUT2_REG 0x02 +#define TCA6424_OUTPUT0_REG 0x04 +#define TCA6424_OUTPUT1_REG 0x05 +#define TCA6424_OUTPUT2_REG 0x06 +#define TCA6424_POLARITY0_REG 0x08 +#define TCA6424_POLARITY1_REG 0x09 +#define TCA6424_POLARITY2_REG 0x0A +#define TCA6424_CONFIG0_REG 0x0C +#define TCA6424_CONFIG1_REG 0x0D +#define TCA6424_CONFIG2_REG 0x0E + +#define TCA6424_NR_GPIOS 24 + +#define TCA64XX_NR_GPIO_MAX TCA6424_NR_GPIOS + +/* 1us (datasheet: reset pulse duration (Tw) is 4ns */ + +#define TCA64XX_TW 1 + +/* 1us (datasheet: time to reset (Treset) is 600ns */ + +#define TCA64XX_TRESET 1 + +#define TCA64XX_IRQ_TYPE_EDGE_BOTH 0x00000000 +#define TCA64XX_IRQ_TYPE_EDGE_RISING 0x00000001 +#define TCA64XX_IRQ_TYPE_EDGE_FALLING 0x00000002 +#define TCA64XX_IRQ_TYPE_LEVEL_HIGH 0x00000001 +#define TCA64XX_IRQ_TYPE_LEVEL_LOW 0x00000002 + +#define TCA64XX_IRQ_TYPE_EDGE 0x00000000 +#define TCA64XX_IRQ_TYPE_LEVEL 0x00000001 + +#define tca64xx_irq_type_is_level(handle, gpio) \ + (tca64xx_get_gpio_triggering_type(handle, gpio) == TCA64XX_IRQ_TYPE_LEVEL) +#define tca64xx_irq_type_is_edge(handle, gpio) \ + (tca64xx_get_gpio_triggering_type(handle, gpio) == TCA64XX_IRQ_TYPE_EDGE) +#define tca64xx_irq_edge_trigger_is_both(handle, gpio) \ + (tca64xx_get_gpio_triggering_level(handle, gpio) == \ + TCA64XX_IRQ_TYPE_EDGE_BOTH) +#define tca64xx_irq_edge_trigger_is_falling(handle, gpio) \ + (tca64xx_get_gpio_triggering_level(handle, gpio) == \ + TCA64XX_IRQ_TYPE_EDGE_FALLING) +#define tca64xx_irq_edge_trigger_is_rising(handle, gpio) \ + (tca64xx_get_gpio_triggering_level(handle, gpio) == \ + TCA64XX_IRQ_TYPE_EDGE_RISING) +#define tca64xx_irq_level_trigger_is_low(handle, gpio) \ + (tca64xx_get_gpio_triggering_level(handle, gpio) == \ + TCA64XX_IRQ_TYPE_LEVEL_LOW) +#define tca64xx_irq_level_trigger_is_high(handle, gpio) \ + (tca64xx_get_gpio_triggering_level(handle, gpio) == \ + TCA64XX_IRQ_TYPE_LEVEL_HIGH) + +#define WORKER_DEFPRIO 50 +#define WORKER_STACKSIZE 1024 + +#define TCA64XX_POLLDELAY (CONFIG_TCA64XX_INT_POLLDELAY / USEC_PER_TICK) + +#define TCA64_LEVEL_SENSITIVE(d,p) \ + (((d)->trigger & (1 << (p))) == 0) +#define TCA64_LEVEL_HIGH(d,p) \ + (((d)->level[0] & (1 << (p))) != 0) +#define TCA64_LEVEL_LOW(d,p) \ + (((d)->level[1] & (1 << (p))) != 0) + +#define TCA64_EDGE_SENSITIVE(d,p) \ + (((d)->trigger & (1 << (p))) != 0) +#define TCA64_EDGE_RISING(d,p) \ + (((d)->level[0] & (1 << (p))) != 0) +#define TCA64_EDGE_FALLING(d,p) \ + (((d)->level[1] & (1 << (p))) != 0) +#define TCA64_EDGE_BOTH(d,p) \ + (TCA64_LEVEL_RISING(d,p) && TCA64_LEVEL_FALLING(d,p)) + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/* This structure represents the configuration of one part */ + +struct tca64_part_s +{ + uint8_t tp_id; /* Part ID (see enum tca64xx_part_e) */ + uint8_t tp_ngpios; /* Number of supported GPIOs */ + uint8_t tp_input; /* Address of first input register */ + uint8_t tp_output; /* Address of first output register */ + uint8_t tp_polarity; /* Address of first polarity register */ + uint8_t tp_config; /* Address of first configuration register */ +}; + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +/* This type represents on registered pin interrupt callback */ + +struct tca64_callback_s +{ + ioe_pinset_t pinset; /* Set of pin interrupts that will generate + * the callback. */ + ioe_callback_t cbfunc; /* The saved callback function pointer */ +}; +#endif + +/* This structure represents the state of the TCA64XX driver */ + +struct tca64_dev_s +{ + struct ioexpander_dev_s dev; /* Nested structure to allow casting as public gpio + * expander. */ + FAR struct tca64_config_s *config; /* Board configuration data */ + FAR struct i2c_master_s *i2c; /* Saved I2C driver instance */ + uint8_t part; /* TCA64xx part ID (see enum tca64xx_part_e) */ + uint8_t addr; /* TCA64xx I2C address */ + sem_t exclsem; /* Mutual exclusion */ + +#ifdef CONFIG_TCA64XX_INT_POLL + WDOG_ID wdog; /* Timer used to poll for missed interrupts */ +#endif + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE + ioe_pinset_t input; /* Last input registeres */ + ioe_pinset_t intstat; /* Pending interrupts */ + ioe_pinset_t trigger; /* Bit encoded: 0=level 1=edge */ + ioe_pinset_t level[2]; /* Bit encoded: 01=high/rising, 10 low/falling, 11 both */ + struct work_s work; /* Supports the interrupt handling "bottom half" */ + + /* Saved callback information for each I/O expander client */ + + struct tca64_callback_s cb[CONFIG_TCA64XX_INT_NCALLBACKS]; +#endif +}; + +#endif /* CONFIG_IOEXPANDER && CONFIG_IOEXPANDER_TCA64XX */ +#endif /* __DRIVERS_IOEXPANDER_TCA64XX_H */ diff --git a/include/nuttx/ioexpander/tca64xx.h b/include/nuttx/ioexpander/tca64xx.h new file mode 100644 index 0000000000..84ef480f01 --- /dev/null +++ b/include/nuttx/ioexpander/tca64xx.h @@ -0,0 +1,138 @@ +/**************************************************************************** + * include/nuttx/ioexpander/tca64xx.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * This header file derives, in part, from the Project Ara TCA64xx driver + * which has this copyright: + * + * Copyright (c) 2014-2015 Google Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef _TSB_TCA64XX_H_ +#define _TSB_TCA64XX_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Unused IO line for irq, reset. */ + +#define TCA64XX_IO_UNUSED (1 << 31) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Identifies supported TCA64xx parts (as well as the number of supported + * parts). + */ + +enum tca64xx_part_e +{ + TCA6408_PART = 0, + TCA6416_PART, + TCA6424_PART, + TCA64_NPARTS +}; + +#ifdef CONFIG_TCA64XX_INT_ENABLE +/* This is the type of the TCA64xx interrupt handler */ + +typedef CODE void (*tca64_handler_t)(FAR void *arg); +#endif + +/* A reference to a structure of this type must be passed to the TCA64xx + * driver when the driver is instantiated. This structure provides + * information about the configuration of the TCA64xx and provides some + * board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied by + * the driver and is presumed to persist while the driver is active. The + * memory must be writeable because, under certain circumstances, the driver + * may modify the frequency. + */ + +struct tca64_config_s +{ + /* Device characterization */ + + uint8_t address; /* 7-bit I2C address (only bits 0-6 used) */ + uint8_t part; /* See enum tca64xx_part_e */ + uint32_t frequency; /* I2C or SPI frequency */ + +#ifdef CONFIG_TCA64XX_INT_ENABLE + /* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the TCA64xx driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the TCA64xx interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + */ + + CODE int (*attach)(FAR struct tca64_config_s *state, + tca64_handler_t handler, FAR void *arg); + CODE void (*enable)(FAR struct tca64_config_s *state, bool enable); +#endif +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: tca64_initialize + * + * Description: + * Instantiate and configure the TCA64xx device driver to use the provided + * I2C device instance. + * + * Input Parameters: + * i2c - An I2C driver instance + * minor - The device i2c address + * config - Persistent board configuration data + * + * Returned Value: + * an ioexpander_dev_s instance on success, NULL on failure. + * + ****************************************************************************/ + +struct i2c_master_s; +FAR struct ioexpander_dev_s *tca64_initialize(FAR struct i2c_master_s *i2c, + FAR struct tca64_config_s *config); + +#endif