esp32[c3|h2|c6]: Bugfixes for filesystem errors

arch/risc-v/src/common/espressif/Kconfig

@@ -476,6 +476,14 @@ config ESPRESSIF_FLASH_FREQ_20M
 
 endchoice # ESPRESSIF_FLASH_FREQ
 
+config ESPRESSIF_SPI_FLASH_USE_ROM_CODE
+	bool "Use SPI flash driver in ROM"
+	default n
+	depends on ESPRESSIF_ESP32C3
+	---help---
+		Use functions in ROM for SPI flash driver instead of
+		source code.
+
 config ESPRESSIF_SPI_FLASH_USE_32BIT_ADDRESS
 	bool "SPI flash uses 32-bit address"
 	default n

arch/risc-v/src/common/espressif/esp_spiflash.c

@@ -49,6 +49,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#ifndef CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE
 /* SPI buffer size */
 
 #  define SPI_BUFFER_WORDS          (16)
@@ -124,7 +125,8 @@
  * Private Types
  ****************************************************************************/
 
-spi_mem_dev_t *dev;
+spi_mem_dev_t *dev = spimem_flash_ll_get_hw(SPI1_HOST);
+#endif /* CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE */
 
 /****************************************************************************
  * Private Functions Declaration
@@ -132,6 +134,10 @@ spi_mem_dev_t *dev;
 
 static void spiflash_start(void);
 static void spiflash_end(void);
+#ifndef CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE
+extern bool spi_flash_check_and_flush_cache(size_t start_addr,
+                                            size_t length);
+#endif /* CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE */
 
 /****************************************************************************
  * Private Data
@@ -156,7 +162,7 @@ static volatile bool s_sched_suspended[CONFIG_ESPRESSIF_NUM_CPUS];
  ****************************************************************************/
 
 /****************************************************************************
- * Name: spiflash_opstart
+ * Name: spiflash_start
  *
  * Description:
  *   Prepare for an SPIFLASH operation.
@@ -189,7 +195,7 @@ static IRAM_ATTR void spiflash_start(void)
 }
 
 /****************************************************************************
- * Name: spiflash_opdone
+ * Name: spiflash_end
  *
  * Description:
  *   Undo all the steps of opstart.
@@ -205,12 +211,16 @@ static IRAM_ATTR void spiflash_start(void)
 static IRAM_ATTR void spiflash_end(void)
 {
   extern void cache_resume_icache(uint32_t);
+  extern void cache_invalidate_icache_all(void);
+
   int cpu;
   irqstate_t flags;
 
   flags = enter_critical_section();
 
   cpu = up_cpu_index();
+
+  cache_invalidate_icache_all();
   cache_resume_icache(s_flash_op_cache_state[cpu] >> 16);
 
   esp_intr_noniram_enable();
@@ -242,6 +252,7 @@ static IRAM_ATTR void spiflash_end(void)
  *
  ****************************************************************************/
 
+#ifndef CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE
 static IRAM_ATTR void esp_spi_trans(uint32_t command,
                                     uint32_t command_bits,
                                     uint32_t address,
@@ -332,7 +343,17 @@ static IRAM_ATTR void esp_spi_trans(uint32_t command,
 
 static IRAM_ATTR void wait_flash_idle(void)
 {
-  while (!spi_flash_ll_host_idle(dev));
+  uint32_t status;
+
+  do
+    {
+      READ_SR1_FROM_FLASH(FLASH_CMD_RDSR, &status);
+      if ((status & FLASH_SR1_BUSY) == 0)
+        {
+          break;
+        }
+    }
+  while (1);
 }
 
 /****************************************************************************
@@ -509,6 +530,7 @@ IRAM_ATTR int spi_flash_erase_range(uint32_t start_address, uint32_t size)
 
   wait_flash_idle();
   disable_flash_write();
+  spi_flash_check_and_flush_cache(start_address, size);
 
   spiflash_end();
 
@@ -561,11 +583,13 @@ IRAM_ATTR int spi_flash_write(uint32_t dest_addr,
 
   wait_flash_idle();
   disable_flash_write();
+  spi_flash_check_and_flush_cache(dest_addr, size);
 
   spiflash_end();
 
   return ret;
 }
+#endif /* CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE */
 
 /****************************************************************************
  * Name: esp_spiflash_init
@@ -588,7 +612,6 @@ int esp_spiflash_init(void)
   nxmutex_init(&s_flash_op_mutex);
 
   spi_flash_guard_set(&g_spi_flash_guard_funcs);
-  dev = spimem_flash_ll_get_hw(SPI1_HOST);
 
   return OK;
 }

boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld

@@ -23,6 +23,7 @@ cache_ibus_mmu_set = Cache_Ibus_MMU_Set;
 cache_invalidate_icache_all = Cache_Invalidate_ICache_All;
 cache_resume_icache = Cache_Resume_ICache;
 cache_suspend_icache = Cache_Suspend_ICache;
+cache_invalidate_icache_all = Cache_Invalidate_ICache_All;
 
 #ifdef CONFIG_ESPRESSIF_BLE
 

boards/risc-v/esp32c3/common/scripts/esp32c3_flat_memory.ld

@@ -98,7 +98,7 @@ MEMORY
    * constraint that (paddr % 64KB == vaddr % 64KB).
    */
 
-  irom0_0_seg (RX) :      org = 0x42000020, len = FLASH_SIZE - 0x20
+  irom0_0_seg (RX) :      org = 0x42000000, len = FLASH_SIZE
 #endif
 
   /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */
@@ -131,7 +131,7 @@ MEMORY
    * constraint that (paddr % 64KB == vaddr % 64KB).
    */
 
-  drom0_0_seg (R) :      org = 0x3c000020, len = FLASH_SIZE - 0x20
+  drom0_0_seg (R) :      org = 0x3c000000, len = FLASH_SIZE
 #endif
 
   /* RTC fast memory (executable). Persists over deep sleep. */

boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld

@@ -20,6 +20,7 @@
 
 cache_resume_icache = Cache_Resume_ICache;
 cache_suspend_icache = Cache_Suspend_ICache;
+cache_invalidate_icache_all = Cache_Invalidate_ICache_All;
 
 #ifdef CONFIG_ESPRESSIF_BLE
 

boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld

@@ -53,10 +53,8 @@
 MEMORY
 {
 #ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
-  /* The 0x20 offset is a convenience for the app binary image generation */
+  ROM (R) :              org = ORIGIN(ROM),
-
+                         len = IDRAM0_2_SEG_SIZE
-  ROM (R) :              org = 0x20,
-                         len = IDRAM0_2_SEG_SIZE - 0x20
 #endif
 
   /* Below values assume the flash cache is on, and have the blocks this
@@ -76,7 +74,7 @@ MEMORY
    * constraint that (paddr % 64KB == vaddr % 64KB).
    */
 
-  irom_seg    (RX) :      org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+  irom_seg    (RX) :      org = 0x42000000, len = IDRAM0_2_SEG_SIZE
 
   /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
    * Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -94,7 +92,7 @@ MEMORY
    * constraint that (paddr % 64KB == vaddr % 64KB).
    */
 
-  drom_seg    (R) :       org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+  drom_seg    (R) :       org = 0x42000000, len = IDRAM0_2_SEG_SIZE
 
   /* RTC fast memory (executable). Persists over deep sleep. */
 

boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld

@@ -20,6 +20,7 @@
 
 cache_resume_icache = Cache_Resume_ICache;
 cache_suspend_icache = Cache_Suspend_ICache;
+cache_invalidate_icache_all = Cache_Invalidate_ICache_All;
 
 #ifdef CONFIG_ESPRESSIF_BLE
 

boards/risc-v/esp32h2/common/scripts/esp32h2_flat_memory.ld

@@ -53,10 +53,8 @@
 MEMORY
 {
 #ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
-  /* The 0x20 offset is a convenience for the app binary image generation */
+  ROM (R) :              org = ORIGIN(ROM),
-
+                         len = IDRAM0_2_SEG_SIZE
-  ROM (R) :              org = 0x20,
-                         len = IDRAM0_2_SEG_SIZE - 0x20
 #endif
 
   /* Below values assume the flash cache is on, and have the blocks this
@@ -76,7 +74,7 @@ MEMORY
    * constraint that (paddr % 64KB == vaddr % 64KB).
    */
 
-  irom_seg    (RX) :      org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+  irom_seg    (RX) :      org = 0x42000000, len = IDRAM0_2_SEG_SIZE
 
   /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
    * Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -94,7 +92,7 @@ MEMORY
    * constraint that (paddr % 64KB == vaddr % 64KB).
    */
 
-  drom_seg    (R) :       org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
+  drom_seg    (R) :       org = 0x42000000, len = IDRAM0_2_SEG_SIZE
 
   /* RTC fast memory (executable). Persists over deep sleep. */