This fixes the basic OS test for the LPC1768
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2754 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
43b3c3fa8e
commit
c0e6c32b1a
@ -325,9 +325,9 @@ void lpc17_lowsetup(void)
|
||||
|
||||
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
|
||||
regval &= ~(SYSCON_PCLKSEL1_UART2_MASK|SYSCON_PCLKSEL1_UART3_SHIFT);
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
#if defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART2_SHIFT);
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
|
||||
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART3_SHIFT);
|
||||
#endif
|
||||
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
|
||||
@ -369,7 +369,7 @@ void lpc17_lowsetup(void)
|
||||
|
||||
putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC17_UART_FCR_OFFSET);
|
||||
|
||||
/* Set up the LCR and set DLAB=1*/
|
||||
/* Set up the LCR and set DLAB=1 */
|
||||
|
||||
putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+LPC17_UART_LCR_OFFSET);
|
||||
|
||||
@ -380,7 +380,7 @@ void lpc17_lowsetup(void)
|
||||
|
||||
/* Clear DLAB */
|
||||
|
||||
putreg32(CONSOLE_LCR_VALUE, LPC17_UART_LCR_OFFSET);
|
||||
putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC17_UART_LCR_OFFSET);
|
||||
|
||||
/* Configure the FIFOs */
|
||||
|
||||
|
||||
@ -71,7 +71,7 @@
|
||||
*/
|
||||
|
||||
#undef CONFIG_LPC17_MAINOSC
|
||||
#define CONFIG_LPC17_MAINOSC 1
|
||||
#define CONFIG_LPC17_MAINOSC 1
|
||||
#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN
|
||||
|
||||
/* Select the main oscillator and CCLK divider. The output of the divider is CCLK.
|
||||
@ -89,7 +89,7 @@
|
||||
*/
|
||||
|
||||
#undef CONFIG_LPC17_PLL0
|
||||
#define CONFIG_LPC17_PLL0 1
|
||||
#define CONFIG_LPC17_PLL0 1
|
||||
#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
|
||||
|
||||
#define BOARD_PLL0CFG_MSEL 20
|
||||
@ -100,7 +100,7 @@
|
||||
|
||||
/* PLL1 -- Not used. */
|
||||
|
||||
#undef CONFIG_LPC17_PLL0
|
||||
#undef CONFIG_LPC17_PLL1
|
||||
#define BOARD_PLL1CFG_MSEL 36
|
||||
#define BOARD_PLL1CFG_NSEL 1
|
||||
#define BOARD_PLL1CFG_VALUE \
|
||||
|
||||
61
configs/nucleus2g/tools/olimex.cfg
Executable file
61
configs/nucleus2g/tools/olimex.cfg
Executable file
@ -0,0 +1,61 @@
|
||||
#daemon configuration
|
||||
telnet_port 4444
|
||||
gdb_port 3333
|
||||
|
||||
#interface
|
||||
interface ft2232
|
||||
ft2232_device_desc "Olimex OpenOCD JTAG A"
|
||||
ft2232_layout "olimex-jtag"
|
||||
ft2232_vid_pid 0x15BA 0x0003
|
||||
|
||||
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME lpc1768
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID ] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
#delays on reset lines
|
||||
jtag_nsrst_delay 200
|
||||
jtag_ntrst_delay 200
|
||||
|
||||
# LPC2000 & LPC1700 -> SRST causes TRST
|
||||
reset_config trst_and_srst srst_pulls_trst
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
|
||||
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
|
||||
|
||||
# REVISIT is there any good reason to have this reset-init event handler??
|
||||
# Normally they should set up (board-specific) clocking then probe the flash...
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# Force NVIC.VTOR to point to flash at 0 ...
|
||||
# WHY? This is it's reset value; we run right after reset!!
|
||||
mwb 0xE000ED08 0x00
|
||||
}
|
||||
|
||||
# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
|
||||
# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
|
||||
|
||||
# 4MHz / 6 = 666kHz, so use 500
|
||||
jtag_khz 100
|
||||
42
configs/nucleus2g/tools/oocd.sh
Executable file
42
configs/nucleus2g/tools/oocd.sh
Executable file
@ -0,0 +1,42 @@
|
||||
#!/bin/sh
|
||||
|
||||
TOPDIR=$1
|
||||
USAGE="$0 <TOPDIR> [-d]"
|
||||
if [ -z "${TOPDIR}" ]; then
|
||||
echo "Missing argument"
|
||||
echo $USAGE
|
||||
exit 1
|
||||
fi
|
||||
|
||||
OPENOCD_PATH="/cygdrive/c/OpenOCD/openocd-0.4.0/src"
|
||||
OPENOCD_EXE=openocd.exe
|
||||
OPENOCD_CFG="${TOPDIR}/configs/nucleus2g/tools/olimex.cfg"
|
||||
OPENOCD_ARGS="-f `cygpath -w ${OPENOCD_CFG}`"
|
||||
|
||||
if [ "X$2" = "X-d" ]; then
|
||||
OPENOCD_ARGS=$OPENOCD_ARGS" -d3"
|
||||
set -x
|
||||
fi
|
||||
|
||||
if [ ! -d ${OPENOCD_PATH} ]; then
|
||||
echo "OpenOCD path does not exist: ${OPENOCD_PATH}"
|
||||
exit 1
|
||||
fi
|
||||
if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then
|
||||
echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}"
|
||||
exit 1
|
||||
fi
|
||||
if [ ! -f ${OPENOCD_CFG} ]; then
|
||||
echo "OpenOCD config file does not exist: ${OPENOCD_CFG}"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
echo "Starting OpenOCD"
|
||||
${OPENOCD_PATH}/${OPENOCD_EXE} ${OPENOCD_ARGS} &
|
||||
echo "OpenOCD daemon started"
|
||||
ps -ef | grep openocd
|
||||
echo "In GDB: target remote localhost:3333"
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user