Add more nops after enabling MMU for Cortex-A8
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@ -505,14 +505,9 @@ __start:
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/* Then write the configured control register */
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mcr CP15_SCTLR(r0) /* Write control reg */
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/* Read the Main ID register. This will be available in R1 after
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* MMU trampoline (not currently used)
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*/
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mrc CP15_MIDR(r1) /* Read main id reg */
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mov r1, r1 /* Null-avoiding nop */
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mov r1, r1 /* Null-avoiding nop */
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.rept 12 /* Cortex A8 wants lots of NOPs here */
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nop
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.endr
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/* And "jump" to .Lvstart in the newly mapped virtual address space */
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/arm_pghead.S
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -491,14 +491,9 @@ __start:
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/* Then write the configured control register */
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mcr CP15_SCTLR(r0) /* Write control reg */
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/* Read the Main ID register. This will be available in R1 after
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* MMU trampoline (not currently used)
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*/
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mrc CP15_MIDR(r1) /* Read main id reg */
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mov r1, r1 /* Null-avoiding nop */
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mov r1, r1 /* Null-avoiding nop */
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.rept 12 /* Cortex A8 wants lots of NOPs here */
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nop
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.endr
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/* And "jump" to .Lvstart in the newly mapped virtual address space */
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