Xtensa: Add initial CPU0 start-up logic
This commit is contained in:
Gregory Nutt
parent
0591b67c15
commit
c1334048c5
@ -13,6 +13,7 @@ config ARCH_CHIP_ESP32
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bool "Expressif ESP32"
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select ARCH_FAMILY_LX6
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select XTENSA_HAVE_INTERRUPTS
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select ARCH_HAVE_MULTICPU
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---help---
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The ESP32 is a dual-core system from Expressif with two Harvard
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architecture Xtensa LX6 CPUs. All embedded memory, external memory
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65
arch/xtensa/src/common/xtensa_attr.h
Normal file
65
arch/xtensa/src/common/xtensa_attr.h
Normal file
@ -0,0 +1,65 @@
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_irq.S
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*
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* Adapted from use in NuttX by:
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from logic originally provided by Espressif Systems:
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*
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* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H
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#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define ROMFN_ATTR
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/* Normally, the linker script will put all code and rodata in flash,
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* and all variables in shared RAM. These macros can be used to redirect
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* particular functions/variables to other memory regions.
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*/
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/* Forces code into IRAM instead of flash */
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#define IRAM_ATTR __attribute__((section(".iram1")))
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/* Forces data into DRAM instead of flash */
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#define DRAM_ATTR __attribute__((section(".dram1")))
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/* Forces code into RTC fast memory */
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#define RTC_IRAM_ATTR __attribute__((section(".rtc.text")))
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/* Forces data into RTC slow memory
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* Any variable marked with this attribute will keep its value
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* during a deep sleep / wake cycle. */
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#define RTC_DATA_ATTR __attribute__((section(".rtc.data")))
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/* Forces read-only data into RTC slow memory
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* Makes constant data available to RTC wake stubs.
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*/
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#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata")))
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#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H */
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@ -110,7 +110,7 @@ void up_initial_state(struct tcb_s *tcb)
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xcp->regs[REG_VPRI] = 0xffffffff;
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#endif
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# warning REVISIT co-processor support
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#warning REVISIT co-processor support
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#if 0 /* REVISIT */
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#if CONFIG_XTENSA_NCOPROCESSORS > 0
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/* Init the coprocessor save area (see xtensa_context.h)
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3854
arch/xtensa/src/esp32/chip/xtensa_dport.h
Normal file
3854
arch/xtensa/src/esp32/chip/xtensa_dport.h
Normal file
File diff suppressed because it is too large
Load Diff
2009
arch/xtensa/src/esp32/chip/xtensa_rtccntl.h
Normal file
2009
arch/xtensa/src/esp32/chip/xtensa_rtccntl.h
Normal file
File diff suppressed because it is too large
Load Diff
356
arch/xtensa/src/esp32/chip/xtensa_soc.h
Normal file
356
arch/xtensa/src/esp32/chip/xtensa_soc.h
Normal file
@ -0,0 +1,356 @@
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_att.h
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*
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* Adapted from use in NuttX by:
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from logic originally provided by Espressif Systems:
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* Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License./*
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H
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#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Bits */
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#define BIT31 0x80000000
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#define BIT30 0x40000000
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#define BIT29 0x20000000
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#define BIT28 0x10000000
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#define BIT27 0x08000000
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#define BIT26 0x04000000
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#define BIT25 0x02000000
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#define BIT24 0x01000000
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#define BIT23 0x00800000
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#define BIT22 0x00400000
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#define BIT21 0x00200000
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#define BIT20 0x00100000
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#define BIT19 0x00080000
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#define BIT18 0x00040000
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#define BIT17 0x00020000
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#define BIT16 0x00010000
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#define BIT15 0x00008000
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#define BIT14 0x00004000
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#define BIT13 0x00002000
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#define BIT12 0x00001000
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#define BIT11 0x00000800
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#define BIT10 0x00000400
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#define BIT9 0x00000200
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#define BIT8 0x00000100
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#define BIT7 0x00000080
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#define BIT6 0x00000040
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#define BIT5 0x00000020
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#define BIT4 0x00000010
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#define BIT3 0x00000008
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#define BIT2 0x00000004
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#define BIT1 0x00000002
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#define BIT0 0x00000001
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#define PRO_CPU_NUM (0)
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#define APP_CPU_NUM (1)
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/* Registers Operation */
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#define BIT(nr) (1UL << (nr))
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/* Write value to register */
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#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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/* Read value from register */
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#define REG_READ(_r) (*(volatile uint32_t *)(_r))
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/* Get bit or get bits from register */
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#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
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/* Set bit or set bits to register */
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#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
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/* Clear bit or clear bits of register */
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#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
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/* Set bits of register controlled by mask */
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#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
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/* Get field from register, used when _f is not left shifted by _f##_S */
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#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f))
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/* Set field to register, used when _f is not left shifted by _f##_S */
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#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
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/* Set field value from a variable, used when _f is not left shifted by _f##_S */
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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/* Get field value from a variable, used when _f is left shifted by _f##_S */
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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/* Set field value to a variable, used when _f is not left shifted by _f##_S */
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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/* Set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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/* Generate a value from a field value, used when _f is not left shifted by _f##_S */
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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/* Generate a value from a field value, used when _f is left shifted by _f##_S */
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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/* Read value from register */
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#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
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/* Write value to register */
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#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
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/* Clear bits of register controlled by mask */
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#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
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/* Set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
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/* Get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
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/* Get bits of register controlled by highest bit and lowest bit */
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
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/* Set bits of register controlled by mask and shift */
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
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/* Get field of register */
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#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
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/* Periheral Clock */
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#define APB_CLK_FREQ_ROM 26*1000000
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define CPU_CLK_FREQ APB_CLK_FREQ
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#define APB_CLK_FREQ 80*1000000 /* Unit: Hz */
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define WDT_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (80000000>>4) /* 80MHz divided by 16 */
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#define SPI_CLK_DIV 4
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#define TICKS_PER_US_ROM 26 /* CPU is 80MHz */
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#define DR_REG_DPORT_BASE 0x3ff00000
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#define DR_REG_UART_BASE 0x3ff40000
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#define DR_REG_SPI1_BASE 0x3ff42000
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#define DR_REG_SPI0_BASE 0x3ff43000
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#define DR_REG_GPIO_BASE 0x3ff44000
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#define DR_REG_GPIO_SD_BASE 0x3ff44f00
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#define DR_REG_FE2_BASE 0x3ff45000
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#define DR_REG_FE_BASE 0x3ff46000
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#define DR_REG_RTCCNTL_BASE 0x3ff48000
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#define DR_REG_RTCIO_BASE 0x3ff48400
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#define DR_REG_SARADC_BASE 0x3ff48800
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#define DR_REG_IO_MUX_BASE 0x3ff49000
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#define DR_REG_RTCMEM0_BASE 0x3ff61000
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#define DR_REG_RTCMEM1_BASE 0x3ff62000
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#define DR_REG_RTCMEM2_BASE 0x3ff63000
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#define DR_REG_HINF_BASE 0x3ff4B000
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#define DR_REG_UHCI1_BASE 0x3ff4C000
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#define DR_REG_I2S_BASE 0x3ff4F000
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#define DR_REG_UART1_BASE 0x3ff50000
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#define DR_REG_BT_BASE 0x3ff51000
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#define DR_REG_I2C_EXT_BASE 0x3ff53000
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#define DR_REG_UHCI0_BASE 0x3ff54000
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#define DR_REG_SLCHOST_BASE 0x3ff55000
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#define DR_REG_RMT_BASE 0x3ff56000
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#define DR_REG_PCNT_BASE 0x3ff57000
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#define DR_REG_SLC_BASE 0x3ff58000
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#define DR_REG_LEDC_BASE 0x3ff59000
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#define DR_REG_EFUSE_BASE 0x3ff5A000
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#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
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#define DR_REG_PWM_BASE 0x3ff5E000
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#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
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#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
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#define DR_REG_SPI2_BASE 0x3ff64000
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#define DR_REG_SPI3_BASE 0x3ff65000
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#define DR_REG_I2C1_EXT_BASE 0x3ff67000
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#define DR_REG_SDMMC_BASE 0x3ff68000
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#define DR_REG_EMAC_BASE 0x3ff69000
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#define DR_REG_PWM1_BASE 0x3ff6C000
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#define DR_REG_I2S1_BASE 0x3ff6D000
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#define DR_REG_UART2_BASE 0x3ff6E000
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#define DR_REG_PWM2_BASE 0x3ff6F000
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#define DR_REG_PWM3_BASE 0x3ff70000
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#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
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/* Interrupt hardware source table
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* This table is decided by hardware, don't touch this.
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*/
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#define ETS_WIFI_MAC_INTR_SOURCE 0 /* Interrupt of WiFi MAC, level */
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#define ETS_WIFI_MAC_NMI_SOURCE 1 /* Interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI */
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#define ETS_WIFI_BB_INTR_SOURCE 2 /* Interrupt of WiFi BB, level, we can do some calibartion */
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#define ETS_BT_MAC_INTR_SOURCE 3 /* will be cancelled */
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#define ETS_BT_BB_INTR_SOURCE 4 /* Interrupt of BT BB, level */
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#define ETS_BT_BB_NMI_SOURCE 5 /* Interrupt of BT BB, NMI, use if BB have bug to fix in NMI */
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#define ETS_RWBT_INTR_SOURCE 6 /* Interrupt of RWBT, level */
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#define ETS_RWBLE_INTR_SOURCE 7 /* Interrupt of RWBLE, level */
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#define ETS_RWBT_NMI_SOURCE 8 /* Interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI */
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#define ETS_RWBLE_NMI_SOURCE 9 /* Interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI */
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#define ETS_SLC0_INTR_SOURCE 10 /* Interrupt of SLC0, level */
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#define ETS_SLC1_INTR_SOURCE 11 /* Interrupt of SLC1, level */
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#define ETS_UHCI0_INTR_SOURCE 12 /* Interrupt of UHCI0, level */
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#define ETS_UHCI1_INTR_SOURCE 13 /* Interrupt of UHCI1, level */
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#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14 /* Interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission */
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#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15 /* Interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission */
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#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16 /* Interrupt of TIMER_GROUP0, WATCHDOG, level */
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#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17 /* Interrupt of TIMER_GROUP0, LACT, level */
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#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18 /* Interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission */
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#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19 /* Interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission */
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#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20 /* Interrupt of TIMER_GROUP1, WATCHDOG, level */
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#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21 /* Interrupt of TIMER_GROUP1, LACT, level */
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#define ETS_GPIO_INTR_SOURCE 22 /* Interrupt of GPIO, level */
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#define ETS_GPIO_NMI_SOURCE 23 /* Interrupt of GPIO, NMI */
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#define ETS_FROM_CPU_INTR0_SOURCE 24 /* Interrupt0 generated from a CPU, level */
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#define ETS_FROM_CPU_INTR1_SOURCE 25 /* Interrupt1 generated from a CPU, level */
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#define ETS_FROM_CPU_INTR2_SOURCE 26 /* Interrupt2 generated from a CPU, level */
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#define ETS_FROM_CPU_INTR3_SOURCE 27 /* Interrupt3 generated from a CPU, level */
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#define ETS_SPI0_INTR_SOURCE 28 /* Interrupt of SPI0, level, SPI0 is for Cache Access, do not use this */
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#define ETS_SPI1_INTR_SOURCE 29 /* Interrupt of SPI1, level, SPI1 is for flash read/write, do not use this */
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#define ETS_SPI2_INTR_SOURCE 30 /* Interrupt of SPI2, level */
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#define ETS_SPI3_INTR_SOURCE 31 /* Interrupt of SPI3, level */
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#define ETS_I2S0_INTR_SOURCE 32 /* Interrupt of I2S0, level */
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#define ETS_I2S1_INTR_SOURCE 33 /* Interrupt of I2S1, level */
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#define ETS_UART0_INTR_SOURCE 34 /* Interrupt of UART0, level */
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#define ETS_UART1_INTR_SOURCE 35 /* Interrupt of UART1, level */
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#define ETS_UART2_INTR_SOURCE 36 /* Interrupt of UART2, level */
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#define ETS_SDIO_HOST_INTR_SOURCE 37 /* Interrupt of SD/SDIO/MMC HOST, level */
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#define ETS_ETH_MAC_INTR_SOURCE 38 /* Interrupt of ethernet mac, level */
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#define ETS_PWM0_INTR_SOURCE 39 /* Interrupt of PWM0, level, Reserved */
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#define ETS_PWM1_INTR_SOURCE 40 /* Interrupt of PWM1, level, Reserved */
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#define ETS_PWM2_INTR_SOURCE 41 /* Interrupt of PWM2, level */
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#define ETS_PWM3_INTR_SOURCE 42 /* Interruot of PWM3, level */
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#define ETS_LEDC_INTR_SOURCE 43 /* Interrupt of LED PWM, level */
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#define ETS_EFUSE_INTR_SOURCE 44 /* Interrupt of efuse, level, not likely to use */
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#define ETS_CAN_INTR_SOURCE 45 /* Interrupt of can, level */
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#define ETS_RTC_CORE_INTR_SOURCE 46 /* Interrupt of rtc core, level, include rtc watchdog */
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#define ETS_RMT_INTR_SOURCE 47 /* Interrupt of remote controller, level */
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#define ETS_PCNT_INTR_SOURCE 48 /* Interrupt of pluse count, level */
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#define ETS_I2C_EXT0_INTR_SOURCE 49 /* Interrupt of I2C controller1, level */
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#define ETS_I2C_EXT1_INTR_SOURCE 50 /* Interrupt of I2C controller0, level */
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#define ETS_RSA_INTR_SOURCE 51 /* Interrupt of RSA accelerator, level */
|
||||
#define ETS_SPI1_DMA_INTR_SOURCE 52 /* Interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this */
|
||||
#define ETS_SPI2_DMA_INTR_SOURCE 53 /* Interrupt of SPI2 DMA, level */
|
||||
#define ETS_SPI3_DMA_INTR_SOURCE 54 /* Interrupt of SPI3 DMA, level */
|
||||
#define ETS_WDT_INTR_SOURCE 55 /* will be cancelled */
|
||||
#define ETS_TIMER1_INTR_SOURCE 56 /* will be cancelled */
|
||||
#define ETS_TIMER2_INTR_SOURCE 57 /* will be cancelled */
|
||||
#define ETS_TG0_T0_EDGE_INTR_SOURCE 58 /* Interrupt of TIMER_GROUP0, TIMER0, EDGE */
|
||||
#define ETS_TG0_T1_EDGE_INTR_SOURCE 59 /* Interrupt of TIMER_GROUP0, TIMER1, EDGE */
|
||||
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60 /* Interrupt of TIMER_GROUP0, WATCH DOG, EDGE */
|
||||
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61 /* Interrupt of TIMER_GROUP0, LACT, EDGE */
|
||||
#define ETS_TG1_T0_EDGE_INTR_SOURCE 62 /* Interrupt of TIMER_GROUP1, TIMER0, EDGE */
|
||||
#define ETS_TG1_T1_EDGE_INTR_SOURCE 63 /* Interrupt of TIMER_GROUP1, TIMER1, EDGE */
|
||||
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64 /* Interrupt of TIMER_GROUP1, WATCHDOG, EDGE */
|
||||
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65 /* Interrupt of TIMER_GROUP0, LACT, EDGE */
|
||||
#define ETS_MMU_IA_INTR_SOURCE 66 /* Interrupt of MMU Invalid Access, LEVEL */
|
||||
#define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */
|
||||
#define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */
|
||||
|
||||
/* Interrupt cpu using table */
|
||||
/*************************************************************************************************************
|
||||
* Intr num Level Type PRO CPU usage APP CPU uasge
|
||||
* 0 1 extern level WMAC Reserved
|
||||
* 1 1 extern level BT/BLE Host VHCI Reserved
|
||||
* 2 1 extern level FROM_CPU FROM_CPU
|
||||
* 3 1 extern level TG0_WDT Reserved
|
||||
* 4 1 extern level WBB
|
||||
* 5 1 extern level BT Controller
|
||||
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
|
||||
* 7 1 software Reserved Reserved
|
||||
* 8 1 extern level BLE Controller
|
||||
* 9 1 extern level
|
||||
* 10 1 extern edge Internal Timer
|
||||
* 11 3 profiling
|
||||
* 12 1 extern level
|
||||
* 13 1 extern level
|
||||
* 14 7 nmi Reserved Reserved
|
||||
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
|
||||
* 16 5 timer
|
||||
* 17 1 extern level
|
||||
* 18 1 extern level
|
||||
* 19 2 extern level
|
||||
* 20 2 extern level
|
||||
* 21 2 extern level
|
||||
* 22 3 extern edge
|
||||
* 23 3 extern level
|
||||
* 24 4 extern level
|
||||
* 25 4 extern level Reserved Reserved
|
||||
* 26 5 extern level Reserved Reserved
|
||||
* 27 3 extern level Reserved Reserved
|
||||
* 28 4 extern edge
|
||||
* 29 3 software Reserved Reserved
|
||||
* 30 4 extern edge Reserved Reserved
|
||||
* 31 5 extern level Reserved Reserved
|
||||
*************************************************************************************************************/
|
||||
|
||||
/* CPU0 Interrupt number reserved, not touch this. */
|
||||
|
||||
#define ETS_WMAC_INUM 0
|
||||
#define ETS_BT_HOST_INUM 1
|
||||
#define ETS_FROM_CPU_INUM 2
|
||||
#define ETS_T0_WDT_INUM 3
|
||||
#define ETS_WBB_INUM 4
|
||||
#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */
|
||||
|
||||
/* CPU0 Intrrupt number used in ROM, should be cancelled in SDK */
|
||||
|
||||
#define ETS_SLC_INUM 1
|
||||
#define ETS_UART0_INUM 5
|
||||
#define ETS_UART1_INUM 5
|
||||
|
||||
/* Other interrupt numbers should be managed by the user */
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H */
|
||||
128
arch/xtensa/src/esp32/esp32_start.c
Normal file
128
arch/xtensa/src/esp32/esp32_start.c
Normal file
@ -0,0 +1,128 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/common/esp32_start.c
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Basic initialize sequence derives from logic originally provided by
|
||||
* Espressif Systems:
|
||||
*
|
||||
* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
|
||||
#include "xtensa_attr.h"
|
||||
#include "chip/esp32_dport.h"
|
||||
#include "chip/esp32_rtccntl.h"
|
||||
#include "xtensa.h"
|
||||
|
||||
#warning REVISIT Need cpu_configure_region_protection() prototype
|
||||
void cpu_configure_region_protection(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __start
|
||||
*
|
||||
* Description:
|
||||
* We arrive here after the bootloader finished loading the program from
|
||||
* flash. The hardware is mostly uninitialized, and the app CPU is in
|
||||
* reset. We do have a stack, so we can do the initialization in C.
|
||||
*
|
||||
* The app CPU will remain in reset unless CONFIG_SMP is selected and
|
||||
* up_cpu_start() is called later in the bring-up sequeuence.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void IRAM_ATTR __start()
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Kill the watchdog timer */
|
||||
|
||||
regval = getreg32(RTC_CNTL_WDTCONFIG0_REG);
|
||||
regval ~= RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
|
||||
putreg32(regval, RTC_CNTL_WDTCONFIG0_REG);
|
||||
|
||||
regval = getreg32(0x6001f048); /* DR_REG_BB_BASE+48 */
|
||||
regval ~= (1 << 14);
|
||||
putreg32(regval, 0x6001f048);
|
||||
|
||||
/* Make page 0 access raise an exception */
|
||||
|
||||
cpu_configure_region_protection();
|
||||
|
||||
/* Move exception vectors to IRAM */
|
||||
|
||||
asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start));
|
||||
|
||||
/* Set .bss to zero */
|
||||
|
||||
memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
|
||||
|
||||
#warning Missing logic: Initialize .data
|
||||
|
||||
#warning REVISIT heap. Do what with non-heterogeneous memory?
|
||||
#warning REVISIT belongs in up_allocateheap()
|
||||
#if 0
|
||||
/* Initialize heap allocator */
|
||||
|
||||
heap_alloc_caps_init();
|
||||
#endif
|
||||
|
||||
/* Make sure that the APP_CPU is disabled for now */
|
||||
|
||||
regval = getreg32(DPORT_APPCPU_CTRL_B_REG);
|
||||
regval &= ~DPORT_APPCPU_CLKGATE_EN
|
||||
putreg32(regval, DPORT_APPCPU_CTRL_B_REG);
|
||||
|
||||
/* Set CPU frequency configured in board.h */
|
||||
|
||||
esp_set_cpu_freq();
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
/* Perform early serial initialization */
|
||||
|
||||
up_earlyserialinit();
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
esp32_board_initialize();
|
||||
|
||||
#warning These belong elsewhere
|
||||
#if 0
|
||||
ets_setup_syscalls();
|
||||
esp_ipc_init();
|
||||
spi_flash_init();
|
||||
#endif
|
||||
|
||||
/* Bring up NuttX */
|
||||
|
||||
os_start();
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user