Move handle clock macros into a header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1120 42af7a65-404d-4744-a932-0658087f49c3
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arch/arm/src/str71x/str71x_internal.h
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95
arch/arm/src/str71x/str71x_internal.h
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/************************************************************************************
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* arch/arm/src/str71x/str71x_internal.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H
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#define __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "str71x_map.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Calculate the values of PCLK1 and PCLK2 from settings in board.h.
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*
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* Example:
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* STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2)
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* STR71X_CLK2 = 4MHz
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* STR71X_PLL1OUT = 16 * STR71X_CLK2 / 2 = 32MHz
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* CLK3 = 32MHz
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* RCLK = 32MHz
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* PCLK1 = 32MHz / 1 = 32MHz
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*/
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/* PLL1OUT derives from Main OSC->CLK2 */
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#ifdef STR71X_PLL1IN_DIV2 /* CLK2 is input to PLL1 */
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# define STR71X_CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is OSC/2 */
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#else
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# define STR71X_CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is OSC */
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#endif
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#define STR71X_PLL1OUT ((STR71X_PLL1OUT_MUL * STR71X_CLK2) / STR71X_PLL1OUT_DIV)
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/* PLL2 OUTderives from HCLK */
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#define STR71X_PLL2OUT ((STR71X_PLL2OUT_MUL * STR71X_HCLK) / STR71X_PLL2OUT_DIV)
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/* Peripheral clocks derive from PLL1OUT->CLK3->RCLK->PCLK1/2 */
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#define STR71X_CLK3 STR71X_PLL1OUT /* CLK3 hard coded to be PLL1OUT */
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#define STR71X_RCLK STR71X_CLK3 /* RCLK hard coded to be CLK3 */
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#define STR71X_PCLK1 (STR71X_RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */
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#define STR71X_PCLK2 (STR71X_RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H */
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@ -42,7 +42,9 @@
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "str71x_internal.h"
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/**************************************************************************
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* Private Definitions
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@ -200,28 +202,6 @@
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#define STR71X_UARTCR_VALUE (STR71X_UARTCR_MODE|STR71X_UARTCR_PARITY|STR71X_UARTCR_STOP|\
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STR71X_UARTCR_RUN|STR71X_UARTCR_RXENABLE|STR71X_UARTCR_FIFOENABLE)
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/* Calculate the value of PCLK1 from settings in board.h.
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*
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* Example:
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* STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2)
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* CLK2 = 4MHz
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* PLL1OUT = 16 * CLK2 / 2 = 32MHz
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* CLK3 = 32MHz
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* RCLK = 32MHz
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* PCLK1 = 32MHz / 1 = 32MHz
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*/
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#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */
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# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */
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#else
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# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */
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#endif
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/* PLL1OUT derives from CLK2 */
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#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV)
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#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */
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#define RCLK CLK3 /* RCLK hard coded to be CLK3 */
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#define PCLK1 (RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */
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/* Calculate BAUD rate from PCLK1:
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*
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* Example:
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@ -232,7 +212,7 @@
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*/
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#define UART_BAUDDIVISOR (16 * STR71X_UART_BAUD)
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#define UART_BAUDRATE ((PCLK1 + (UART_BAUDDIVISOR/2) / UART_BAUDDIVISOR))
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#define UART_BAUDRATE ((STR71X_PCLK1 + (UART_BAUDDIVISOR/2) / UART_BAUDDIVISOR))
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/**************************************************************************
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* Private Types
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@ -52,6 +52,7 @@
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#include "chip.h"
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#include "up_arch.h"
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#include "up_internal.h"
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#include "str71x_internal.h"
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#ifdef CONFIG_USE_SERIALDRIVER
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@ -181,28 +182,6 @@
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# warning "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
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#endif
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/* Calculate the value of PCLK1 from settings in board.h.
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*
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* Example:
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* STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2)
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* CLK2 = 4MHz
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* PLL1OUT = 16 * CLK2 / 2 = 32MHz
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* CLK3 = 32MHz
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* RCLK = 32MHz
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* PCLK1 = 32MHz / 1 = 32MHz
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*/
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#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */
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# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */
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#else
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# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */
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#endif
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/* PLL1OUT derives from CLK2 */
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#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV)
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#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */
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#define RCLK CLK3 /* RCLK hard coded to be CLK3 */
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#define PCLK1 (RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -486,7 +465,7 @@ static int up_setup(struct uart_dev_s *dev)
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/* Set the BAUD rate */
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divisor = 16 * priv->baud;
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baud = (PCLK1 + divisor/2) / divisor;
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baud = (STR71X_PCLK1 + divisor/2) / divisor;
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up_serialout(priv, STR71X_UART_BR_OFFSET, baud);
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/* Get mode setting */
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@ -49,33 +49,12 @@
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#include "up_arch.h"
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#include "chip.h"
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#include "str71x_internal.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Calculate the value of PCLK2 from settings in board.h.
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*
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* Example:
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* STR71X_RCCU_MAIN_OSC = 4MHz
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* CLK2 = 4MHz (not divided by 2)
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* PLL1OUT = 16 * CLK2 / 2 = 32MHz
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* CLK3 = 32MHz
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* RCLK = 32MHz
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* PCLK2 = 32MHz / 1 = 32MHz
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*/
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#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */
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# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */
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#else
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# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */
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#endif
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/* PLL1OUT derives from CLK2 */
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#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV)
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#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */
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#define RCLK CLK3 /* RCLK hard coded to be CLK3 */
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#define PCLK2 (RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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@ -101,8 +80,8 @@
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* than the maximum.
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*/
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#if PCLK2 > MAX_TIM0CLK
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# define PCLK2_DIVIDER (((PCLK2) + (MAX_TIM0CLK+1)) / MAX_TIM0CLK)
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#if STR71X_PCLK2 > MAX_TIM0CLK
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# define PCLK2_DIVIDER (((STR71X_PCLK2) + (MAX_TIM0CLK+1)) / MAX_TIM0CLK)
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#else
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# define PCLK2_DIVIDER (1)
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#endif
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@ -116,7 +95,7 @@
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* TIM0CLK would 6,4000,000 and the final OCAR_VALUE would be 64,000.
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*/
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#define ACTUAL_TIM0CLK (PCLK2 / PCLK2_DIVIDER)
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#define ACTUAL_TIM0CLK (STR71X_PCLK2 / PCLK2_DIVIDER)
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#define OCAR_VALUE (ACTUAL_TIM0CLK / CLK_TCK)
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#if OCAR_VALUE > 65535
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