diff --git a/arch/arm/src/str71x/str71x_internal.h b/arch/arm/src/str71x/str71x_internal.h new file mode 100644 index 0000000000..ffb9bbb5ce --- /dev/null +++ b/arch/arm/src/str71x/str71x_internal.h @@ -0,0 +1,95 @@ +/************************************************************************************ + * arch/arm/src/str71x/str71x_internal.h + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H +#define __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include "str71x_map.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Calculate the values of PCLK1 and PCLK2 from settings in board.h. + * + * Example: + * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2) + * STR71X_CLK2 = 4MHz + * STR71X_PLL1OUT = 16 * STR71X_CLK2 / 2 = 32MHz + * CLK3 = 32MHz + * RCLK = 32MHz + * PCLK1 = 32MHz / 1 = 32MHz + */ + +/* PLL1OUT derives from Main OSC->CLK2 */ + +#ifdef STR71X_PLL1IN_DIV2 /* CLK2 is input to PLL1 */ +# define STR71X_CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is OSC/2 */ +#else +# define STR71X_CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is OSC */ +#endif + +#define STR71X_PLL1OUT ((STR71X_PLL1OUT_MUL * STR71X_CLK2) / STR71X_PLL1OUT_DIV) + +/* PLL2 OUTderives from HCLK */ + +#define STR71X_PLL2OUT ((STR71X_PLL2OUT_MUL * STR71X_HCLK) / STR71X_PLL2OUT_DIV) + +/* Peripheral clocks derive from PLL1OUT->CLK3->RCLK->PCLK1/2 */ + +#define STR71X_CLK3 STR71X_PLL1OUT /* CLK3 hard coded to be PLL1OUT */ +#define STR71X_RCLK STR71X_CLK3 /* RCLK hard coded to be CLK3 */ +#define STR71X_PCLK1 (STR71X_RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */ +#define STR71X_PCLK2 (STR71X_RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H */ diff --git a/arch/arm/src/str71x/str71x_lowputc.c b/arch/arm/src/str71x/str71x_lowputc.c index 2c98f20599..d4f22bb11f 100644 --- a/arch/arm/src/str71x/str71x_lowputc.c +++ b/arch/arm/src/str71x/str71x_lowputc.c @@ -42,7 +42,9 @@ #include "up_internal.h" #include "up_arch.h" + #include "chip.h" +#include "str71x_internal.h" /************************************************************************** * Private Definitions @@ -200,28 +202,6 @@ #define STR71X_UARTCR_VALUE (STR71X_UARTCR_MODE|STR71X_UARTCR_PARITY|STR71X_UARTCR_STOP|\ STR71X_UARTCR_RUN|STR71X_UARTCR_RXENABLE|STR71X_UARTCR_FIFOENABLE) -/* Calculate the value of PCLK1 from settings in board.h. - * - * Example: - * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2) - * CLK2 = 4MHz - * PLL1OUT = 16 * CLK2 / 2 = 32MHz - * CLK3 = 32MHz - * RCLK = 32MHz - * PCLK1 = 32MHz / 1 = 32MHz - */ - -#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */ -# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */ -#else -# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */ -#endif - /* PLL1OUT derives from CLK2 */ -#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV) -#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */ -#define RCLK CLK3 /* RCLK hard coded to be CLK3 */ -#define PCLK1 (RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */ - /* Calculate BAUD rate from PCLK1: * * Example: @@ -232,7 +212,7 @@ */ #define UART_BAUDDIVISOR (16 * STR71X_UART_BAUD) -#define UART_BAUDRATE ((PCLK1 + (UART_BAUDDIVISOR/2) / UART_BAUDDIVISOR)) +#define UART_BAUDRATE ((STR71X_PCLK1 + (UART_BAUDDIVISOR/2) / UART_BAUDDIVISOR)) /************************************************************************** * Private Types diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index 72514324c2..e9739ec622 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -52,6 +52,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" +#include "str71x_internal.h" #ifdef CONFIG_USE_SERIALDRIVER @@ -181,28 +182,6 @@ # warning "No CONFIG_UARTn_SERIAL_CONSOLE Setting" #endif -/* Calculate the value of PCLK1 from settings in board.h. - * - * Example: - * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2) - * CLK2 = 4MHz - * PLL1OUT = 16 * CLK2 / 2 = 32MHz - * CLK3 = 32MHz - * RCLK = 32MHz - * PCLK1 = 32MHz / 1 = 32MHz - */ - -#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */ -# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */ -#else -# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */ -#endif - /* PLL1OUT derives from CLK2 */ -#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV) -#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */ -#define RCLK CLK3 /* RCLK hard coded to be CLK3 */ -#define PCLK1 (RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */ - /**************************************************************************** * Private Types ****************************************************************************/ @@ -486,7 +465,7 @@ static int up_setup(struct uart_dev_s *dev) /* Set the BAUD rate */ divisor = 16 * priv->baud; - baud = (PCLK1 + divisor/2) / divisor; + baud = (STR71X_PCLK1 + divisor/2) / divisor; up_serialout(priv, STR71X_UART_BR_OFFSET, baud); /* Get mode setting */ diff --git a/arch/arm/src/str71x/str71x_timerisr.c b/arch/arm/src/str71x/str71x_timerisr.c index 1e6f6215a3..571d67de27 100644 --- a/arch/arm/src/str71x/str71x_timerisr.c +++ b/arch/arm/src/str71x/str71x_timerisr.c @@ -49,33 +49,12 @@ #include "up_arch.h" #include "chip.h" +#include "str71x_internal.h" /**************************************************************************** * Definitions ****************************************************************************/ -/* Calculate the value of PCLK2 from settings in board.h. - * - * Example: - * STR71X_RCCU_MAIN_OSC = 4MHz - * CLK2 = 4MHz (not divided by 2) - * PLL1OUT = 16 * CLK2 / 2 = 32MHz - * CLK3 = 32MHz - * RCLK = 32MHz - * PCLK2 = 32MHz / 1 = 32MHz - */ - -#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */ -# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */ -#else -# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */ -#endif - /* PLL1OUT derives from CLK2 */ -#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV) -#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */ -#define RCLK CLK3 /* RCLK hard coded to be CLK3 */ -#define PCLK2 (RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */ - /* The desired timer interrupt frequency is provided by the definition * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of * system clock ticks per second. That value is a user configurable setting @@ -101,8 +80,8 @@ * than the maximum. */ -#if PCLK2 > MAX_TIM0CLK -# define PCLK2_DIVIDER (((PCLK2) + (MAX_TIM0CLK+1)) / MAX_TIM0CLK) +#if STR71X_PCLK2 > MAX_TIM0CLK +# define PCLK2_DIVIDER (((STR71X_PCLK2) + (MAX_TIM0CLK+1)) / MAX_TIM0CLK) #else # define PCLK2_DIVIDER (1) #endif @@ -116,7 +95,7 @@ * TIM0CLK would 6,4000,000 and the final OCAR_VALUE would be 64,000. */ -#define ACTUAL_TIM0CLK (PCLK2 / PCLK2_DIVIDER) +#define ACTUAL_TIM0CLK (STR71X_PCLK2 / PCLK2_DIVIDER) #define OCAR_VALUE (ACTUAL_TIM0CLK / CLK_TCK) #if OCAR_VALUE > 65535