From c1886c6181fd41972243475d096c9c7b610d536d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 4 Apr 2015 19:04:29 -0600 Subject: [PATCH] SAMV7: Apparently the data sheet is wrong, SDRAM clocking must be enabled at the PMC or the SDRAM does not work! The data sheet says that there is no clock control for SDRAMC --- arch/arm/src/samv7/samv71_periphclks.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/samv7/samv71_periphclks.h b/arch/arm/src/samv7/samv71_periphclks.h index 6a360dba4c..60ed117fe8 100644 --- a/arch/arm/src/samv7/samv71_periphclks.h +++ b/arch/arm/src/samv7/samv71_periphclks.h @@ -118,7 +118,7 @@ #define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI) #define sam_pwm1_enableclk() sam_enableperiph1(SAM_PID_PWM1) #define sam_fpu_enableclk() -#define sam_sdramc_enableclk() +#define sam_sdramc_enableclk() sam_enableperiph1(SAM_PID_SDRAMC) #define sam_wdt1_enableclk() #define sam_ccw_enableclk() @@ -186,7 +186,7 @@ #define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI) #define sam_pwm1_disableclk() sam_disableperiph1(SAM_PID_PWM1) #define sam_fpu_disableclk() -#define sam_sdramc_disableclk() +#define sam_sdramc_disableclk() sam_disableperiph1(SAM_PID_SDRAMC) #define sam_wdt1_disableclk() #define sam_ccw_disableclk()