stm32h7:spi Add buffers for DMA
This commit is contained in:
David Sidrane
patacongo
parent
a62aa84448
commit
c191787ba4
@ -633,6 +633,90 @@ config STM32H7_SPI_DMATHRESHOLD
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by polling logic. But we need a threshold value to determine what
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is small.
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config STM32H7_SPI1_DMA
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bool "SPI1 DMA"
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default n
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depends on STM32H7_SPI1 && STM32H7_SPI_DMA
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---help---
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Use DMA to improve SPI1 transfer performance.
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config STM32H7_SPI1_DMA_BUFFER
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int "SPI1 DMA buffer size"
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default 0
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depends on STM32H7_SPI1_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI1.
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config STM32H7_SPI2_DMA
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bool "SPI2 DMA"
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default n
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depends on STM32H7_SPI2 && STM32H7_SPI_DMA
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---help---
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Use DMA to improve SPI2 transfer performance.
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config STM32H7_SPI2_DMA_BUFFER
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int "SPI2 DMA buffer size"
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default 0
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depends on STM32H7_SPI2_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI2.
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config STM32H7_SPI3_DMA
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bool "SPI3 DMA"
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default n
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depends on STM32H7_SPI3 && STM32H7_SPI_DMA
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---help---
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Use DMA to improve SPI3 transfer performance.
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config STM32H7_SPI3_DMA_BUFFER
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int "SPI3 DMA buffer size"
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default 0
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depends on STM32H7_SPI3_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI3.
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config STM32H7_SPI4_DMA
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bool "SPI4 DMA"
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default n
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depends on STM32H7_SPI4 && STM32H7_SPI_DMA
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---help---
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Use DMA to improve SPI4 transfer performance.
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config STM32H7_SPI4_DMA_BUFFER
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int "SPI4 DMA buffer size"
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default 0
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depends on STM32H7_SPI4_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI4.
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config STM32H7_SPI5_DMA
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bool "SPI5 DMA"
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default n
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depends on STM32H7_SPI5 && STM32H7_SPI_DMA
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---help---
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Use DMA to improve SPI5 transfer performance.
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config STM32H7_SPI5_DMA_BUFFER
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int "SPI5 DMA buffer size"
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default 0
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depends on STM32H7_SPI5_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI5.
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config STM32H7_SPI6_DMA
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bool "SPI6 DMA"
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default n
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depends on STM32H7_SPI6 && STM32H7_SPI_DMA
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---help---
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Use DMA to improve SPI6 transfer performance.
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config STM32H7_SPI6_DMA_BUFFER
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int "SPI6 DMA buffer size"
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default 0
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depends on STM32H7_SPI6_DMA
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---help---
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Add a properly aligned DMA buffer for RX and TX DMA for SPI6.
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endmenu # "SPI Configuration"
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menu "U[S]ART Configuration"
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@ -51,6 +51,7 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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@ -119,6 +120,56 @@
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# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_M2P)
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# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P)
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# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P)
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/* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and
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* multiples of ARMV7M_DCACHE_LINESIZE
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*/
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# if defined(CONFIG_ARMV7M_DCACHE)
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# define SPIDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
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# define SPIDMA_SIZE(b) (((b) + SPIDMA_BUFFER_MASK) & ~SPIDMA_BUFFER_MASK)
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# define SPIDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE)
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# else
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# define SPIDMA_SIZE(b) (b)
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# define SPIDMA_BUF_ALIGN
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# endif
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# if defined(CONFIG_STM32H7_SPI1_DMA_BUFFER) && \
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CONFIG_STM32H7_SPI1_DMA_BUFFER > 0
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# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI1_DMA_BUFFER)
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# define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
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# endif
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# if defined(CONFIG_STM32H7_SPI2_DMA_BUFFER) && \
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CONFIG_STM32H7_SPI2_DMA_BUFFER > 0
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# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI2_DMA_BUFFER)
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# define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
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# endif
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# if defined(CONFIG_STM32H7_SPI3_DMA_BUFFER) && \
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CONFIG_STM32H7_SPI3_DMA_BUFFER > 0
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# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI3_DMA_BUFFER)
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# define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
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# endif
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# if defined(CONFIG_STM32H7_SPI4_DMA_BUFFER) && \
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CONFIG_STM32H7_SPI4_DMA_BUFFER > 0
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# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI4_DMA_BUFFER)
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# define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
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# endif
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# if defined(CONFIG_STM32H7_SPI5_DMA_BUFFER) && \
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CONFIG_STM32H7_SPI5_DMA_BUFFER > 0
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# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI5_DMA_BUFFER)
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# define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
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# endif
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#if defined(CONFIG_STM32H7_SPI6_DMA_BUFFER) && \
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CONFIG_STM32H7_SPI6_DMA_BUFFER > 0
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# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI6_DMA_BUFFER)
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# define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
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# endif
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#endif
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/* Kernel clock configuration
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@ -187,6 +238,9 @@ struct stm32_spidev_s
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#endif
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uint32_t rxch; /* The RX DMA channel number */
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uint32_t txch; /* The TX DMA channel number */
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uint8_t *rxbuf; /* The RX DMA buffer */
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uint8_t *txbuf; /* The TX DMA buffer */
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size_t buflen; /* The DMA buffer length */
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DMA_HANDLE rxdma; /* DMA channel handle for RX transfers */
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DMA_HANDLE txdma; /* DMA channel handle for TX transfers */
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sem_t rxsem; /* Wait for RX DMA to complete */
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@ -218,7 +272,6 @@ static inline void spi_putreg(FAR struct stm32_spidev_s *priv,
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static inline uint32_t spi_readword(FAR struct stm32_spidev_s *priv);
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static inline void spi_writeword(FAR struct stm32_spidev_s *priv,
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uint32_t byte);
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static inline bool spi_9to16bitmode(FAR struct stm32_spidev_s *priv);
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#ifdef CONFIG_DEBUG_SPI_INFO
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static inline void spi_dumpregs(FAR struct stm32_spidev_s *priv);
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#endif
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@ -319,6 +372,11 @@ static const struct spi_ops_s g_sp1iops =
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#endif
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};
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#if defined(SPI1_DMABUFSIZE_ADJUSTED)
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static uint8_t g_spi1_txbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN;
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static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN;
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#endif
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static struct stm32_spidev_s g_spi1dev =
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{
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.spidev =
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@ -330,9 +388,14 @@ static struct stm32_spidev_s g_spi1dev =
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#ifdef CONFIG_STM32H7_SPI_INTERRUPTS
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.spiirq = STM32_IRQ_SPI1,
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#endif
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#ifdef CONFIG_STM32H7_SPI_DMA
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#ifdef CONFIG_STM32H7_SPI1_DMA
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.rxch = DMAMAP_SPI1_RX,
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.txch = DMAMAP_SPI1_TX,
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# if defined(SPI1_DMABUFSIZE_ADJUSTED)
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.rxbuf = g_spi1_rxbuf,
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.txbuf = g_spi1_txbuf,
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.buflen = SPI1_DMABUFSIZE_ADJUSTED,
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# endif
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#endif
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#ifdef CONFIG_PM
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.pm_cb.prepare = spi_pm_prepare,
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@ -372,6 +435,11 @@ static const struct spi_ops_s g_sp2iops =
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#endif
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};
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#if defined(SPI2_DMABUFSIZE_ADJUSTED)
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static uint8_t g_spi2_txbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN;
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static uint8_t g_spi2_rxbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN;
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#endif
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static struct stm32_spidev_s g_spi2dev =
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{
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.spidev =
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@ -383,9 +451,14 @@ static struct stm32_spidev_s g_spi2dev =
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#ifdef CONFIG_STM32H7_SPI_INTERRUPTS
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.spiirq = STM32_IRQ_SPI2,
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#endif
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#ifdef CONFIG_STM32H7_SPI_DMA
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#ifdef CONFIG_STM32H7_SPI2_DMA
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.rxch = DMAMAP_SPI2_RX,
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.txch = DMAMAP_SPI2_TX,
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# if defined(SPI2_DMABUFSIZE_ADJUSTED)
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.rxbuf = g_spi2_rxbuf,
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.txbuf = g_spi2_txbuf,
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.buflen = SPI2_DMABUFSIZE_ADJUSTED,
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# endif
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#endif
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#ifdef CONFIG_PM
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.pm_cb.prepare = spi_pm_prepare,
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@ -425,6 +498,11 @@ static const struct spi_ops_s g_sp3iops =
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#endif
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};
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#if defined(SPI3_DMABUFSIZE_ADJUSTED)
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static uint8_t g_spi3_txbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN;
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static uint8_t g_spi3_rxbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN;
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#endif
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static struct stm32_spidev_s g_spi3dev =
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{
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.spidev =
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@ -436,9 +514,14 @@ static struct stm32_spidev_s g_spi3dev =
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#ifdef CONFIG_STM32H7_SPI_INTERRUPTS
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.spiirq = STM32_IRQ_SPI3,
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#endif
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#ifdef CONFIG_STM32H7_SPI_DMA
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#ifdef CONFIG_STM32H7_SPI3_DMA
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.rxch = DMAMAP_SPI3_RX,
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.txch = DMAMAP_SPI3_TX,
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# if defined(SPI3_DMABUFSIZE_ADJUSTED)
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.rxbuf = g_spi3_rxbuf,
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.txbuf = g_spi3_txbuf,
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.buflen = SPI3_DMABUFSIZE_ADJUSTED,
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# endif
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#endif
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#ifdef CONFIG_PM
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.pm_cb.prepare = spi_pm_prepare,
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@ -478,6 +561,11 @@ static const struct spi_ops_s g_sp4iops =
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#endif
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};
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#if defined(SPI4_DMABUFSIZE_ADJUSTED)
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static uint8_t g_spi4_txbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN;
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static uint8_t g_spi4_rxbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN;
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#endif
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static struct stm32_spidev_s g_spi4dev =
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{
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.spidev =
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@ -489,9 +577,14 @@ static struct stm32_spidev_s g_spi4dev =
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#ifdef CONFIG_STM32H7_SPI_INTERRUPTS
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.spiirq = STM32_IRQ_SPI4,
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#endif
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#ifdef CONFIG_STM32H7_SPI_DMA
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#ifdef CONFIG_STM32H7_SPI4_DMA
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.rxch = DMAMAP_SPI4_RX,
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.txch = DMAMAP_SPI4_TX,
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# if defined(SPI4_DMABUFSIZE_ADJUSTED)
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.rxbuf = g_spi4_rxbuf,
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.txbuf = g_spi4_txbuf,
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.buflen = SPI4_DMABUFSIZE_ADJUSTED,
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# endif
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#endif
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#ifdef CONFIG_PM
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.pm_cb.prepare = spi_pm_prepare,
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@ -531,6 +624,11 @@ static const struct spi_ops_s g_sp5iops =
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#endif
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};
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#if defined(SPI5_DMABUFSIZE_ADJUSTED)
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static uint8_t g_spi5_txbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN;
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static uint8_t g_spi5_rxbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN;
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#endif
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static struct stm32_spidev_s g_spi5dev =
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{
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.spidev =
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@ -542,9 +640,14 @@ static struct stm32_spidev_s g_spi5dev =
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#ifdef CONFIG_STM32H7_SPI_INTERRUPTS
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.spiirq = STM32_IRQ_SPI5,
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#endif
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#ifdef CONFIG_STM32H7_SPI_DMA
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#ifdef CONFIG_STM32H7_SPI5_DMA
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.rxch = DMAMAP_SPI5_RX,
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.txch = DMAMAP_SPI5_TX,
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# if defined(SPI5_DMABUFSIZE_ADJUSTED)
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.rxbuf = g_spi5_rxbuf,
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.txbuf = g_spi5_txbuf,
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.buflen = SPI5_DMABUFSIZE_ADJUSTED,
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# endif
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#endif
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#ifdef CONFIG_PM
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.pm_cb.prepare = spi_pm_prepare,
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@ -584,6 +687,11 @@ static const struct spi_ops_s g_sp6iops =
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#endif
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};
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#if defined(SPI6_DMABUFSIZE_ADJUSTED)
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static uint8_t g_spi6_txbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN;
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static uint8_t g_spi6_rxbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN;
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#endif
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static struct stm32_spidev_s g_spi6dev =
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{
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.spidev =
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@ -595,9 +703,14 @@ static struct stm32_spidev_s g_spi6dev =
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#ifdef CONFIG_STM32H7_SPI_INTERRUPTS
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.spiirq = STM32_IRQ_SPI6,
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#endif
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#ifdef CONFIG_STM32H7_SPI_DMA
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#ifdef CONFIG_STM32H7_SPI6_DMA
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.rxch = DMAMAP_SPI6_RX,
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.txch = DMAMAP_SPI6_TX,
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#if defined(SPI6_DMABUFSIZE_ADJUSTED)
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.rxbuf = g_spi6_rxbuf,
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.txbuf = g_spi6_txbuf,
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.buflen = SPI6_DMABUFSIZE_ADJUSTED,
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# endif
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#endif
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#ifdef CONFIG_PM
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.pm_cb.prepare = spi_pm_prepare,
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@ -814,27 +927,6 @@ static void spi_dumpregs(FAR struct stm32_spidev_s *priv)
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}
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#endif
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/****************************************************************************
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* Name: spi_9to16bitmode
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*
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* Description:
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* Check if the SPI is operating in more then 8 bit mode
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*
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* Input Parameters:
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* priv - Device-specific state data
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*
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* Returned Value:
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* true: >8 bit mode-bit mode, false: <= 8-bit mode
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*
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****************************************************************************/
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static inline bool spi_9to16bitmode(FAR struct stm32_spidev_s *priv)
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{
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uint32_t regval = spi_getreg(priv, STM32_SPI_CFG1_OFFSET);
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return ((regval & SPI_CFG1_CRCSIZE_9BIT) == SPI_CFG1_CRCSIZE_9BIT);
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}
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/****************************************************************************
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* Name: spi_dmarxwait
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*
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@ -988,7 +1080,7 @@ static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv,
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/* 8- or 16-bit mode? */
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if (spi_9to16bitmode(priv))
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if (priv->nbits > 8)
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{
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/* 16-bit mode -- is there a buffer to receive data in? */
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@ -1046,7 +1138,7 @@ static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv,
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/* 8- or 16-bit mode? */
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if (spi_9to16bitmode(priv))
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if (priv->nbits > 8)
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{
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/* 16-bit mode -- is there a buffer to transfer data from? */
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@ -1565,7 +1657,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd)
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* frames, two bytes are received by a 16-bit read of the data register!
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*/
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if (spi_9to16bitmode(priv))
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if (priv->nbits > 8)
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{
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spi_writeword(priv, (uint16_t)(wd & 0xffff));
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ret = spi_readword(priv);
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@ -1589,7 +1681,7 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd)
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/* Dump some info */
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if (spi_9to16bitmode(priv))
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if (priv->nbits > 8)
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{
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spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval);
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}
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@ -1641,7 +1733,7 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev,
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/* 8- or 16-bit mode? */
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|
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if (spi_9to16bitmode(priv))
|
||||
if (priv->nbits > 8)
|
||||
{
|
||||
/* 16-bit mode */
|
||||
|
||||
@ -1739,14 +1831,14 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
|
||||
FAR void *rxbuffer, size_t nwords)
|
||||
{
|
||||
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
|
||||
|
||||
FAR void * xbuffer = rxbuffer;
|
||||
DEBUGASSERT(priv != NULL);
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI_DMATHRESHOLD
|
||||
/* Convert the number of word to a number of bytes */
|
||||
|
||||
size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords;
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI_DMATHRESHOLD
|
||||
/* If this is a small SPI transfer, then let spi_exchange_nodma() do the work. */
|
||||
|
||||
if (nbytes <= CONFIG_STM32H7_SPI_DMATHRESHOLD)
|
||||
@ -1768,23 +1860,48 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32H7_DMACAPABLE
|
||||
stm32_dmacfg_t dmacfg1;
|
||||
stm32_dmacfg_t dmacfg2;
|
||||
stm32_dmacfg_t dmatxcfg;
|
||||
stm32_dmacfg_t dmarxcfg;
|
||||
|
||||
/* Setup DMAs */
|
||||
|
||||
/* If this bus uses a in driver buffers we will incur 2 copies,
|
||||
* The copy cost is << less the non DMA transfer time and having
|
||||
* the buffer in the driver ensures DMA can be used. This is bacause
|
||||
* the API does not support passing the buffer extent so the only
|
||||
* extent is buffer + the transfer size. These can sizes be less than
|
||||
* the cache line size, and not aligned and tyicaly greater then 4
|
||||
* bytes, which is about the break even point for the DMA IO overhead.
|
||||
*/
|
||||
|
||||
if (txbuffer && priv->txbuf)
|
||||
{
|
||||
if (nbytes > priv->buflen)
|
||||
{
|
||||
nbytes = priv->buflen;
|
||||
}
|
||||
|
||||
memcpy(priv->txbuf, txbuffer, nbytes);
|
||||
txbuffer = priv->txbuf;
|
||||
rxbuffer = rxbuffer ? priv->rxbuf : rxbuffer;
|
||||
}
|
||||
|
||||
/* TX transfer configuration */
|
||||
|
||||
dmacfg1.maddr = (uint32_t)txbuffer;
|
||||
dmacfg1.ndata = nwords;
|
||||
dmacfg1.cfg1 = priv->txccr;
|
||||
dmatxcfg.maddr = (uint32_t)txbuffer;
|
||||
dmatxcfg.ndata = nwords;
|
||||
dmatxcfg.cfg1 = priv->txccr;
|
||||
|
||||
/* RX transfer configuration */
|
||||
|
||||
dmacfg2.maddr = (uint32_t)rxbuffer;
|
||||
dmacfg2.ndata = nwords;
|
||||
dmacfg2.cfg1 = priv->rxccr;
|
||||
dmarxcfg.maddr = (uint32_t)rxbuffer;
|
||||
dmarxcfg.ndata = nwords;
|
||||
dmarxcfg.cfg1 = priv->rxccr;
|
||||
|
||||
if ((txbuffer && !stm32_dmacapable(priv->txdma, &dmacfg1)) ||
|
||||
(rxbuffer && !stm32_dmacapable(priv->rxdma, &dmacfg2)))
|
||||
if ((txbuffer && priv->txbuf == 0 &&
|
||||
!stm32_dmacapable(priv->txdma, &dmatxcfg)) ||
|
||||
(rxbuffer && priv->rxbuf == 0 &&
|
||||
!stm32_dmacapable(priv->rxdma, &dmarxcfg)))
|
||||
{
|
||||
/* Unsupported memory region fall back to non-DMA method. */
|
||||
|
||||
@ -1793,30 +1910,21 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
|
||||
else
|
||||
#endif
|
||||
{
|
||||
static uint8_t rxdummy[ARMV7M_DCACHE_LINESIZE]
|
||||
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
|
||||
static uint8_t rxdummy[4] __attribute__((aligned(4)));
|
||||
static const uint16_t txdummy = 0xffff;
|
||||
size_t buflen = nwords;
|
||||
|
||||
if (spi_9to16bitmode(priv))
|
||||
{
|
||||
buflen = nwords * sizeof(uint16_t);
|
||||
}
|
||||
|
||||
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n",
|
||||
txbuffer, rxbuffer, nwords);
|
||||
DEBUGASSERT(priv->spibase != 0);
|
||||
|
||||
/* Setup DMAs */
|
||||
|
||||
spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords);
|
||||
spi_dmatxsetup(priv, txbuffer, &txdummy, nwords);
|
||||
spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nbytes);
|
||||
spi_dmatxsetup(priv, txbuffer, &txdummy, nbytes);
|
||||
|
||||
/* Flush cache to physical memory */
|
||||
|
||||
if (txbuffer)
|
||||
{
|
||||
up_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen);
|
||||
up_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + nbytes);
|
||||
}
|
||||
|
||||
/* REVISIT: Master transfer start */
|
||||
@ -1864,12 +1972,12 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
|
||||
if (rxbuffer != NULL)
|
||||
{
|
||||
up_invalidate_dcache((uintptr_t)rxbuffer,
|
||||
(uintptr_t)rxbuffer + buflen);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_invalidate_dcache((uintptr_t)rxdummy,
|
||||
(uintptr_t)rxdummy + sizeof(rxdummy));
|
||||
(uintptr_t)rxbuffer + nbytes);
|
||||
|
||||
if (priv->rxbuf)
|
||||
{
|
||||
memcpy(xbuffer, priv->rxbuf, nbytes);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user