sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

fix arm FPSCR typos in comments.

Browse Source
This commit is contained in:
Oki Minabe 2022-02-17 00:01:00 +09:00 committed by Xiang Xiao
parent 7675be7a09
commit c1ea37742b
12 changed files with 36 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/src/armv7-a/arm_fullcontextrestore.S
View File

@ -87,11 +87,11 @@ arm_fullcontextrestore:
#endif #endif
/* Load the floating point control and status register. At the end of the /* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
#endif #endif
#ifdef CONFIG_BUILD_KERNEL #ifdef CONFIG_BUILD_KERNEL

4
arch/arm/src/armv7-a/arm_restorefpu.S
View File

@ -80,11 +80,11 @@ arm_restorefpu:
#endif #endif
/* Load the floating point control and status register. At the end of the /* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
bx lr bx lr
.size arm_restorefpu, .-arm_restorefpu .size arm_restorefpu, .-arm_restorefpu

4
arch/arm/src/armv7-a/arm_savefpu.S
View File

@ -84,10 +84,10 @@ arm_savefpu:
#endif #endif
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
vmrs r2, fpscr /* Fetch the FPCSR */ vmrs r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
bx lr bx lr

4
arch/arm/src/armv7-a/arm_saveusercontext.S
View File

@ -115,10 +115,10 @@ arm_saveusercontext:
#endif #endif
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
vmrs r2, fpscr /* Fetch the FPCSR */ vmrs r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
#endif #endif

14
arch/arm/src/armv7-m/gnu/arm_fpu.S
View File

@ -87,10 +87,10 @@ arm_savefpu:
vstmia r1!, {s0-s31} /* Save the full FP context */ vstmia r1!, {s0-s31} /* Save the full FP context */
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
vmrs r2, fpscr /* Fetch the FPCSR */ vmrs r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
#else #else
/* Store all floating point registers */ /* Store all floating point registers */
@ -150,7 +150,7 @@ arm_savefpu:
/* Store the floating point control and status register */ /* Store the floating point control and status register */
fmrx r2, fpscr /* Fetch the FPCSR */ fmrx r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
#endif #endif
bx lr bx lr
@ -193,11 +193,11 @@ arm_restorefpu:
vldmia r1!, {s0-s31} /* Restore the full FP context */ vldmia r1!, {s0-s31} /* Restore the full FP context */
/* Load the floating point control and status register. At the end of the /* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
#else #else
/* Load all floating point registers Registers are loaded in numeric order, /* Load all floating point registers Registers are loaded in numeric order,
* s0, s1, ... in increasing address order. * s0, s1, ... in increasing address order.
@ -257,11 +257,11 @@ arm_restorefpu:
#endif #endif
/* Load the floating point control and status register. r1 points t /* Load the floating point control and status register. r1 points t
* the address of the FPCSR register. * the address of the FPSCR register.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
fmxr fpscr, r2 /* Restore the FPCSR */ fmxr fpscr, r2 /* Restore the FPSCR */
#endif #endif
bx lr bx lr

4
arch/arm/src/armv7-r/arm_fullcontextrestore.S
View File

@ -86,11 +86,11 @@ arm_fullcontextrestore:
#endif #endif
/* Load the floating point control and status register. At the end of the /* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
#endif #endif
#ifdef CONFIG_BUILD_PROTECTED #ifdef CONFIG_BUILD_PROTECTED

4
arch/arm/src/armv7-r/arm_restorefpu.S
View File

@ -80,11 +80,11 @@ arm_restorefpu:
#endif #endif
/* Load the floating point control and status register. At the end of the /* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
bx lr bx lr
.size arm_restorefpu, .-arm_restorefpu .size arm_restorefpu, .-arm_restorefpu

4
arch/arm/src/armv7-r/arm_savefpu.S
View File

@ -84,10 +84,10 @@ arm_savefpu:
#endif #endif
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
vmrs r2, fpscr /* Fetch the FPCSR */ vmrs r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
bx lr bx lr

4
arch/arm/src/armv7-r/arm_saveusercontext.S
View File

@ -114,10 +114,10 @@ arm_saveusercontext:
#endif #endif
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
vmrs r2, fpscr /* Fetch the FPCSR */ vmrs r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
#endif #endif

14
arch/arm/src/armv8-m/arm_fpu.S
View File

@ -87,10 +87,10 @@ arm_savefpu:
vstmia r1!, {s0-s31} /* Save the full FP context */ vstmia r1!, {s0-s31} /* Save the full FP context */
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
vmrs r2, fpscr /* Fetch the FPCSR */ vmrs r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
#else #else
/* Store all floating point registers */ /* Store all floating point registers */
@ -150,7 +150,7 @@ arm_savefpu:
/* Store the floating point control and status register */ /* Store the floating point control and status register */
fmrx r2, fpscr /* Fetch the FPCSR */ fmrx r2, fpscr /* Fetch the FPSCR */
str r2, [r1], #4 /* Save the floating point control and status register */ str r2, [r1], #4 /* Save the floating point control and status register */
#endif #endif
bx lr bx lr
@ -193,11 +193,11 @@ arm_restorefpu:
vldmia r1!, {s0-s31} /* Restore the full FP context */ vldmia r1!, {s0-s31} /* Restore the full FP context */
/* Load the floating point control and status register. At the end of the /* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location. * vstmia, r1 will point to the FPSCR storage location.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
#else #else
/* Load all floating point registers Registers are loaded in numeric order, /* Load all floating point registers Registers are loaded in numeric order,
* s0, s1, ... in increasing address order. * s0, s1, ... in increasing address order.
@ -257,11 +257,11 @@ arm_restorefpu:
#endif #endif
/* Load the floating point control and status register. r1 points t /* Load the floating point control and status register. r1 points t
* the address of the FPCSR register. * the address of the FPSCR register.
*/ */
ldr r2, [r1], #4 /* Fetch the floating point control and status register */ ldr r2, [r1], #4 /* Fetch the floating point control and status register */
fmxr fpscr, r2 /* Restore the FPCSR */ fmxr fpscr, r2 /* Restore the FPSCR */
#endif #endif
bx lr bx lr

6
libs/libc/machine/arm/armv7-m/gnu/arch_setjmp.S
View File

@ -77,10 +77,10 @@ setjmp:
vstmia r0!, {s16-s31} /* Save the callee-saved FP registers */ vstmia r0!, {s16-s31} /* Save the callee-saved FP registers */
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r0 will point to the FPCSR storage location. * vstmia, r0 will point to the FPSCR storage location.
*/ */
vmrs r1, fpscr /* Fetch the FPCSR */ vmrs r1, fpscr /* Fetch the FPSCR */
str r1, [r0], #4 /* Save the floating point control and status register */ str r1, [r0], #4 /* Save the floating point control and status register */
/* DSA: don't need to inc r0 */ /* DSA: don't need to inc r0 */
#endif /* CONFIG_ARCH_FPU */ #endif /* CONFIG_ARCH_FPU */
@ -132,7 +132,7 @@ longjmp:
ldr r2, [r0], #4 /* Fetch the floating point control and status register */ ldr r2, [r0], #4 /* Fetch the floating point control and status register */
/* DSA: don't need to inc r0 */ /* DSA: don't need to inc r0 */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
#endif /* CONFIG_ARCH_FPU */ #endif /* CONFIG_ARCH_FPU */
mov r0, r1 /* return val */ mov r0, r1 /* return val */

6
libs/libc/machine/arm/armv8-m/gnu/arch_setjmp.S
View File

@ -77,10 +77,10 @@ setjmp:
vstmia r0!, {s16-s31} /* Save the callee-saved FP registers */ vstmia r0!, {s16-s31} /* Save the callee-saved FP registers */
/* Store the floating point control and status register. At the end of the /* Store the floating point control and status register. At the end of the
* vstmia, r0 will point to the FPCSR storage location. * vstmia, r0 will point to the FPSCR storage location.
*/ */
vmrs r1, fpscr /* Fetch the FPCSR */ vmrs r1, fpscr /* Fetch the FPSCR */
str r1, [r0], #4 /* Save the floating point control and status register */ str r1, [r0], #4 /* Save the floating point control and status register */
/* DSA: don't need to inc r0 */ /* DSA: don't need to inc r0 */
#endif /* CONFIG_ARCH_FPU */ #endif /* CONFIG_ARCH_FPU */
@ -132,7 +132,7 @@ longjmp:
ldr r2, [r0], #4 /* Fetch the floating point control and status register */ ldr r2, [r0], #4 /* Fetch the floating point control and status register */
/* DSA: don't need to inc r0 */ /* DSA: don't need to inc r0 */
vmsr fpscr, r2 /* Restore the FPCSR */ vmsr fpscr, r2 /* Restore the FPSCR */
#endif /* CONFIG_ARCH_FPU */ #endif /* CONFIG_ARCH_FPU */
mov r0, r1 /* return val */ mov r0, r1 /* return val */