From c232be541cff92f1df1713a3beb176ddf101d3cf Mon Sep 17 00:00:00 2001 From: "Alan C. Assis" Date: Thu, 17 Mar 2022 16:00:22 -0300 Subject: [PATCH] Add SPIRAM to ESP32-S2 --- arch/xtensa/src/esp32s2/Kconfig | 94 +- arch/xtensa/src/esp32s2/Make.defs | 5 + arch/xtensa/src/esp32s2/esp32s2_psram.c | 725 ++++ arch/xtensa/src/esp32s2/esp32s2_psram.h | 139 + arch/xtensa/src/esp32s2/esp32s2_spiram.c | 380 ++ arch/xtensa/src/esp32s2/esp32s2_spiram.h | 206 ++ arch/xtensa/src/esp32s2/esp32s2_start.c | 88 +- .../src/esp32s2/hardware/esp32s2_efuse.h | 23 + .../src/esp32s2/hardware/esp32s2_extmem.h | 32 + .../xtensa/src/esp32s2/hardware/esp32s2_soc.h | 2 + .../esp32s2/hardware/esp32s2_spi_mem_reg.h | 3165 +++++++++++++++++ .../src/esp32s2/rom/esp32s2_opi_flash.h | 367 ++ .../xtensa/src/esp32s2/rom/esp32s2_spiflash.h | 1020 ++++++ .../esp32s2/esp32s2-saola-1/scripts/Make.defs | 6 - .../esp32s2-saola-1/scripts/esp32s2_rom.ld | 15 +- 15 files changed, 6253 insertions(+), 14 deletions(-) create mode 100644 arch/xtensa/src/esp32s2/esp32s2_psram.c create mode 100644 arch/xtensa/src/esp32s2/esp32s2_psram.h create mode 100644 arch/xtensa/src/esp32s2/esp32s2_spiram.c create mode 100644 arch/xtensa/src/esp32s2/esp32s2_spiram.h create mode 100644 arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h create mode 100644 arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h create mode 100644 arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig index eabe497dba..3f1de8c51a 100644 --- a/arch/xtensa/src/esp32s2/Kconfig +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -92,7 +92,8 @@ config ESP32S2_INSTRUCTION_CACHE_LINE_SIZE choice ESP32S2_DATA_CACHE_SIZE prompt "Data cache size" - default ESP32S2_DATA_CACHE_0KB + default ESP32S2_DATA_CACHE_0KB if !ESP32S2_SPIRAM + default ESP32S2_DATA_CACHE_8KB if ESP32S2_SPIRAM ---help--- Data cache size to be set on application startup. If you use 0KB data cache, the other 16KB will be added to the heap. @@ -100,6 +101,7 @@ choice ESP32S2_DATA_CACHE_SIZE will be added to the heap. config ESP32S2_DATA_CACHE_0KB + depends on !ESP32S2_SPIRAM bool "No DATA CACHE" ---help--- Disable Data Cache @@ -442,6 +444,96 @@ endif endmenu # SPI Flash Configuration +menu "SPI RAM Configuration" + depends on ESP32S2_SPIRAM + +config ESP32S2_DEFAULT_PSRAM_CLK_IO + int "PSRAM CLK pin" + default 30 + +config ESP32S2_DEFAULT_PSRAM_CS_IO + int "PSRAM CS pin" + default 26 + +choice ESP32S2_SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + default ESP32S2_SPIRAM_TYPE_AUTO + +config ESP32S2_SPIRAM_TYPE_AUTO + bool "Auto-detect" + +config ESP32S2_SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config ESP32S2_SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64 or LY68L6400" + +endchoice # ESP32S2_SPIRAM_TYPE + +config ESP32S2_SPIRAM_SIZE + int + default -1 if ESP32S2_SPIRAM_TYPE_AUTO + default 4194304 if ESP32S2_SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if ESP32S2_SPIRAM_TYPE_ESPPSRAM64 + default 0 + +config ESP32S2_SPIRAM_FETCH_INSTRUCTIONS + bool "Cache fetch instructions from SPI RAM" + default n + ---help--- + If enabled, instruction in flash will be copied into SPI RAM. + If ESP32S2_SPIRAM_RODATA is also enabled, you can run the instruction + when erasing or programming the flash. + +config ESP32S2_SPIRAM_RODATA + bool "Cache load read only data from SPI RAM" + default n + ---help--- + If enabled, rodata in flash will be copied into SPI RAM. + If ESP32S2_SPIRAM_FETCH_INSTRUCTIONS is also enabled, + you can run the instruction when erasing or programming the + flash. + +choice ESP32S2_SPIRAM_SPEED + prompt "Set RAM clock speed" + default ESP32S2_SPIRAM_SPEED_40M + ---help--- + Select the speed for the SPI RAM chip. + +config ESP32S2_SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config ESP32S2_SPIRAM_SPEED_80M + bool "80MHz clock speed" + +endchoice # ESP32S2_SPIRAM_SPEED + +config ESP32S2_SPIRAM_SPEED + int + default 80 if ESP32S2_SPIRAM_SPEED_80M + default 40 if ESP32S2_SPIRAM_SPEED_40M + +config ESP32S2_SPIRAM_BOOT_INIT + bool "Initialize SPI RAM during startup" + default "y" + ---help--- + If this is enabled, the SPI RAM will be enabled during initial + boot. Unless you have specific requirements, you'll want to leave + this enabled so memory allocated during boot-up can also be + placed in SPI RAM. + +config ESP32S2_SPIRAM_IGNORE_NOTFOUND + bool "Ignore PSRAM when not found" + default "n" + depends on ESP32S2_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA + ---help--- + Normally, if PSRAM initialization is enabled during compile time + but not found at runtime, it is seen as an error making the CPU + panic. If this is enabled, booting will complete but no PSRAM + will be available. + +endmenu # SPI RAM Configuration + menu "Real-Time Timer Configuration" depends on ESP32S2_RT_TIMER diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs index ed40a7082f..74ddefa0af 100644 --- a/arch/xtensa/src/esp32s2/Make.defs +++ b/arch/xtensa/src/esp32s2/Make.defs @@ -110,3 +110,8 @@ ifeq ($(CONFIG_ONESHOT),y) CHIP_CSRCS += esp32s2_oneshot_lowerhalf.c endif endif + +ifeq ($(CONFIG_ESP32S2_SPIRAM),y) +CHIP_CSRCS += esp32s2_spiram.c +CHIP_CSRCS += esp32s2_psram.c +endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_psram.c b/arch/xtensa/src/esp32s2/esp32s2_psram.c new file mode 100644 index 0000000000..aba01acbb0 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_psram.c @@ -0,0 +1,725 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_psram.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "esp32s2_gpio.h" +#include "esp32s2_psram.h" + +#include "rom/esp32s2_spiflash.h" +#include "rom/esp32s2_opi_flash.h" +#include "hardware/esp32s2_efuse.h" +#include "hardware/esp32s2_spi.h" +#include "hardware/esp32s2_spi_mem_reg.h" +#include "hardware/esp32s2_iomux.h" +#include "hardware/esp32s2_gpio_sigmap.h" + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* EFUSE */ + +#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0) + +/* Commands for PSRAM chip */ + +#define PSRAM_READ 0x03 +#define PSRAM_FAST_READ 0x0B +#define PSRAM_FAST_READ_QUAD 0xEB +#define PSRAM_WRITE 0x02 +#define PSRAM_QUAD_WRITE 0x38 +#define PSRAM_ENTER_QMODE 0x35 +#define PSRAM_EXIT_QMODE 0xF5 +#define PSRAM_RESET_EN 0x66 +#define PSRAM_RESET 0x99 +#define PSRAM_SET_BURST_LEN 0xC0 +#define PSRAM_DEVICE_ID 0x9F + +#define PSRAM_FAST_READ_DUMMY 4 +#define PSRAM_FAST_READ_QUAD_DUMMY 6 + +/* ID */ + +#define PSRAM_ID_KGD_M 0xff +#define PSRAM_ID_KGD_S 8 +#define PSRAM_ID_KGD 0x5d +#define PSRAM_ID_EID_M 0xff +#define PSRAM_ID_EID_S 16 + +/* Use the [7:5](bit7~bit5) of EID to distinguish the psram size: + * + * BIT7 | BIT6 | BIT5 | SIZE(MBIT) + * ------------------------------------- + * 0 | 0 | 0 | 16 + * 0 | 0 | 1 | 32 + * 0 | 1 | 0 | 64 + */ + +#define PSRAM_EID_SIZE_M 0x07 +#define PSRAM_EID_SIZE_S 5 + +#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) +#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) +#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) +#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) + +/* For the old version 32Mbit PSRAM, using the special driver */ + +#define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20) +#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) + +/* IO-pins for PSRAM. + * WARNING: PSRAM shares all but the CS and CLK pins with the flash, so + * these defines hardcode the flash pins as well, making this code + * incompatible with either a setup that has the flash on non-standard + * pins or ESP32S2s with built-in flash. + */ + +#define FLASH_CLK_IO SPI_CLK_GPIO_NUM +#define FLASH_CS_IO SPI_CS0_GPIO_NUM + +/* PSRAM clock and cs IO should be configured based on hardware design. */ + +#define PSRAM_CLK_IO CONFIG_ESP32S2_DEFAULT_PSRAM_CLK_IO /* Default value is 30 */ +#define PSRAM_CS_IO CONFIG_ESP32S2_DEFAULT_PSRAM_CS_IO /* Default value is 26 */ +#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM +#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM +#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM +#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM + +#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M +#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M + +#define PSRAM_IO_MATRIX_DUMMY_20M 0 +#define PSRAM_IO_MATRIX_DUMMY_40M 0 +#define PSRAM_IO_MATRIX_DUMMY_80M 0 +#define _SPI_CACHE_PORT 0 +#define _SPI_FLASH_PORT 1 +#define _SPI_80M_CLK_DIV 1 +#define _SPI_40M_CLK_DIV 2 +#define _SPI_20M_CLK_DIV 4 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef enum +{ + PSRAM_CLK_MODE_NORM = 0, /* Normal SPI mode */ + PSRAM_CLK_MODE_A1C, /* ONE extra clock cycles after CS is set high level */ + PSRAM_CLK_MODE_A2C, /* Two extra clock cycles after CS is set high level */ + PSRAM_CLK_MODE_ALON, /* clock always on */ + PSRAM_CLK_MODE_MAX, +} psram_clk_mode_t; + +typedef enum +{ + PSRAM_EID_SIZE_16MBITS = 0, + PSRAM_EID_SIZE_32MBITS = 1, + PSRAM_EID_SIZE_64MBITS = 2, +} psram_eid_size_t; + +typedef struct +{ + uint8_t flash_clk_io; + uint8_t flash_cs_io; + uint8_t psram_clk_io; + uint8_t psram_cs_io; + uint8_t psram_spiq_sd0_io; + uint8_t psram_spid_sd1_io; + uint8_t psram_spiwp_sd3_io; + uint8_t psram_spihd_sd2_io; +} psram_io_t; + +#define PSRAM_IO_CONF_DEFAULT() { \ + .flash_clk_io = FLASH_CLK_IO, \ + .flash_cs_io = FLASH_CS_IO, \ + .psram_clk_io = PSRAM_CLK_IO, \ + .psram_cs_io = PSRAM_CS_IO, \ + .psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO, \ + .psram_spid_sd1_io = PSRAM_SPID_SD1_IO, \ + .psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO, \ + .psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \ +} + +typedef enum +{ + PSRAM_SPI_1 = 0x1, + PSRAM_SPI_MAX , +} psram_spi_num_t; + +typedef enum +{ + PSRAM_CMD_QPI, + PSRAM_CMD_SPI, +} psram_cmd_mode_t; + +static uint32_t g_psram_id; + +static uint8_t g_psram_cs_io = UINT8_MAX; + +extern uint32_t esp_rom_efuse_get_flash_gpio_info(void); +extern uint32_t esp_rom_efuse_get_flash_wp_gpio(void); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void IRAM_ATTR psram_cache_init(int psram_cache_mode, int vaddrmode); + +uint8_t psram_get_cs_io(void) +{ + return g_psram_cs_io; +} + +static void psram_set_op_mode(int spi_num, int mode) +{ + if (mode == PSRAM_CMD_QPI) + { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE); + SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); + } + else if (mode == PSRAM_CMD_SPI) + { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE); + } +} + +static void _psram_exec_cmd(int spi_num, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, uint8_t *mosi_data, + int mosi_bit_len, uint8_t *miso_data, + int miso_bit_len) +{ + esp_rom_spi_cmd_t conf; + uint32_t _addr = addr; + conf.addr = &_addr; + conf.addr_bit_len = addr_bit_len; + conf.cmd = cmd; + conf.cmd_bit_len = cmd_bit_len; + conf.dummy_bit_len = dummy_bits; /* There is a hw approach on chip723 */ + conf.tx_data = (uint32_t *)mosi_data; + conf.tx_data_bit_len = mosi_bit_len; + conf.rx_data = (uint32_t *)miso_data; + conf.rx_data_bit_len = miso_bit_len; + esp_rom_spi_cmd_config(spi_num, &conf); +} + +void psram_exec_cmd(int spi_num, int mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, uint8_t *mosi_data, + int mosi_bit_len, uint8_t *miso_data, + int miso_bit_len, uint32_t cs_mask, + bool is_write_erase_operation) +{ + uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); + uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); + uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); + uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); + + psram_set_op_mode(spi_num, mode); + _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, + addr_bit_len, dummy_bits, mosi_data, + mosi_bit_len, miso_data, miso_bit_len); + + esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, + cs_mask, is_write_erase_operation); + + WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); + WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); + WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); + WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); +} + +/* exit QPI mode(set back to SPI mode) */ + +static void psram_disable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_QPI, + PSRAM_EXIT_QMODE, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* if is program/erase operation */ +} + +/* switch psram burst length(32 bytes or 1024 bytes) + * datasheet says it should be 1024 bytes by default + */ + +static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode) +{ + psram_exec_cmd(spi_num, mode, + PSRAM_SET_BURST_LEN, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* if is program/erase operation */ +} + +/* send reset command to psram, in spi mode */ + +static void psram_reset_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET_EN, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ + + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int psram_enable_wrap(uint32_t wrap_size) +{ + static uint32_t current_wrap_size; + + if (current_wrap_size == wrap_size) + { + return OK; + } + + switch (wrap_size) + { + case 0: + case 32: + psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI); + current_wrap_size = wrap_size; + return OK; + case 16: + case 64: + default: + return -EFAULT; + } +} + +bool psram_support_wrap_size(uint32_t wrap_size) +{ + switch (wrap_size) + { + case 0: + case 32: + return true; + case 16: + case 64: + default: + return false; + } +} + +/* Read ID operation only supports SPI CMD and mode, should issue + * `psram_disable_qio_mode` before calling this + */ + +static void psram_read_id(int spi_num, uint32_t *dev_id) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_DEVICE_ID, 8, /* command and command bit len */ + 0, 24, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + (uint8_t *) dev_id, 24, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/* enter QPI mode */ + +static void IRAM_ATTR psram_enable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_ENTER_QMODE, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode) +{ + if (clk_mode == PSRAM_CLK_MODE_NORM) + { + /* SPI1 Flash Operation port */ + + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), + SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); + + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), + SPI_MEM_CS_SETUP_TIME_V, 0, + SPI_MEM_CS_SETUP_TIME_S); + + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), + SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } + else + { + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), + SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } +} + +static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode) +{ + if (clk_mode == PSRAM_CLK_MODE_NORM) + { + /* SPI0 SRAM Cache port */ + + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), + SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, + SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), + SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, + SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), + SPI_MEM_SPI_SMEM_CS_HOLD_M | + SPI_MEM_SPI_SMEM_CS_SETUP_M); + + /* SPI0 Flash Cache port */ + + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), + SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), + SPI_MEM_CS_SETUP_TIME_V, 0, + SPI_MEM_CS_SETUP_TIME_S); + + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), + SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } + else + { + CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), + SPI_CS_HOLD_M | SPI_CS_SETUP_M); + } +} + +/* psram gpio init, different working frequency we have different + * solutions + */ + +static void IRAM_ATTR psram_gpio_config(void) +{ + psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT(); + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) + { + /* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */ + } + else + { + /* FLASH pins are all configured via GPIO matrix in ROM. */ + + psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig); + psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig); + psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig); + psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig); + psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig); + psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio(); + } + + esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig); + g_psram_cs_io = psram_io.psram_cs_io; +} + +int psram_get_size(void) +{ + int psram_size = PSRAM_SIZE_ID(g_psram_id); + + if (PSRAM_IS_64MBIT_TRIAL(g_psram_id)) + { + return PSRAM_SIZE_8MB; + } + + switch (psram_size) + { + case PSRAM_EID_SIZE_64MBITS: + return PSRAM_SIZE_8MB; + + case PSRAM_EID_SIZE_32MBITS: + return PSRAM_SIZE_4MB; + + case PSRAM_EID_SIZE_16MBITS: + return PSRAM_SIZE_2MB; + + default: + return PSRAM_SIZE_16MB; + } +} + +/* used in UT only */ + +bool psram_is_32mbit_ver0(void) +{ + return PSRAM_IS_32MBIT_VER0(g_psram_id); +} + +static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode) +{ + if (spi_num == _SPI_CACHE_PORT) + { + REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, clk_mode); + } + else + if (spi_num == _SPI_FLASH_PORT) + { + REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, clk_mode); + } +} + +/* PSRAM Mode init will overwrite original flash speed mode, so that it is + * possible to change psram and flash speed after OTA. + * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is + * decided by bootloader, OTA can not change this mode. + */ + +int IRAM_ATTR psram_enable(int mode, int vaddrmode) +{ + int spi_num = PSRAM_SPI_1; + psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX; + + DEBUGASSERT(mode < PSRAM_CACHE_MAX); + + /* GPIO related settings */ + + psram_gpio_config(); + + /* SPI1: set spi1 clk mode, in order to send commands on SPI1 */ + + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C); + + /* SPI1: set cs timing(hold time) in order to send commands on SPI1 */ + + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C); + + psram_disable_qio_mode(spi_num); + psram_read_id(spi_num, &g_psram_id); + + if (!PSRAM_IS_VALID(g_psram_id)) + { + /* 16Mbit psram ID read error workaround: + * treat the first read id as a dummy one as the pre-condition, + * Send Read ID command again + */ + + psram_read_id(spi_num, &g_psram_id); + + if (!PSRAM_IS_VALID(g_psram_id)) + { + merr("PSRAM ID read error: 0x%08x", g_psram_id); + return -ENODEV; + } + } + + if (psram_is_32mbit_ver0()) + { + /* SPI1: keep clock mode and cs timing for spi1 */ + + clk_mode = PSRAM_CLK_MODE_A1C; + } + else + { + /* For other psram, we don't need any extra clock cycles after + * cs get back to high level + */ + + clk_mode = PSRAM_CLK_MODE_NORM; + + /* SPI1: set clock mode and cs timing to normal mode */ + + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); + } + + /* SPI1: send psram reset command */ + + psram_reset_mode(PSRAM_SPI_1); + + /* SPI1: send QPI enable command */ + + psram_enable_qio_mode(PSRAM_SPI_1); + + /* after sending commands, set spi1 clock mode and cs timing to + * normal mode. Since all the operations are sent via SPI0 Cache + */ + + /* SPI1: set clock mode to normal mode. */ + + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); + + /* SPI1: set cs timing to normal */ + + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); + + /* SPI0: set spi0 clock mode */ + + psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode); + + /* SPI0: set spi0 flash/cache cs timing */ + + psram_set_spi0_cache_cs_timing(clk_mode); + + /* SPI0: init SPI commands for Cache */ + + psram_cache_init(mode, vaddrmode); + + return OK; +} + +static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv) +{ + uint32_t freqbits; + + if (1 >= freqdiv) + { + WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); + } + else + { + freqbits = (((freqdiv - 1) << SPI_MEM_SCLKCNT_N_S)) | + (((freqdiv / 2 - 1) << SPI_MEM_SCLKCNT_H_S)) | + (((freqdiv - 1) << SPI_MEM_SCLKCNT_L_S)); + + WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits); + } +} + +/* register initialization for sram cache params and r/w commands */ + +static void IRAM_ATTR psram_cache_init(int psram_cache_mode, + int vaddrmode) +{ + int extra_dummy = 0; + + switch (psram_cache_mode) + { + case PSRAM_CACHE_S80M: + psram_clock_set(0, 1); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M; + break; + case PSRAM_CACHE_S40M: + psram_clock_set(0, 2); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M; + break; + case PSRAM_CACHE_S26M: + psram_clock_set(0, 3); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M; + break; + case PSRAM_CACHE_S20M: + psram_clock_set(0, 4); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M; + break; + default: + psram_clock_set(0, 2); + break; + } + + /* disable dio mode for cache command */ + + CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_USR_SRAM_DIO_M); + + /* enable qio mode for cache command */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); + + /* enable cache read command */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_CACHE_SRAM_USR_RCMD_M); + + /* enable cache write command */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_CACHE_SRAM_USR_WCMD_M); + + /* write address for cache command */ + + SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_SRAM_ADDR_BITLEN_V, 23, + SPI_MEM_SRAM_ADDR_BITLEN_S); + + /* enable cache read dummy */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); + + /* config sram cache r/w command */ + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); /* 0x38 */ + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S); + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, + PSRAM_FAST_READ_QUAD, + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); /* 0x0b */ + + /* dummy, psram cache : 40m--+1dummy,80m--+2dummy */ + + SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, + PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy, + SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); + + /* ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) */ + + CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_psram.h b/arch/xtensa/src/esp32s2/esp32s2_psram.h new file mode 100644 index 0000000000..b56114a942 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_psram.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_psram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PSRAM_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PSRAM_H + +#define PSRAM_SIZE_2MB (2 * 1024 * 1024) +#define PSRAM_SIZE_4MB (4 * 1024 * 1024) +#define PSRAM_SIZE_8MB (8 * 1024 * 1024) +#define PSRAM_SIZE_16MB (16 * 1024 * 1024) +#define PSRAM_SIZE_32MB (32 * 1024 * 1024) + +#define PSRAM_SIZE_16MBITS 0 +#define PSRAM_SIZE_32MBITS 1 +#define PSRAM_SIZE_64MBITS 2 +#define PSRAM_SIZE_MAX 3 + +#define PSRAM_CACHE_S80M 1 +#define PSRAM_CACHE_S40M 2 +#define PSRAM_CACHE_S26M 3 +#define PSRAM_CACHE_S20M 4 +#define PSRAM_CACHE_MAX 5 + +#define SPIRAM_WRAP_MODE_16B 0 +#define SPIRAM_WRAP_MODE_32B 1 +#define SPIRAM_WRAP_MODE_64B 2 +#define SPIRAM_WRAP_MODE_DISABLE 3 + +/* See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the + * definitions of these modes. Important is that NORMAL works with the + * cache disabled. + */ + +#define PSRAM_VADDR_MODE_NORMAL 0 /* CPU use their own flash + * cache for external RAM access + */ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: psram_get_physical_size + * + * Description: + * Get the physical psram size in bytes. + * + ****************************************************************************/ + +int psram_get_physical_size(uint32_t *out_size_bytes); + +/**************************************************************************** + * Name: psram_get_available_size + * + * Description: + * Get the available physical psram size in bytes. + * + * If ECC is enabled, available PSRAM size will be 15/16 times its + * physical size. If not, it equals to the physical psram size. + * Note: For now ECC is only enabled on ESP32S2 Octal PSRAM + * + * Input Parameters: + * out_size_bytes - availabe physical psram size in bytes. + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +int psram_get_available_size(uint32_t *out_size_bytes); + +/**************************************************************************** + * Name: psram_get_available_size + * + * Description: + * Enable psram cache + * + * Esp-idf uses this to initialize cache for psram, mapping it into the + * main memory address space. + * + * Input Parameters: + * mode - SPI mode to access psram in. + * vaddrmode - Mode the psram cache works in. + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +int psram_enable(int mode, int vaddrmode); + +/**************************************************************************** + * Name: psram_get_cs_io + * + * Description: + * Get the psram CS IO + * + * Returned Value: + * The psram CS IO pin. + * + ****************************************************************************/ + +uint8_t psram_get_cs_io(void); + +/**************************************************************************** + * Name: psram_get_size + * + * Description: + * Return size of PSRAM in bytes + * + * Returned Value: + * PSRAM size in bytes + * + ****************************************************************************/ + +int psram_get_size(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PSRAM_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiram.c b/arch/xtensa/src/esp32s2/esp32s2_spiram.c new file mode 100644 index 0000000000..d76a636a52 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_spiram.c @@ -0,0 +1,380 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_spiram.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xtensa.h" +#include "xtensa_attr.h" +#include "esp32s2_psram.h" +#include "esp32s2_spiram.h" +#include "hardware/esp32s2_soc.h" +#include "hardware/esp32s2_cache_memory.h" +#include "hardware/esp32s2_extmem.h" +#include "hardware/esp32s2_iomux.h" + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL + +#if defined(CONFIG_ESP32S2_SPIRAM) + +#define MMU_PAGE_TO_BYTES(page_id) ((page_id) << 16) +#define BYTES_TO_MMU_PAGE(bytes) ((bytes) / MMU_PAGE_SIZE) + +#if defined(CONFIG_ESP32S2_SPIRAM_SPEED_40M) +# define PSRAM_SPEED PSRAM_CACHE_S40M +#else /* #if CONFIG_ESP32S2_SPIRAM_SPEED_80M */ +# define PSRAM_SPEED PSRAM_CACHE_S80M +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +static bool g_spiram_inited; + +/* These variables are in bytes */ + +static uint32_t g_allocable_vaddr_start; +static uint32_t g_allocable_vaddr_end; +static DRAM_ATTR uint32_t g_mapped_vaddr_start; + +#if defined(CONFIG_ESP32S2_SPIRAM_FETCH_INSTRUCTIONS) +static int g_instr_flash2spiram_offs; +static uint32_t g_instr_start_page; +static uint32_t g_instr_end_page; +#endif + +#if defined(CONFIG_ESP32S2_SPIRAM_RODATA) +static int g_rodata_flash2spiram_offs; +static uint32_t g_rodata_start_page; +static uint32_t g_rodata_end_page; +#endif + +#if defined(CONFIG_ESP32S2_SPIRAM_FETCH_INSTRUCTIONS) || \ + defined(CONFIG_ESP32S2_SPIRAM_RODATA) +static uint32_t page0_mapped; +static uint32_t page0_page = INVALID_PHY_PAGE; +#endif + +/* Let's export g_mapped_size to export heap */ + +DRAM_ATTR uint32_t g_mapped_size; + +/**************************************************************************** + * ROM Function Prototypes + ****************************************************************************/ + +extern void cache_writeback_all(void); +extern uint32_t cache_suspend_dcache(void); +extern void cache_resume_dcache(uint32_t val); +extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, + uint32_t paddr, uint32_t psize, + uint32_t num, uint32_t fixed); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mmu_map_psram + * + * Description: + * Map the PSRAM to MMU + * + * Input Parameters: + * start_paddr - start of physical PSRAM address + * end_paddr - end of physical PSRAM address + * out_start_vaddr - start of virtual address + * + * Returned Value: + * Zero value (OK) on success or a negative error. + * + ****************************************************************************/ + +int mmu_map_psram(uint32_t start_paddr, uint32_t end_paddr, + uint32_t *out_start_vaddr) +{ + /* For now, this function should only run when virtual address is enough + * Decide these logics when there's a real PSRAM with larger size + */ + + uint32_t map_length = end_paddr - start_paddr; + + if (map_length > SOC_EXTRAM_DATA_SIZE) + { + /* Decide these logics when there's a real PSRAM with larger size */ + + merr("PSRAM physical size is too large, not support mapping it yet!"); + return -ENOMEM; + } + + /* should be MMU page aligned */ + + assert((start_paddr % MMU_PAGE_SIZE) == 0); + + uint32_t start_vaddr = DPORT_CACHE_ADDRESS_LOW; + uint32_t end_vaddr = start_vaddr + map_length; + uint32_t cache_bus_mask = 0; + + cache_bus_mask |= (end_vaddr > 0) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0; + cache_bus_mask |= (end_vaddr >= DPORT_ADDRESS_HIGH) ? + EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0; + cache_bus_mask |= (end_vaddr >= DRAM1_ADDRESS_HIGH) ? + EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; + + assert(end_vaddr <= DRAM0_CACHE_ADDRESS_HIGH); + + minfo("start_paddr is %x, map_length is %xB, %d pages", + start_paddr, map_length, BYTES_TO_MMU_PAGE(map_length)); + + /* No need to disable cache, this file is put in Internal RAM */ + + cache_dbus_mmu_set(MMU_ACCESS_SPIRAM, start_vaddr, start_paddr, 64, + BYTES_TO_MMU_PAGE(map_length), 0); + + REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, cache_bus_mask); + + *out_start_vaddr = start_vaddr; + + return OK; +} + +/**************************************************************************** + * Name: mmu_map_psram + * + * Description: + * Initialize the CACHE to use with PSRAM + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_spiram_init_cache(void) +{ + int ret; + uint32_t start_page = 0; + + g_mapped_size = esp_spiram_get_size(); + + /* Map the PSRAM physical range to MMU */ + + ret = mmu_map_psram(MMU_PAGE_TO_BYTES(start_page), + MMU_PAGE_TO_BYTES(start_page) + + g_mapped_size, &g_mapped_vaddr_start); + if (ret < 0) + { + merr("MMU PSRAM mapping wrong!"); + abort(); + } + + /* After mapping, we DON'T care about the PSRAM PHYSICAL + * ADDRESSS ANYMORE! + */ + + g_allocable_vaddr_start = g_mapped_vaddr_start; + g_allocable_vaddr_end = g_mapped_vaddr_start + g_mapped_size; +} + +/**************************************************************************** + * Name: esp_spiram_test + * + * Description: + * Simple RAM test. Writes a word every 32 bytes. Takes about a second + * to complete for 4MiB. Returns true when RAM seems OK, false when test + * fails. WARNING: Do not run this before the 2nd cpu has been initialized + * (in a two-core system) or after the heap allocator has taken ownership + * of the memory. + * + * Input Parameters: + * None + * + * Returned Value: + * True on success or False on failure + * + ****************************************************************************/ + +bool esp_spiram_test(void) +{ + volatile int *spiram = (volatile int *)g_mapped_vaddr_start; + + size_t s = g_mapped_size; + size_t p; + int errct = 0; + int initial_err = -1; + + for (p = 0; p < (s / sizeof(int)); p += 8) + { + spiram[p] = p ^ 0xaaaaaaaa; + } + + for (p = 0; p < (s / sizeof(int)); p += 8) + { + if (spiram[p] != (p ^ 0xaaaaaaaa)) + { + errct++; + if (errct == 1) + { + initial_err = p * sizeof(int); + } + + if (errct < 4) + { + merr("SPI SRAM error @ %08x:%08x/%08x \n", &spiram[p], + spiram[p], p ^ 0xaaaaaaaa); + } + } + } + + if (errct != 0) + { + merr("SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", + errct, s / 32, initial_err + SOC_EXTRAM_DATA_LOW); + return false; + } + else + { + minfo("SPI SRAM memory test OK!"); + return true; + } +} + +#if defined(CONFIG_ESP32S2_SPIRAM_RODATA) +void rodata_flash_page_info_init(void) +{ + uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - + ((uint32_t)&_rodata_reserved_start & + ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / + MMU_PAGE_SIZE; + + g_rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + + CACHE_DROM_MMU_START); + g_rodata_start_page &= MMU_ADDRESS_MASK; + g_rodata_end_page = g_rodata_start_page + rodata_page_cnt - 1; +} + +uint32_t IRAM_ATTR rodata_flash_start_page_get(void) +{ + return g_rodata_start_page; +} + +uint32_t IRAM_ATTR rodata_flash_end_page_get(void) +{ + return g_rodata_end_page; +} + +int IRAM_ATTR g_rodata_flash2spiram_offset(void) +{ + return g_rodata_flash2spiram_offs; +} +#endif + +int esp_spiram_init(void) +{ + int r; + size_t spiram_size; + + r = psram_enable(PSRAM_SPEED, PSRAM_MODE); + if (r != OK) + { + merr("SPI RAM enabled but initialization failed. Bailing out.\n"); + return r; + } + + g_spiram_inited = true; + + spiram_size = esp_spiram_get_size(); + +#if defined(CONFIG_ESP32S2_SPIRAM_SIZE) && (CONFIG_ESP32S2_SPIRAM_SIZE != -1) + if (spiram_size != CONFIG_ESP32S2_SPIRAM_SIZE) + { + merr("Expected %dMB chip but found %dMB chip. Bailing out..", + (CONFIG_ESP32S2_SPIRAM_SIZE / 1024 / 1024), + (spiram_size / 1024 / 1024)); + return; + } +#endif + + minfo("Found %dMB SPI RAM device\n", spiram_size / (1024 * 1024)); + minfo("Speed: %dMHz\n", CONFIG_ESP32S2_SPIRAM_SPEED); + minfo("Initialized, cache is in normal (1-core) mode.\n"); + return OK; +} + +size_t esp_spiram_get_size(void) +{ + if (!g_spiram_inited) + { + merr("SPI RAM not initialized"); + abort(); + } + + return psram_get_size(); +} + +/* Before flushing the cache, if psram is enabled as a memory-mapped thing, + * we need to write back the data in the cache to the psram first, otherwise + * it will get lost. For now, we just read 64/128K of random PSRAM memory to + * do this. + */ + +void IRAM_ATTR esp_spiram_writeback_cache(void) +{ + cache_writeback_all(); +} + +/** + * @brief If SPI RAM(PSRAM) has been initialized + * + * @return true SPI RAM has been initialized successfully + * @return false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void) +{ + return g_spiram_inited; +} + +uint8_t esp_spiram_get_cs_io(void) +{ + return psram_get_cs_io(); +} + +#endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiram.h b/arch/xtensa/src/esp32s2/esp32s2_spiram.h new file mode 100644 index 0000000000..39b1af0f93 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_spiram.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_spiram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_SPIRAM_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_SPIRAM_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* @brief Initialize spiram interface/hardware. Normally called from + * cpu_start.c. + * + * @return ESP_OK on success + */ + +int esp_spiram_init(void); + +/** + * @brief Configure Cache/MMU for access to external SPI RAM. + * + * Normally this function is called from cpu_start, if + * CONFIG_SPIRAM_BOOT_INIT option is enabled. Applications which need to + * enable SPI RAM at run time can disable CONFIG_SPIRAM_BOOT_INIT, and + * call this function later. + * + * @attention this function must be called with flash cache disabled. + */ + +void esp_spiram_init_cache(void); + +/** + * @brief Memory test for SPI RAM. Should be called after SPI RAM is + * initialized and (in case of a dual-core system) the app CPU is online. + * This test overwrites the memory with crap, so do not call after e.g. the + * heap allocator has stored important stuff in SPI RAM. + * + * @return true on success, false on failed memory test + */ + +bool esp_spiram_test(void); + +/** + * @brief Add the initialized SPI RAM to the heap allocator. + */ + +int esp_spiram_add_to_heapalloc(void); + +/** + * @brief Get the available physical size of the attached SPI RAM chip + * + * @note If ECC is enabled, the available physical size would be smaller + * than the physical size. See `CONFIG_SPIRAM_ECC_ENABLE` + * + * @return Size in bytes, or 0 if no external RAM chip support compiled in. + */ + +size_t esp_spiram_get_size(void); + +/** + * @brief Force a writeback of the data in the SPI RAM cache. This is to be + * called whenever cache is disabled, because disabling cache on the ESP32 + * discards the data in the SPI RAM cache. + * + * This is meant for use from within the SPI flash code. + */ + +void esp_spiram_writeback_cache(void); + +/** + * @brief If SPI RAM(PSRAM) has been initialized + * + * @return + * - true SPI RAM has been initialized successfully + * - false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void); + +/** + * @brief get psram CS IO + * + * This interface should be called after PSRAM is enabled, otherwise it will + * return an invalid value -1/0xff. + * + * @return psram CS IO or -1/0xff if psram not enabled + */ + +uint8_t esp_spiram_get_cs_io(void); + +/** + * @brief Reserve a pool of internal memory for specific DMA/internal + * allocations + * + * @param size Size of reserved pool in bytes + * + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM when no memory available for pool + */ + +int esp_spiram_reserve_dma_pool(size_t size); + +/** + * @brief If SPI RAM(PSRAM) has been initialized + * + * @return + * - true SPI RAM has been initialized successfully + * - false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void); + +#if defined(CONFIG_ESP32S2_SPIRAM_FETCH_INSTRUCTIONS) + +extern int _instruction_reserved_start; +extern int _instruction_reserved_end; + +/** + * @brief Get the start page number of the instruction in SPI flash + * + * @return start page number + */ + +uint32_t instruction_flash_start_page_get(void); + +/** + * @brief Get the end page number of the instruction in SPI flash + * + * @return end page number + */ + +uint32_t instruction_flash_end_page_get(void); + +/** + * @brief Get the offset of instruction from SPI flash to SPI RAM + * + * @return instruction offset + */ + +int instruction_flash2spiram_offset(void); + +#endif + +#if defined(CONFIG_SPIRAM_RODATA) + +extern int _rodata_reserved_start; +extern int _rodata_reserved_end; + +/** + * @brief Get the start page number of the rodata in SPI flash + * + * @return start page number + */ + +uint32_t rodata_flash_start_page_get(void); + +/** + * @brief Get the end page number of the rodata in SPI flash + * + * @return end page number + */ + +uint32_t rodata_flash_end_page_get(void); + +/** + * @brief Get the offset number of rodata from SPI flash to SPI RAM + * + * @return rodata offset + */ + +int rodata_flash2spiram_offset(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.c b/arch/xtensa/src/esp32s2/esp32s2_start.c index addf53a46c..eddd9fc3b4 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_start.c +++ b/arch/xtensa/src/esp32s2/esp32s2_start.c @@ -37,6 +37,7 @@ #include "hardware/esp32s2_extmem.h" #include "esp32s2_clockconfig.h" #include "esp32s2_region.h" +#include "esp32s2_spiram.h" #include "esp32s2_start.h" #include "esp32s2_lowputc.h" #include "esp32s2_wdt.h" @@ -110,6 +111,9 @@ typedef enum CACHE_LINE_SIZE_64B = 2, /* 64 Byte cache line size */ } cache_line_size_t; +#define CACHE_SIZE_8KB CACHE_SIZE_HALF +#define CACHE_SIZE_16KB CACHE_SIZE_FULL + /**************************************************************************** * ROM Function Prototypes ****************************************************************************/ @@ -123,13 +127,18 @@ extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, extern uint32_t cache_suspend_icache(void); extern void cache_resume_icache(uint32_t val); +extern void cache_invalidate_dcache_all(void); extern void cache_invalidate_icache_all(void); +extern void cache_set_dcache_mode(cache_size_t cache_size, cache_ways_t ways, + cache_line_size_t cache_line_size); extern void cache_set_icache_mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); extern void cache_allocate_sram(cache_layout_t sram0_layout, cache_layout_t sram1_layout, cache_layout_t sram2_layout, cache_layout_t sram3_layout); +extern void esp_config_data_cache_mode(void); +extern void cache_enable_dcache(uint32_t autoload); /**************************************************************************** * Private Function Prototypes @@ -160,6 +169,62 @@ uint32_t g_idlestack[IDLETHREAD_STACKWORDS] * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp_config_data_cache_mode + * + * Description: + * Configure the data cache mode to use with PSRAM. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +IRAM_ATTR void esp_config_data_cache_mode(void) +{ + cache_size_t cache_size; + cache_ways_t cache_ways; + cache_line_size_t cache_line_size; + +#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB) +#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB) + cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, + CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID); + cache_size = CACHE_SIZE_8KB; +#else + cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, + CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID); + cache_size = CACHE_SIZE_16KB; +#endif +#else +#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB) + cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, + CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID); + cache_size = CACHE_SIZE_8KB; +#else + cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, + CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH); + cache_size = CACHE_SIZE_16KB; +#endif +#endif + + cache_ways = CACHE_4WAYS_ASSOC; +#if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B) + cache_line_size = CACHE_LINE_SIZE_16B; +#else + cache_line_size = CACHE_LINE_SIZE_32B; +#endif + merr("Data cache \t\t: size %dKB, %dWays, cache line size %dByte", + cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, + cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32); + + cache_set_dcache_mode(cache_size, cache_ways, cache_line_size); + cache_invalidate_dcache_all(); +} + /**************************************************************************** * Name: configure_cpu_caches * @@ -196,7 +261,7 @@ static void IRAM_ATTR configure_cpu_caches(void) cache_ways = CACHE_4WAYS_ASSOC; -#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B +#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B) cache_line_size = CACHE_LINE_SIZE_16B; #else cache_line_size = CACHE_LINE_SIZE_32B; @@ -206,6 +271,11 @@ static void IRAM_ATTR configure_cpu_caches(void) cache_set_icache_mode(cache_size, cache_ways, cache_line_size); cache_invalidate_icache_all(); cache_resume_icache(0); + +#if defined(CONFIG_ESP32S2_SPIRAM_BOOT_INIT) + esp_config_data_cache_mode(); + cache_enable_dcache(0); +#endif } /**************************************************************************** @@ -285,6 +355,22 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void) showprogress('A'); +#if defined(CONFIG_ESP32S2_SPIRAM_BOOT_INIT) + if (esp_spiram_init() != OK) + { +# if defined(CONFIG_ESP32S2_SPIRAM_IGNORE_NOTFOUND) + mwarn("SPIRAM Initialization failed!\n"); +# else + PANIC(); +# endif + } + else + { + esp_spiram_init_cache(); + esp_spiram_test(); + } +#endif + /* Initialize onboard resources */ esp32s2_board_initialize(); diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h index 0cc076b5d2..b02af55ef2 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h @@ -3279,4 +3279,27 @@ #define EFUSE_EFUSE_DATE_V 0xFFFFFFFF #define EFUSE_EFUSE_DATE_S 0 +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + #endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h index 96873dc81e..8c461c13df 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h @@ -66,4 +66,36 @@ #define EXTMEM_PRO_ICACHE_MASK_IRAM1 EXTMEM_PRO_ICACHE_MASK_BUS1 #define EXTMEM_PRO_ICACHE_MASK_DROM0 EXTMEM_PRO_ICACHE_MASK_BUS2 +#define EXTMEM_PRO_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) + +/* EXTMEM_PRO_DCACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */ + +/* Description: The bit is used to disable dbus2 0: enable 1: disable */ + +#define EXTMEM_PRO_DCACHE_MASK_BUS2 (BIT(2)) +#define EXTMEM_PRO_DCACHE_MASK_BUS2_M (BIT(2)) +#define EXTMEM_PRO_DCACHE_MASK_BUS2_V 0x1 +#define EXTMEM_PRO_DCACHE_MASK_BUS2_S 2 + +/* EXTMEM_PRO_DCACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ + +/* Description: The bit is used to disable dbus1 0: enable 1: disable */ + +#define EXTMEM_PRO_DCACHE_MASK_BUS1 (BIT(1)) +#define EXTMEM_PRO_DCACHE_MASK_BUS1_M (BIT(1)) +#define EXTMEM_PRO_DCACHE_MASK_BUS1_V 0x1 +#define EXTMEM_PRO_DCACHE_MASK_BUS1_S 1 + +/* EXTMEM_PRO_DCACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +/* description: The bit is used to disable dbus0 0: enable 1: disable */ + +#define EXTMEM_PRO_DCACHE_MASK_BUS0 (BIT(0)) +#define EXTMEM_PRO_DCACHE_MASK_BUS0_M (BIT(0)) +#define EXTMEM_PRO_DCACHE_MASK_BUS0_V 0x1 +#define EXTMEM_PRO_DCACHE_MASK_BUS0_S 0 +#define EXTMEM_PRO_DCACHE_MASK_DRAM0 EXTMEM_PRO_DCACHE_MASK_BUS0 +#define EXTMEM_PRO_DCACHE_MASK_DRAM1 EXTMEM_PRO_DCACHE_MASK_BUS1 +#define EXTMEM_PRO_DCACHE_MASK_DPORT EXTMEM_PRO_DCACHE_MASK_BUS2 + #endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EXTMEM_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h index 819d2c348f..4850a3a128 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h @@ -299,6 +299,8 @@ #define SOC_EXTRAM_DATA_LOW 0x3f500000 #define SOC_EXTRAM_DATA_HIGH 0x3ff80000 +#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) + /* Virtual address 0 */ #define VADDR0_START_ADDR SOC_DROM_LOW diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h new file mode 100644 index 0000000000..ebf0f7bbeb --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h @@ -0,0 +1,3165 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_spi_mem_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_MEM_REG_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_MEM_REG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) + +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: Read flash enable. Read flash operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 + +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Write flash enable. Write enable command will be sent when + * the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 + +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Write flash disable. Write disable command will be sent when + * the bit is set. The bit will be cleared once the operation done. 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 + +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Read JEDEC ID . Read ID command will be sent when the bit is + * set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 + +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Read status register-1. Read status operation will be + * triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 + +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: Write status register enable. Write status operation will + * be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0:disable. + */ + +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 + +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: Page program enable(1 byte ~256 bytes data to be programmed). + * Page program operation will be triggered when the bit is set. The bit + * will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 + +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: Sector erase enable(4KB). Sector erase operation will be + * triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 + +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: Block erase enable(32KB) . Block erase operation will be + * triggered when the bit is set. The bit will be cleared once the operation + * done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 + +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: Chip erase enable. Chip erase operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 + +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: Drive Flash into power down. An operation will be triggered + * when the bit is set. The bit will be cleared once the operation done.1: + * enable 0: disable. + */ + +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 + +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: This bit combined with SPI_MEM_RESANDRES bit releases Flash + * from the power-down state or high performance mode and obtains the devices + * ID. The bit will be cleared once the operation done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 + +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: Drive Flash into high performance mode. The bit will be + * cleared once the operation done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 + +/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: User define command enable. An operation will be triggered + * when the bit is set. The bit will be cleared once the operation done.1: + * enable 0: disable. + */ + +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 +#define SPI_MEM_USR_S 18 + +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: In user mode, it is set to indicate that program/erase + * operation will be triggered. The bit is combined with SPI_MEM_USR bit. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 + +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) + +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: In user mode, it is the memory address. other then the + * bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a + * transfer. + */ + +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) + +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: In hardware 0xEB read operation, ADDR phase and DIN phase + * apply 4 signals(4-bit-mode). + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 + +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: In hardware 0xBB read operation, ADDR phase and DIN phase + * apply 2 signals(2-bit-mode). + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 + +/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: Two bytes data will be written to status register when it is + * set. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 + +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ + +/* Description: Write protect signal output when SPI is idle. + * 1: output high, + * 0: output low. + */ + +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 + +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: In hardware 0x6B read operation, DIN phase apply 4 + * signals(4-bit-mode). + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 + +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ + +/* Description: The bit is used to set MOSI line polarity, + * 1: high + * 0: low + */ + +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 + +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ + +/* Description: The bit is used to set MISO line polarity + * 1: high + * 0: low + */ + +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 + +/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ + +/* Description: The Device ID is read out to SPI_MEM_RD_STATUS register, this + * bit combine with spi_mem_flash_res bit. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 + +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: In hardware 0x3B read operation, DIN phase apply 2 signals. + * 1: enable + * 0: disable + */ + +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 + +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ + +/* Description: This bit should be set when SPI_MEM_FREAD_QIO, + * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + */ + +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 + +/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: For SPI1, enable crc32 when writing encrypted data to flash. + * 1: enable + * 0:disable + */ + +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 + +/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: For SPI1, initialize crc32 module before writing encrypted + * data to flash. Active low. + */ + +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 + +/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase. */ + +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 + +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase. */ + +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 + +/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase. */ + +#define SPI_MEM_FCMD_DUAL (BIT(7)) +#define SPI_MEM_FCMD_DUAL_M (BIT(7)) +#define SPI_MEM_FCMD_DUAL_V 0x1 +#define SPI_MEM_FCMD_DUAL_S 7 + +/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. */ + +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 + +/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase. */ + +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 + +/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. */ + +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 + +/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: In the DUMMY phase the signal level of SPI bus is output by + * the SPI0 controller. + */ + +#define SPI_MEM_FDUMMY_OUT (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_V 0x1 +#define SPI_MEM_FDUMMY_OUT_S 3 + +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) + +/* SPI_MEM_CS_DLY_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: The bit is used to select the spi clock edge to modify + * CS line timing. + */ + +#define SPI_MEM_CS_DLY_EDGE (BIT(31)) +#define SPI_MEM_CS_DLY_EDGE_M (BIT(31)) +#define SPI_MEM_CS_DLY_EDGE_V 0x1 +#define SPI_MEM_CS_DLY_EDGE_S 31 + +/* SPI_MEM_CS_DLY_MODE : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ + +/* Description: The cs signals are delayed by system clock cycles 0: output + * without delayed 1: output with the posedge of clk_apb 2 output with the + * negedge of clk_apb 3: output with the posedge of clk_160 4 output with + * the negedge of clk_160 5: output with the spi_clk + */ + +#define SPI_MEM_CS_DLY_MODE 0x00000007 +#define SPI_MEM_CS_DLY_MODE_M ((SPI_MEM_CS_DLY_MODE_V)<<(SPI_MEM_CS_DLY_MODE_S)) +#define SPI_MEM_CS_DLY_MODE_V 0x7 +#define SPI_MEM_CS_DLY_MODE_S 28 + +/* SPI_MEM_CS_DLY_NUM : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ + +/* Description: spi_mem_cs signal is delayed by system clock cycles */ + +#define SPI_MEM_CS_DLY_NUM 0x00000003 +#define SPI_MEM_CS_DLY_NUM_M ((SPI_MEM_CS_DLY_NUM_V)<<(SPI_MEM_CS_DLY_NUM_S)) +#define SPI_MEM_CS_DLY_NUM_V 0x3 +#define SPI_MEM_CS_DLY_NUM_S 26 + +/* SPI_MEM_CS_HOLD_DLY : R/W ;bitpos:[25:14] ;default: 12'h1 ; */ + +/* Description: SPI fsm is delayed to idle by spi clock cycles. */ + +#define SPI_MEM_CS_HOLD_DLY 0x00000FFF +#define SPI_MEM_CS_HOLD_DLY_M ((SPI_MEM_CS_HOLD_DLY_V)<<(SPI_MEM_CS_HOLD_DLY_S)) +#define SPI_MEM_CS_HOLD_DLY_V 0xFFF +#define SPI_MEM_CS_HOLD_DLY_S 14 + +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[13:2] ;default: 12'hfff ; */ + +/* Description: Delay cycles of resume Flash when resume Flash from standby + * mode is enable by spi clock. + */ + +#define SPI_MEM_CS_HOLD_DLY_RES 0x00000FFF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0xFFF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 + +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: SPI Bus clock (SPI_CLK) mode bits. + * 0: SPI Bus clock (SPI_CLK) is off when CS inactive + * 1: SPI_CLK is delayed one cycle after SPI_CS inactive + * 2: SPI_CLK isdelayed two cycles after SPI_CS inactive + * 3: SPI_CLK is always on. + */ + +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 + +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) + +/* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: The FSM will be reset. */ + +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 + +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[25:13] ;default: 13'h1 ; */ + +/* Description: SPI CS signal is delayed to inactive by SPI clock this bits + * are combined with spi_mem_cs_hold bit. + */ + +#define SPI_MEM_CS_HOLD_TIME 0x00001FFF +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1FFF +#define SPI_MEM_CS_HOLD_TIME_S 13 + +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h1 ; */ + +/* Description: (cycles-1) of prepare phase by spi clock this bits are + * combined with spi_mem_cs_setup bit. + */ + +#define SPI_MEM_CS_SETUP_TIME 0x00001FFF +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1FFF +#define SPI_MEM_CS_SETUP_TIME_S 0 + +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) + +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: When SPI1 access to flash or Ext_RAM, set this bit in + * 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + */ + +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 + +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = + * f_MSPI_CORE_CLK/(SPI_MEM_CLK_CNT_N + 1) + */ + +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 + +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ + +/* Description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). */ + +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 + +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ + +/* Description: It must equal to the value of SPI_MEM_CLKCNT_N. */ + +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 + +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) + +/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ + +/* Description: Set this bit to enable enable the CMD phase of an + * operation. + */ + +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 + +/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable enable the ADDR phase of an operation. + */ + +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 + +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable enable the DUMMY phase of an + * operation. + */ + +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 + +/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable enable the DIN phase of a read-data + * operation. + */ + +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 + +/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the DOUT phase of an write-data + * operation. + */ + +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 + +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the + * bit is enable. + */ + +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 + +/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: DOUT phase only access to high-part of the buffer + * SPI_MEM_W8_REG~SPI_MEM_W15_REG. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 + +/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: DIN phase only access to high-part of the buffer + * SPI_MEM_W8_REG~SPI_MEM_W15_REG. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 + +/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT + * phase in SPI1 write operation. + */ + +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 + +/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 + * write operation. + */ + +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 + +/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 4-bm in DOUT phase in SPI1 write + * operation. + */ + +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 + +/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 2-bm in DOUT phase in SPI1 write + * operation. + */ + +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 + +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to + * change the clock mode 0~3 of SPI_CLK. + */ + +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 + +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ + +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 + +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: Set this bit to keep SPI_CS low when MSPI is in DONE state. */ + +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 + +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) + +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ + +/* Description: The length in bits of ADDR phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 + +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ + +/* Description: The SPI_CLK cycle length minus 1 of DUMMY phase. */ + +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) + +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ + +/* Description: The length in bits of CMD phase. The register value shall be + * (bit_num-1) + */ + +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 + +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ + +/* Description: The value of user defined(USR) command. */ + +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 + +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) + +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ + +/* Description: The length in bits of DOUT phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_MEM_USR_MOSI_DBITLEN 0x000007FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x7FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) + +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ + +/* Description: The length in bits of DIN phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_MEM_USR_MISO_DBITLEN 0x000007FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x7FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) + +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ + +/* Description: Mode bits in the flash fast read mode it is combined with + * SPI_MEM_FASTRD_MODE bit. + */ + +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 + +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ + +/* Description: The value is stored when set SPI_MEM_FLASH_RDSR bit and + * SPI_MEM_FLASH_RES bit. + */ + +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 + +#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x30) + +/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The register are the higher 32bits in the 64 bits address + * mode. + */ + +#define SPI_MEM_EXT_ADDR 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_M ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S)) +#define SPI_MEM_EXT_ADDR_V 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_S 0 + +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) + +/* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable auto PER function. Hardware will sent + * out PER command if PES command is sent. + */ + +#define SPI_MEM_AUTO_PER (BIT(11)) +#define SPI_MEM_AUTO_PER_M (BIT(11)) +#define SPI_MEM_AUTO_PER_V 0x1 +#define SPI_MEM_AUTO_PER_S 11 + +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: SPI_CS line keep low when the bit is set. */ + +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 + +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: + * 1: SPI_CLK line is high when MSPI is idle. + * 0: SPI_CLK line is low when MSPI is idle. + */ + +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 + +/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: Ext_RAM is connected to SPI SUBPIN bus. */ + +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 + +/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: Flash is connected to SPI SUBPIN bus. */ + +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 + +/* SPI_MEM_CS_POL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ + +/* Description: In the master mode the bits are the polarity of spi cs line + * the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol. + */ + +#define SPI_MEM_CS_POL 0x00000003 +#define SPI_MEM_CS_POL_M ((SPI_MEM_CS_POL_V)<<(SPI_MEM_CS_POL_S)) +#define SPI_MEM_CS_POL_V 0x3 +#define SPI_MEM_CS_POL_S 5 + +/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The bit is used to enable the intterrupt of SPI + * transmitting done. + */ + +#define SPI_MEM_TRANS_END_INT_ENA (BIT(4)) +#define SPI_MEM_TRANS_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_TRANS_END_INT_ENA_S 4 + +/* SPI_MEM_TRANS_END : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The bit is used to indicate the transimitting is done. */ + +#define SPI_MEM_TRANS_END (BIT(3)) +#define SPI_MEM_TRANS_END_M (BIT(3)) +#define SPI_MEM_TRANS_END_V 0x1 +#define SPI_MEM_TRANS_END_S 3 + +/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ + +/* Description: SPI CS1 pin enable + * 1: disable CS1 + * 0: spi_mem_cs1 signal is from/to CS1 pin + */ + +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 + +/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to raise high SPI_CS pin, which means that the + * SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer + * starts. + */ + +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 + +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) + +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ + +/* Description: For SPI1, the value of crc32. */ + +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) + +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 4-bm in ADDR phase. + */ + +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 + +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 4-bm in DOUT phase. + */ + +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 + +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 4-bm in DIN phase. + */ + +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 + +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to flash or Ext_RAM, set this bit to + * enable 2-bm in ADDR phase. + */ + +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 + +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 2-bm in DOUT phase. + */ + +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 + +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to flash or Ext_RAM, set this bit to + * enable 2-bm in DIN phase. + */ + +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 + +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: + * 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. + * 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, + * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and + * SPI_MEM_FASTRD_MODE bits. + */ + +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 + +/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: + * Set this bit to enable SPI0 transfer with 32 bits address. The value of + * SPI_MEM_USR_ADDR_BITLEN should be 31. + */ + +#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1 + +/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable Cache's access and SPI0's transfer. */ + +#define SPI_MEM_CACHE_REQ_EN (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_V 0x1 +#define SPI_MEM_CACHE_REQ_EN_S 0 + +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) + +/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus + * 1 of DUMMY phase in write data transfer. + */ + +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x000000FF +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0xFF +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 + +/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable OPI mode in all SPI0 Ext_RAM + * transfer. + */ + +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 + +/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ + +/* Description: + * 1: The command value of SPI0 write Ext_RAM is + * SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. + * 0: The value is 0x3. + */ + +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 + +/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, it is the length in bits of + * ADDR phase. The register value shall be (bit_num-1). + */ + +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 + +/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus + * 1 of DUMMY phase in read data transfer. + */ + +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x000000FF +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0xFF +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 + +/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ + +/* Description: + * 1: The command value of SPI0 read Ext_RAM is + * SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. + * 0: The value is 0x2. + */ + +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 + +/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY + * phase in read operations. + */ + +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 + +/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY + * phase in write operations. + */ + +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 + +/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + */ + +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 + +/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM + * transfer. + */ + +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 + +/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable SPI0 read Ext_RAM with 32 bits + * address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + */ + +#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 + +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) + +/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal + * level of SPI bus is output by the SPI0 controller. + */ + +#define SPI_MEM_SDUMMY_OUT (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_V 0x1 +#define SPI_MEM_SDUMMY_OUT_S 22 + +/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * CMD phase. + */ + +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 + +/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * ADDR phase. + */ + +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 + +/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * DOUT phase. + */ + +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 + +/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * DIN phase. + */ + +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 + +/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * CMD phase. + */ + +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 + +/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * ADDR phase. + */ + +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 + +/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * DOUT phase. + */ + +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 + +/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * DIN phase. + */ + +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 + +/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * CMD phase. + */ + +#define SPI_MEM_SCMD_DUAL (BIT(13)) +#define SPI_MEM_SCMD_DUAL_M (BIT(13)) +#define SPI_MEM_SCMD_DUAL_V 0x1 +#define SPI_MEM_SCMD_DUAL_S 13 + +/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * ADDR phase. + */ + +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 + +/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * DOUT phase. + */ + +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 + +/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * DIN phase. + */ + +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 + +/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */ + +/* Description: Mode bits when SPI0 accesses to Ext_RAM. */ + +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 + +/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ + +/* Description: SPI_CLK mode bits when SPI0 accesses to Ext_RAM. + * 0: SPI_CLK is off when CS inactive + * 1: SPI_CLK is delayed one cycle after CS inactive + * 2: SPI_CLK is delayed two cycles after CS inactive + * 3: SPI_CLK is always on. + */ + +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 + +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) + +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ + +/* Description: When SPI0 reads Ext_RAM, it is the length in bits of CMD + * phase. The register value shall be (bit_num-1). + */ + +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE: R/W;bitpos:[15:0];default:16'h0; */ + +/* Description: When SPI0 reads Ext_RAM, it is the command value of + * CMD phase. + */ + +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) + +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ + +/* Description: When SPI0 writes Ext_RAM, it is the length in bits of CMD + * phase. The register value shall be (bit_num-1). + */ + +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE: R/W;bitpos:[15:0];default: 16'h0; */ + +/* Description: When SPI0 writes Ext_RAM, it is the command value of + * CMD phase. + */ + +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) + +/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit in 1-division + * mode, f_SPI_CLK = f_MSPI_CORE_CLK. + */ + +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 + +/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = + * f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) + */ + +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 + +/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ + +/* Description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). */ + +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 + +/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ + +/* Description: It must equal to the value of SPI_MEM_SCLKCNT_N. */ + +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 + +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) + +/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ + +/* Description: The status of SPI1 state machine. + * 0: idle state(IDLE), + * 1: preparation state(PREP), + * 2: send command state(CMD), + * 3: send address state(ADDR), + * 4: red data state(DIN), + * 5:write data state(DOUT), + * 6: wait state(DUMMY), + * 7: done state(DONE). + */ + +#define SPI_MEM_ST 0x00000007 +#define SPI_MEM_ST_M ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S)) +#define SPI_MEM_ST_V 0x7 +#define SPI_MEM_ST_S 0 + +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) + +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 + +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) + +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 + +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) + +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 + +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) + +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 + +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) + +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 + +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) + +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 + +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) + +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 + +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) + +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 + +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) + +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 + +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) + +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 + +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) + +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 + +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) + +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 + +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) + +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 + +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) + +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 + +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) + +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 + +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) + +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) + +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ + +/* Description: The dummy cycle length when wait flash idle(RDSR). */ + +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x000000FF +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0xFF +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 + +/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */ + +/* Description: The command value of auto wait flash idle transfer(RDSR). */ + +#define SPI_MEM_WAITI_CMD 0x000000FF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFF +#define SPI_MEM_WAITI_CMD_S 2 + +/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable DUMMY phase in auto wait flash idle + * transfer(RDSR). + */ + +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 + +/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable auto-waiting flash idle operation when + * PP/SE/BE/CE/WRSR/PES command is sent. + */ + +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (BIT(0)) +#define SPI_MEM_WAITI_EN_V 0x1 +#define SPI_MEM_WAITI_EN_S 0 + +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x09C) + +/* Description: program erase suspend bit, program erase suspend operation + * will be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0:disable. + */ + +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 + +/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: program erase resume bit, program erase suspend operation + * will be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 + +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) + +/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */ + +/* Description: Program/Erase suspend command value. */ + +#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PES_COMMAND_S 9 + +/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */ + +/* Description: Program/Erase resume command value. */ + +#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PER_COMMAND_S 1 + +/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable auto-suspend function. */ + +#define SPI_MEM_FLASH_PES_EN (BIT(0)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(0)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 0 + +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A4) + +/* Description: The status of flash suspend. This bit is set when PES command + * is sent, and cleared when PER is sent. Only used in SPI1. + */ + +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 + +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xA8) + +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ + +/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing + * compensation. Active when SPI_MEM_TIMING_CALI bit is set. + */ + +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000003 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x3 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 + +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for + * all reading operations. + */ + +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 + +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to power on HCLK. When PLL is powered on, the + * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals + * to that of XTAL. + */ + +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xAC) + +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ + +/* Description: SPI_DQS input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) + * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 +#define SPI_MEM_DINS_MODE_S 24 + +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ + +/* Description: SPI_IO7 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 + +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ + +/* Description: SPI_IO6 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 + +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ + +/* Description: SPI_IO5 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. 3: Delay for + * (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative + * edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 + +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ + +/* Description: SPI_IO4 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 + +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ + +/* Description: SPI_HD input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN3_MODE 0x00000007 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x7 +#define SPI_MEM_DIN3_MODE_S 9 + +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ + +/* Description: SPI_WP input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN2_MODE 0x00000007 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x7 +#define SPI_MEM_DIN2_MODE_S 6 + +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ + +/* Description: SPI_Q input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN1_MODE 0x00000007 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x7 +#define SPI_MEM_DIN1_MODE_S 3 + +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ + +/* Description: SPI_D input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK nega tive edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o ne + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN0_MODE 0x00000007 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x7 +#define SPI_MEM_DIN0_MODE_S 0 + +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xB0) + +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ + +/* Description: SPI_DQS input delay number. */ + +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 + +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ + +/* Description: SPI_IO7 input delay number. */ + +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 + +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ + +/* Description: SPI_IO6 input delay number. */ + +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 + +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ + +/* Description: SPI_IO5 input delay number. */ + +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 + +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ + +/* Description: SPI_IO4 input delay number. */ + +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 + +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ + +/* Description: SPI_HD input delay number. */ + +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 + +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ + +/* Description: SPI_WP input delay number. */ + +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 + +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ + +/* Description: SPI_Q input delay number. */ + +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 + +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: SPI_D input delay number. */ + +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 + +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xB4) + +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb + * 3: output with the spi_clk + */ + +#define SPI_MEM_DOUTS_MODE 0x00000007 +#define SPI_MEM_DOUTS_MODE_M ((SPI_MEM_DOUTS_MODE_V)<<(SPI_MEM_DOUTS_MODE_S)) +#define SPI_MEM_DOUTS_MODE_V 0x7 +#define SPI_MEM_DOUTS_MODE_S 24 + +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the spi_clk + */ + +#define SPI_MEM_DOUT7_MODE 0x00000007 +#define SPI_MEM_DOUT7_MODE_M ((SPI_MEM_DOUT7_MODE_V)<<(SPI_MEM_DOUT7_MODE_S)) +#define SPI_MEM_DOUT7_MODE_V 0x7 +#define SPI_MEM_DOUT7_MODE_S 21 + +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the spi_clk + */ + +#define SPI_MEM_DOUT6_MODE 0x00000007 +#define SPI_MEM_DOUT6_MODE_M ((SPI_MEM_DOUT6_MODE_V)<<(SPI_MEM_DOUT6_MODE_S)) +#define SPI_MEM_DOUT6_MODE_V 0x7 +#define SPI_MEM_DOUT6_MODE_S 18 + +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the spi_clk + */ + +#define SPI_MEM_DOUT5_MODE 0x00000007 +#define SPI_MEM_DOUT5_MODE_M ((SPI_MEM_DOUT5_MODE_V)<<(SPI_MEM_DOUT5_MODE_S)) +#define SPI_MEM_DOUT5_MODE_V 0x7 +#define SPI_MEM_DOUT5_MODE_S 15 + +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the spi_clk + */ + +#define SPI_MEM_DOUT4_MODE 0x00000007 +#define SPI_MEM_DOUT4_MODE_M ((SPI_MEM_DOUT4_MODE_V)<<(SPI_MEM_DOUT4_MODE_S)) +#define SPI_MEM_DOUT4_MODE_V 0x7 +#define SPI_MEM_DOUT4_MODE_S 12 + +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_DOUT3_MODE 0x00000007 +#define SPI_MEM_DOUT3_MODE_M ((SPI_MEM_DOUT3_MODE_V)<<(SPI_MEM_DOUT3_MODE_S)) +#define SPI_MEM_DOUT3_MODE_V 0x7 +#define SPI_MEM_DOUT3_MODE_S 9 + +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_DOUT2_MODE 0x00000007 +#define SPI_MEM_DOUT2_MODE_M ((SPI_MEM_DOUT2_MODE_V)<<(SPI_MEM_DOUT2_MODE_S)) +#define SPI_MEM_DOUT2_MODE_V 0x7 +#define SPI_MEM_DOUT2_MODE_S 6 + +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_DOUT1_MODE 0x00000007 +#define SPI_MEM_DOUT1_MODE_M ((SPI_MEM_DOUT1_MODE_V)<<(SPI_MEM_DOUT1_MODE_S)) +#define SPI_MEM_DOUT1_MODE_V 0x7 +#define SPI_MEM_DOUT1_MODE_S 3 + +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_DOUT0_MODE 0x00000007 +#define SPI_MEM_DOUT0_MODE_M ((SPI_MEM_DOUT0_MODE_V)<<(SPI_MEM_DOUT0_MODE_S)) +#define SPI_MEM_DOUT0_MODE_V 0x7 +#define SPI_MEM_DOUT0_MODE_S 0 + +#define SPI_MEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B8) + +/* SPI_MEM_DOUTS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUTS_NUM 0x00000003 +#define SPI_MEM_DOUTS_NUM_M ((SPI_MEM_DOUTS_NUM_V)<<(SPI_MEM_DOUTS_NUM_S)) +#define SPI_MEM_DOUTS_NUM_V 0x3 +#define SPI_MEM_DOUTS_NUM_S 16 + +/* SPI_MEM_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle + * 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT7_NUM 0x00000003 +#define SPI_MEM_DOUT7_NUM_M ((SPI_MEM_DOUT7_NUM_V)<<(SPI_MEM_DOUT7_NUM_S)) +#define SPI_MEM_DOUT7_NUM_V 0x3 +#define SPI_MEM_DOUT7_NUM_S 14 + +/* SPI_MEM_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle + * 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT6_NUM 0x00000003 +#define SPI_MEM_DOUT6_NUM_M ((SPI_MEM_DOUT6_NUM_V)<<(SPI_MEM_DOUT6_NUM_S)) +#define SPI_MEM_DOUT6_NUM_V 0x3 +#define SPI_MEM_DOUT6_NUM_S 12 + +/* SPI_MEM_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT5_NUM 0x00000003 +#define SPI_MEM_DOUT5_NUM_M ((SPI_MEM_DOUT5_NUM_V)<<(SPI_MEM_DOUT5_NUM_S)) +#define SPI_MEM_DOUT5_NUM_V 0x3 +#define SPI_MEM_DOUT5_NUM_S 10 + +/* SPI_MEM_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT4_NUM 0x00000003 +#define SPI_MEM_DOUT4_NUM_M ((SPI_MEM_DOUT4_NUM_V)<<(SPI_MEM_DOUT4_NUM_S)) +#define SPI_MEM_DOUT4_NUM_V 0x3 +#define SPI_MEM_DOUT4_NUM_S 8 + +/* SPI_MEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT3_NUM 0x00000003 +#define SPI_MEM_DOUT3_NUM_M ((SPI_MEM_DOUT3_NUM_V)<<(SPI_MEM_DOUT3_NUM_S)) +#define SPI_MEM_DOUT3_NUM_V 0x3 +#define SPI_MEM_DOUT3_NUM_S 6 + +/* SPI_MEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT2_NUM 0x00000003 +#define SPI_MEM_DOUT2_NUM_M ((SPI_MEM_DOUT2_NUM_V)<<(SPI_MEM_DOUT2_NUM_S)) +#define SPI_MEM_DOUT2_NUM_V 0x3 +#define SPI_MEM_DOUT2_NUM_S 4 + +/* SPI_MEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT1_NUM 0x00000003 +#define SPI_MEM_DOUT1_NUM_M ((SPI_MEM_DOUT1_NUM_V)<<(SPI_MEM_DOUT1_NUM_S)) +#define SPI_MEM_DOUT1_NUM_V 0x3 +#define SPI_MEM_DOUT1_NUM_S 2 + +/* SPI_MEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_DOUT0_NUM 0x00000003 +#define SPI_MEM_DOUT0_NUM_M ((SPI_MEM_DOUT0_NUM_V)<<(SPI_MEM_DOUT0_NUM_S)) +#define SPI_MEM_DOUT0_NUM_V 0x3 +#define SPI_MEM_DOUT0_NUM_S 0 + +/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN: R/W ;bitpos:[4:2]; default: 3'd0; */ + +/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing + * compensation, when SPI0 accesses to Ext_RAM. Active when + * SPI_SMEM_TIMING_CALI bit is set. + */ + +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000003 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x3 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 + +/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for + * all reading operations. + */ + +#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 + +/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to power on HCLK. When PLL is powered on, the + * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals + * to that of XTAL. + */ + +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) + +/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ + +/* Description: SPI_DQS input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 + +/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ + +/* Description: SPI_IO7 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 + +/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ + +/* Description: SPI_IO6 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (S PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 + +/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ + +/* Description: SPI_IO5 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 + +/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ + +/* Description: SPI_IO4 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+ 1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 + +/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ + +/* Description: SPI_HD input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 + +/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ + +/* Description: SPI_WP input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 + +/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ + +/* Description: SPI_Q input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 + +/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ + +/* Description: SPI_D input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) + +/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ + +/* Description: SPI_DQS input delay number. */ + +#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 + +/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ + +/* Description: SPI_IO7 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 + +/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ + +/* Description: SPI_IO6 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 + +/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ + +/* Description: SPI_IO5 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 + +/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ + +/* Description: SPI_IO4 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 + +/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ + +/* Description: SPI_HD input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 + +/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ + +/* Description: SPI_WP input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 + +/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ + +/* Description: SPI_Q input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 + +/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: SPI_D input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C8) + +/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUTS_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M ((SPI_MEM_SPI_SMEM_DOUTS_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUTS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 24 + +/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT7_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M ((SPI_MEM_SPI_SMEM_DOUT7_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 21 + +/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ +#define SPI_MEM_SPI_SMEM_DOUT6_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M ((SPI_MEM_SPI_SMEM_DOUT6_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 18 + +/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT5_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M ((SPI_MEM_SPI_SMEM_DOUT5_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 15 + +/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT4_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M ((SPI_MEM_SPI_SMEM_DOUT4_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 12 + +/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT3_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M ((SPI_MEM_SPI_SMEM_DOUT3_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 9 + +/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4 output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT2_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M ((SPI_MEM_SPI_SMEM_DOUT2_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 6 + +/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2 output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT1_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M ((SPI_MEM_SPI_SMEM_DOUT1_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 3 + +/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT0_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M ((SPI_MEM_SPI_SMEM_DOUT0_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0CC) + +/* SPI_MEM_SPI_SMEM_DOUTS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUTS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUTS_NUM_M ((SPI_MEM_SPI_SMEM_DOUTS_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUTS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUTS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUTS_NUM_S 16 + +/* SPI_MEM_SPI_SMEM_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT7_NUM_M ((SPI_MEM_SPI_SMEM_DOUT7_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT7_NUM_S 14 + +/* SPI_MEM_SPI_SMEM_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2 output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4 output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT6_NUM_M ((SPI_MEM_SPI_SMEM_DOUT6_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT6_NUM_S 12 + +/* SPI_MEM_SPI_SMEM_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2 output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT5_NUM_M ((SPI_MEM_SPI_SMEM_DOUT5_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT5_NUM_S 10 + +/* SPI_MEM_SPI_SMEM_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: output without delayed + * 1: output with the posedge of clk_apb + * 2: output with the negedge of clk_apb + * 3: output with the posedge of clk_160 + * 4: output with the negedge of clk_160 + * 5: output with the spi_clk high edge + * 6: output with the spi_clk low edge + */ + +#define SPI_MEM_SPI_SMEM_DOUT4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT4_NUM_M ((SPI_MEM_SPI_SMEM_DOUT4_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT4_NUM_S 8 + +/* SPI_MEM_SPI_SMEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle + * 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_SPI_SMEM_DOUT3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT3_NUM_M ((SPI_MEM_SPI_SMEM_DOUT3_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT3_NUM_S 6 + +/* SPI_MEM_SPI_SMEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle + * 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_SPI_SMEM_DOUT2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT2_NUM_M ((SPI_MEM_SPI_SMEM_DOUT2_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT2_NUM_S 4 + +/* SPI_MEM_SPI_SMEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_SPI_SMEM_DOUT1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT1_NUM_M ((SPI_MEM_SPI_SMEM_DOUT1_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT1_NUM_S 2 + +/* SPI_MEM_SPI_SMEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: the output signals are delayed by system clock cycles + * 0: delayed by 1 cycle 1: delayed by 2 cycles ... + */ + +#define SPI_MEM_SPI_SMEM_DOUT0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT0_NUM_M ((SPI_MEM_SPI_SMEM_DOUT0_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT0_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D0) + +/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[27:15] ;default: 13'h1 ; */ + +/* Description: For spi0 spi cs signal is delayed to inactive by spi clock + * this bits are combined with spi_mem_cs_hold bit. + */ + +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x00001FFF +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1FFF +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 15 + +/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[14:2] ;default: 13'h1 ; */ + +/* Description: For spi0 (cycles-1) of prepare phase by spi clock this bits + * are combined with spi_mem_cs_setup bit. + */ + +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x00001FFF +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1FFF +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 + +/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: For spi0 spi cs keep low when spi is in done phase. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 + +/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ + +#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 + +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D4) + +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE: R/W;bitpos:[23:22];default: 2'b0 ; */ + +/* Description: the bits are combined with the bit spi_fmem_ddr_fdqs_loop + * which used to select data strobe generating mode in ddr mode. + */ + +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE 0x00000003 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V)<<(SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x3 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 + +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: + * 1: Use internal signal as data strobe, the strobe can not be delayed by + * input timing module. + * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be + * delayed by input timing module + */ + +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 + +/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ + +/* Description: The delay number of data strobe which from memory based on + * SPI_CLK. + */ + +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x000000FF +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0xFF +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 13 + +/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[12:5] ;default: 8'b1 ; */ + +/* Description: It is the minimum output data length in the panda device. */ + +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x000000FF +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0xFF +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 + +/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: the bit is used to disable dual edge in command phase when + * DDR mode. + */ + +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 + +/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder TX data of the word in DDR mode. */ + +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 + +/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder RX data of the word in DDR mode. */ + +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 + +/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable variable dummy cycle in DDRmode. */ + +#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 + +/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: 1: in DDR mode, 0: in SDR mode. */ + +#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D8) + +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE: R/W;bitpos:[23:22];default: 2'b0; */ + +/* Description: the bits are combined with the bit spi_smem_ddr_fdqs_loop + * which used to select data strobe generating mode in ddr mode. + */ + +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V)<<(SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 + +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: + * 1: Use internal signal as data strobe, the strobe can not be delayed by + * input timing module. + * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be + * delayed by input timing module + */ + +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 + +/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ + +/* Description: The delay number of data strobe which from memory based on + * SPI_CLK. + */ + +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x000000FF +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0xFF +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 13 + +/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[12:5] ;default: 8'b1 ; */ + +/* Description: It is the minimum output data length in the ddr psram. */ + +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x000000FF +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0xFF +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: the bit is used to disable dual edge in CMD phase when ddr + * mode. + */ + +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 + +/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder tx data of the word in spi ddr mode. */ + +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 + +/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder rx data of the word in spi ddr mode. */ + +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 + +/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable variable dummy cycle in spi ddr mode. */ + +#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 + +/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: 1: in ddr mode, 0 in sdr mode */ + +#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0xE8) + +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +/* Description: Register clock gate enable signal. 1: Enable. 0: Disable. */ + +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) + +/* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */ + +/* Description: SPI register version. */ + +#define SPI_MEM_DATE 0x00FFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H */ diff --git a/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h b/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h new file mode 100644 index 0000000000..f5526f0cd3 --- /dev/null +++ b/arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h @@ -0,0 +1,367 @@ +/***************************************************************************** + * arch/xtensa/src/esp32s2/rom/esp32s2_opi_flash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ROM_ESP32S2_OPI_FLASH_H +#define __ARCH_XTENSA_SRC_ESP32S2_ROM_ESP32S2_OPI_FLASH_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef struct +{ + uint16_t cmd; /* !< Command value */ + uint16_t cmd_bit_len; /* !< Command byte length */ + uint32_t *addr; /* !< Point to address value */ + uint32_t addr_bit_len; /* !< Address byte length */ + uint32_t *tx_data; /* !< Point to send data buffer */ + uint32_t tx_data_bit_len; /* !< Send data byte length. */ + uint32_t *rx_data; /* !< Point to recevie data buffer */ + uint32_t rx_data_bit_len; /* !< Recevie Data byte length. */ + uint32_t dummy_bit_len; +} esp_rom_spi_cmd_t; + +#define ESP_ROM_OPIFLASH_MUX_TAKE() +#define ESP_ROM_OPIFLASH_MUX_GIVE() +#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) +#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) + +/* Definition of MX25UM25645G Octa Flash + * SPI status register + */ + +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_QE BIT9 + +#define FLASH_OP_MODE_RDCMD_DOUT 0x3B +#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 +#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 +#define ESP_ROM_FLASH_PAGE_SIZE 256 + +/* FLASH commands */ + +#define ROM_FLASH_CMD_RDID 0x9F +#define ROM_FLASH_CMD_WRSR 0x01 +#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_WREN 0x06 +#define ROM_FLASH_CMD_WRDI 0x04 +#define ROM_FLASH_CMD_RDSR 0x05 +#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_ERASE_SEC 0x20 +#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 +#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 +#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define ROM_FLASH_CMD_RSTEN 0x66 +#define ROM_FLASH_CMD_RST 0x99 + +#define ROM_FLASH_CMD_SE4B 0x21 +#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 +#define ROM_FLASH_CMD_BE4B 0xDC +#define ROM_FLASH_CMD_BE4B_OCT 0x23DC +#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 +#define ROM_FLASH_CMD_RST_OCT 0x6699 + +#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC +#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE +#define ROM_FLASH_CMD_FSTRD4B 0x0C +#define ROM_FLASH_CMD_PP4B 0x12 +#define ROM_FLASH_CMD_PP4B_OCT 0xED12 + +#define ROM_FLASH_CMD_RDID_OCT 0x609F +#define ROM_FLASH_CMD_WREN_OCT 0xF906 +#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 +#define ROM_FLASH_CMD_RDCR2 0x71 +#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 +#define ROM_FLASH_CMD_WRCR2 0x72 +#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 + +/* Definitions for GigaDevice GD25LX256E Flash */ + +#define ROM_FLASH_CMD_RDFSR_GD 0x70 +#define ROM_FLASH_CMD_RD_GD 0x03 +#define ROM_FLASH_CMD_RD4B_GD 0x13 +#define ROM_FLASH_CMD_FSTRD_GD 0x0B +#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C +#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B +#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C +#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB +#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC +#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD + +#define ROM_FLASH_CMD_PP_GD 0x02 +#define ROM_FLASH_CMD_PP4B_GD 0x12 +#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 +#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 +#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 +#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E + +#define ROM_FLASH_CMD_SE_GD 0x20 +#define ROM_FLASH_CMD_SE4B_GD 0x21 +#define ROM_FLASH_CMD_BE32K_GD 0x52 +#define ROM_FLASH_CMD_BE32K4B_GD 0x5C +#define ROM_FLASH_CMD_BE64K_GD 0xD8 +#define ROM_FLASH_CMD_BE64K4B_GD 0xDC + +#define ROM_FLASH_CMD_EN4B_GD 0xB7 +#define ROM_FLASH_CMD_DIS4B_GD 0xE9 + +/* spi user mode command config */ + +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ + +void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd); + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase + * operation, since the CPU would check permission + */ + +void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len, + uint8_t cs_en_mask, bool is_write_erase); + +/** + * @brief Config opi flash pads according to efuse settings. + */ + +void esp_rom_opiflash_pin_config(void); + +/** + * @brief Set SPI operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ + +void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ + +void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ + +void esp_rom_opiflash_mode_reset(int spi_num); + +#if 0 + +/* MX25UM25645G opi flash interface */ + +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase + * flash operation + */ + +void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t *mosi_data, int mosi_bit_len, + uint8_t *miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation); + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ + +void esp_rom_opiflash_soft_reset(int spi_num, + esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash ID + * @note command format would be defined in initialization + * @param[out] out_id buffer to accept id + * @return flash operation result + */ + +uint32_t esp_rom_opiflash_read_id(int spi_num, + esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash status register(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash status value + */ + +uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief wait opi flash status register to be idle + * @param spi_num spi port + * @param mode Flash Operation Mode + */ + +void esp_rom_opiflash_wait_idle(int spi_num, + esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of configure register + * @return value of config register2 + */ + +uint8_t esp_rom_opiflash_rdcr2(int spi_num, + esp_rom_spiflash_read_mode_t mode, + uint32_t addr); + +/** + * @brief to write the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of config register + * @param val the value to write + */ + +void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t addr, uint8_t val); + +/** + * @brief to erase flash sector(for MX25UM25645G) + * @param spi_num spi port + * @param address the sector address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ + +esp_rom_spiflash_result_t +esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, + esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase flash block(for MX25UM25645G) + * @param spi_num spi port + * @param address the block address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ + +esp_rom_spiflash_result_t +esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, + esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase a flash area define by start address and length + * (for MX25UM25645G) + * @param spi_num spi port + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @param mode flash operation mode + * @return flash operation result + */ + +esp_rom_spiflash_result_t +esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, + uint32_t area_len, + esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read data from opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ + +esp_rom_spiflash_result_t +esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t flash_addr, uint8_t *data_addr, int len); + +/** + * @brief to write data to opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ + +esp_rom_spiflash_result_t +esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t flash_addr, uint8_t *data_addr, + uint32_t len); + +/** + * @brief to set opi flash operation mode(for MX25UM25645G) + * @param spi_num spi port + * @param cur_mode current operation mode + * @param target the target operation mode to be set + */ + +void esp_rom_opiflash_set_mode(int spi_num, + esp_rom_spiflash_read_mode_t cur_mode, + esp_rom_spiflash_read_mode_t target_mode); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ROM_ESP32S2_OPI_FLASH_H */ diff --git a/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h b/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h new file mode 100644 index 0000000000..87d862214c --- /dev/null +++ b/arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h @@ -0,0 +1,1020 @@ +/***************************************************************************** + * arch/xtensa/src/esp32s2/rom/esp32s2_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ROM_ESP32S2_SPIFLASH_H +#define __ARCH_XTENSA_SRC_ESP32S2_ROM_ESP32S2_SPIFLASH_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 3 +#define SPI0_R_QIO_ADDR_BITSLEN 31 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 1 +#define SPI0_R_DIO_ADDR_BITSLEN 27 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 3 +#define SPI1_R_QIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B + +/* SPI address register */ + +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f + +/* SPI status register */ + +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|\ + ESP_ROM_SPIFLASH_BP1|\ + ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +/* Extra dummy for flash read */ + +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 + +#define FLASH_ID_GD25LQ32C 0xC86016 + +/***************************************************************************** + * Public Types + *****************************************************************************/ + +typedef enum +{ + ESP_ROM_SPIFLASH_QIO_MODE = 0, + ESP_ROM_SPIFLASH_QOUT_MODE, + ESP_ROM_SPIFLASH_DIO_MODE, + ESP_ROM_SPIFLASH_DOUT_MODE, + ESP_ROM_SPIFLASH_FASTRD_MODE, + ESP_ROM_SPIFLASH_SLOWRD_MODE +} esp_rom_spiflash_read_mode_t; + +typedef enum +{ + ESP_ROM_SPIFLASH_RESULT_OK, + ESP_ROM_SPIFLASH_RESULT_ERR, + ESP_ROM_SPIFLASH_RESULT_TIMEOUT +} esp_rom_spiflash_result_t; + +typedef struct +{ + uint32_t device_id; + uint32_t chip_size; /* chip size in bytes */ + uint32_t block_size; + uint32_t sector_size; + uint32_t page_size; + uint32_t status_mask; +} esp32s2_spiflash_chip_t; + +typedef struct +{ + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * Global ROM spiflash data, as used by legacy SPI flash functions + */ + +struct spiflash_legacy_data_s +{ + esp32s2_spiflash_chip_t chip; + uint8_t dummy_len_plus[3]; + uint8_t sig_matrix; +}; + +/** + * Structure holding SPI flash access critical sections management functions. + * + * Flash API uses two types of functions for flash access management: + * 1) Functions which prepare/restore flash cache and interrupts before + * calling appropriate ROM functions (SPIWrite, SPIRead and + * SPIEraseBlock): + * - 'start' function should disable flash cache and non-IRAM interrupts + * and is invoked before the call to one of ROM functions from + * "struct spiflash_guard_funcs_s". + * - 'end' function should restore state of flash cache and non-IRAM + * interrupts and is invoked after the call to one of ROM + * functions from "struct spiflash_guard_funcs_s". + * These two functions are not reentrant. + * 2) Functions which synchronizes access to internal data used by flash API. + * These functions are mostly intended to synchronize access to flash API + * internal data in multithreaded environment and use OS primitives: + * - 'op_lock' locks access to flash API internal data. + * - 'op_unlock' unlocks access to flash API internal data. + * These two functions are reentrant and can be used around the outside of + * multiple calls to 'start' & 'end', in order to create atomic multi-part + * flash operations. + * + * Different versions of the guarding functions should be used depending on + * the context of execution (with or without functional OS). In normal + * conditions when flash API is called from task the functions use OS + * primitives. + * When there is no OS at all or when it is not guaranteed that OS is + * functional (accessing flash from exception handler) these functions cannot + * use OS primitives or even does not need them (multithreaded access is + * not possible). + * + * @note Structure and corresponding guard functions should not reside + * in flash. For example structure can be placed in DRAM and functions + * in IRAM sections. + */ + +struct spiflash_guard_funcs +{ + void (*start)(void); /* critical section start function */ + void (*end)(void); /* critical section end function */ + void (*op_lock)(void); /* flash access API lock function */ + void (*op_unlock)(void); /* flash access API unlock function */ + + /* checks flash write addresses */ + + bool (*address_is_safe)(size_t addr, size_t size); + + void (*yield)(void); /* yield to the OS during flash erase */ +}; + +/***************************************************************************** + * Public Function Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Name: esp_rom_spiflash_fix_dummylen + * + * Description: + * Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High + * Speed. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, + * 1 for 80M. + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/***************************************************************************** + * Name: esp_rom_spiflash_select_qiomode + * + * Description: + * Select SPI Flash to QIO mode when WP pad is read from Flash. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t wp_gpio_num: WP gpio number. + * + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * Returned Value: + * None + *****************************************************************************/ + +void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, + uint32_t ishspi); + +/***************************************************************************** + * Name: esp_rom_spiflash_set_drvs + * + * Description: + * Set SPI Flash pad drivers. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t wp_gpio_num: WP gpio number. + * + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, + * drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from flash by rom code, function + * usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] + * is the real value. + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, + uint32_t ishspi, + uint8_t *drvs); + +/***************************************************************************** + * Name: esp_rom_spiflash_select_padsfunc + * + * Description: + * Select SPI Flash function for pads. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/***************************************************************************** + * Name: esp_rom_spiflash_attach + * + * Description: + * SPI Flash init, clock divisor is 4, use 1 line Slow read mode. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * uint8_t legacy: In legacy mode, more SPI command is used in line. + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); + +/***************************************************************************** + * Name: esp_rom_spiflash_read_status + * + * Description: + * SPI Read Flash status register. We use CMD 0x05 (RDSR). + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32s2_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t *status : The pointer to which to return the Flash status value. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_read_status(esp32s2_spiflash_chip_t *spi, + uint32_t *status); + +/***************************************************************************** + * Name: esp32s2_spiflash_read_statushigh + * + * Description: + * SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32s2_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t *status : The pointer to which to return the Flash status value. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp32s2_spiflash_read_statushigh(esp32s2_spiflash_chip_t *spi, + uint32_t *status); + +/***************************************************************************** + * Name: esp32s2_spiflash_write_status + * + * Description: + * Write status to Falsh status register. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32s2_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t status_value : Value to . + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp32s2_spiflash_write_status(esp32s2_spiflash_chip_t *spi, + uint32_t status_value); + +/***************************************************************************** + * Name: esp_rom_spiflash_read_user_cmd + * + * Description: + * Use a command to Read Flash status register. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32s2_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t*status : The pointer to which to return the Flash status value. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_read_user_cmd(uint32_t *status, + uint8_t cmd); + +/***************************************************************************** + * Name: esp_rom_spiflash_config_readmode + * + * Description: + * Config SPI Flash read mode when init. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status + * register, caller is responsible for this. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/***************************************************************************** + * Name: esp_rom_spiflash_config_clk + * + * Description: + * Config SPI Flash clock divisor. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t freqdiv: clock divisor. + * + * uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_config_clk(uint8_t freqdiv, + uint8_t spi); + +/***************************************************************************** + * Name: esp_rom_spiflash_common_cmd + * + * Description: + * Send CommonCmd to Flash so that is can go into QIO mode, some Flash use + * different CMD. + * + * Please do not call this function in SDK. + * + * Input Paramater: + * esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a + * command. + * + * Returned Value: + * uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + * + *****************************************************************************/ + +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +/***************************************************************************** + * Name: esp_rom_spiflash_unlock + * + * Description: + * Unlock SPI write protect. + * + * Please do not call this function in SDK. + * + * Input Value: + * None. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_lock + * + * Description: + * SPI write protect. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * None. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_config_param + * + * Description: + * Update SPI Flash parameter. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * uint32_t chip_size : The Flash size. + * + * uint32_t block_size : The Flash block size. + * + * uint32_t sector_size : The Flash sector size. + * + * uint32_t page_size : The Flash page size. + * + * uint32_t status_mask : The Mask used when read status from Flash + * (use single CMD). + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_config_param(uint32_t deviceid, + uint32_t chip_size, + uint32_t block_size, + uint32_t sector_size, + uint32_t page_size, + uint32_t status_mask); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_chip + * + * Description: + * Erase whole flash chip. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * None + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_block + * + * Description: + * Erase a 64KB block of flash + * Uses SPI flash command D8H. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * uint32_t block_num : Which block to erase. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_sector + * + * Description: + * Erase a sector of flash. + * Uses SPI flash command 20H. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t sector_num : Which sector to erase. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_area + * + * Description: + * Erase some sectors. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * uint32_t area_len : Length to erase, should be sector aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_erase_area(uint32_t start_addr, + uint32_t area_len); + +/***************************************************************************** + * Name: esp_rom_spiflash_write + * + * Description: + * Write Data to Flash, you should Erase it yourself if need. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * const uint32_t *src : The pointer to data which is to write. + * + * uint32_t len : Length to write, should be 4 bytes aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_write(uint32_t dest_addr, + const uint32_t *src, + int32_t len); + +/***************************************************************************** + * Name: esp_rom_spiflash_read + * + * Description: + * Read Data from Flash, you should Erase it yourself if need. + * + * Please do not call this function in SDK. + * + * Input Values: + * uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * uint32_t *dest : The buf to read the data. + * + * uint32_t len : Length to read, should be 4 bytes aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_read(uint32_t src_addr, + uint32_t *dest, + int32_t len); + +/***************************************************************************** + * Name: esp_rom_spiflash_write_encrypted_enable + * + * Description: + * SPI1 go into encrypto mode. + * + * Please do not call this function in SDK. + * + *****************************************************************************/ + +void esp_rom_spiflash_write_encrypted_enable(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_prepare_encrypted_data + * + * Description: + * Prepare 32 Bytes data to encrpto writing, you should Erase it yourself + * if need. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * uint32_t *data : The pointer to data which is to write. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, + uint32_t *data); + +/***************************************************************************** + * Name: esp_rom_spiflash_write_encrypted_disable + * + * Description: + * SPI1 go out of encrypto mode. + * + * Please do not call this function in SDK. + * + *****************************************************************************/ + +void esp_rom_spiflash_write_encrypted_disable(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_write_encrypted + * + * Description: + * Write data to flash with transparent encryption. + * Sectors to be written should already be erased. + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * uint32_t len : Length to write, should be 32 bytes aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_write_encrypted(uint32_t flash_addr, + uint32_t *data, + uint32_t len); + +/***************************************************************************** + * Name: esp_rom_spiflash_wait_idle + * + * Description: + * Wait until SPI flash write operation is complete + * + * Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp32s2_spiflash_chip_t + *spi); + +/***************************************************************************** + * Name: esp_rom_spiflash_select_qio_pins + * + * Description: + * Enable Quad I/O pin functions + * + * Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * Input Parameters: + * wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * spiconfig - Pin configuration, as returned from + * ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and + * wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and + * wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number + * and also the CLK pin number. CLK pin selection is used to + * determine if HSPI or SPI peripheral will be used (use HSPI + * if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected + * peripheral. + * + *****************************************************************************/ + +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, + uint32_t spiconfig); + +/***************************************************************************** + * Name: spi_flash_guard_set + * + * Description: + * Sets guard functions to access flash. + * + * Input Parameters: + * funcs - funcs pointer to structure holding flash access guard functions + * + * Returned Value: + * None + * + *****************************************************************************/ + +void spi_flash_guard_set(const struct spiflash_guard_funcs *funcs); + +/***************************************************************************** + * Name: spi_flash_write_encrypted + * + * Description: + * Write data encrypted to Flash. + * + * Flash encryption must be enabled for this function to work. + * + * Flash encryption must be enabled when calling this function. + * If flash encryption is disabled, the function returns + * ESP_ERR_INVALID_STATE. Use esp_flash_encryption_enabled() + * function to determine if flash encryption is enabled. + * + * Both dest_addr and size must be multiples of 16 bytes. For + * absolute best performance, both dest_addr and size arguments should + * be multiples of 32 bytes. + * + * Input Parameters: + * dest_addr - Destination address in Flash. Must be a multiple of 16 + * bytes. + * src - Pointer to the source buffer. + * size - Length of data, in bytes. Must be a multiple of 16 bytes. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_write_encrypted(uint32_t dest_addr, const void *src, + uint32_t size); + +/***************************************************************************** + * Name: spi_flash_write + * + * Description: + * + * Write data to Flash. + * + * Note: For fastest write performance, write a 4 byte aligned size at a + * 4 byte aligned offset in flash from a source buffer in DRAM. Varying + * any of these parameters will still work, but will be slower due to + * buffering. + * + * Writing more than 8KB at a time will be split into multiple + * write operations to avoid disrupting other tasks in the system. + * + * Parameters: + * dest_addr - Destination address in Flash. + * src - Pointer to the source buffer. + * size - Length of data, in bytes. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_write(uint32_t dest_addr, const void *src, uint32_t size); + +/***************************************************************************** + * Name: spi_flash_read + * + * Description: + * Read data from Flash. + * + * Note: For fastest read performance, all parameters should be + * 4 byte aligned. If source address and read size are not 4 byte + * aligned, read may be split into multiple flash operations. If + * destination buffer is not 4 byte aligned, a temporary buffer will + * be allocated on the stack. + * + * Reading more than 16KB of data at a time will be split + * into multiple reads to avoid disruption to other tasks in the + * system. Consider using spi_flash_mmap() to read large amounts + * of data. + * + * Parameters: + * src_addr - source address of the data in Flash. + * dest - pointer to the destination buffer + * size - length of data + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_read(uint32_t src_addr, void *dest, uint32_t size); + +/***************************************************************************** + * Name: spi_flash_erase_sector + * + * Description: + * Erase the Flash sector. + * + * Parameters: + * sector - Sector number, the count starts at sector 0, 4KB per sector. + * + * Returned Values: esp_err_t + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_erase_sector(uint32_t sector); + +/***************************************************************************** + * Name: spi_flash_erase_range + * + * Description: + * Erase a range of flash sectors + * + * Parameters: + * start_address - Address where erase operation has to start. + * Must be 4kB-aligned + * size - Size of erased range, in bytes. Must be divisible by + * 4kB. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_erase_range(uint32_t start_address, uint32_t size); + +/***************************************************************************** + * Name: spi_flash_cache_enabled + * + * Description: + * Check at runtime if flash cache is enabled on both CPUs. + * + * Returned Values: + * Return true if both CPUs have flash cache enabled, false otherwise. + * + *****************************************************************************/ + +bool spi_flash_cache_enabled(void); + +/***************************************************************************** + * Name: spi_flash_enable_cache + * + * Description: + * Re-enable cache for the core defined as cpuid parameter. + * + * Parameters: + * cpuid - core number to enable instruction cache for. + * + *****************************************************************************/ + +void spi_flash_enable_cache(uint32_t cpuid); + +/***************************************************************************** + * Public Data + *****************************************************************************/ + +extern const struct spiflash_legacy_data_s *rom_spiflash_legacy_data; + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ROM_ESP32S2_SPIFLASH_H */ diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs index 191eec16f6..48041c88f9 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs @@ -52,12 +52,6 @@ ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef ARCHWARNINGSXX = -Wall -Wshadow -Wundef ARCHPICFLAGS = -fpic -# if SPIRAM/PSRAM is used then we need to include a workaround - -ifeq ($(CONFIG_ESP32S2_SPIRAM),y) - ARCHCFLAGS += -mfix-esp32s2-psram-cache-issue -endif - CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld index ec17e1d484..25db27c30b 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2_rom.ld @@ -18,7 +18,7 @@ PROVIDE ( Cache_Clean_Items = 0x40018250 ); PROVIDE ( Cache_Config_DCache_Autoload = 0x40018794 ); PROVIDE ( Cache_Config_ICache_Autoload = 0x40018664 ); PROVIDE ( Cache_Count_Flash_Pages = 0x40018f70 ); -PROVIDE ( Cache_Dbus_MMU_Set = 0x40018eb0 ); +PROVIDE ( cache_dbus_mmu_set = 0x40018eb0 ); PROVIDE ( Cache_DCache_Preload_Done = 0x40018630 ); PROVIDE ( Cache_Disable_DCache = 0x40018c68 ); PROVIDE ( Cache_Disable_DCache_Autoload = 0x4001888c ); @@ -26,7 +26,7 @@ PROVIDE ( Cache_Disable_DCache_PreLock = 0x40018a5c ); PROVIDE ( Cache_Disable_ICache = 0x40018c2c ); PROVIDE ( Cache_Disable_ICache_Autoload = 0x4001875c ); PROVIDE ( Cache_Disable_ICache_PreLock = 0x4001892c ); -PROVIDE ( Cache_Enable_DCache = 0x40018d58 ); +PROVIDE ( cache_enable_dcache = 0x40018d58 ); PROVIDE ( Cache_Enable_DCache_Autoload = 0x40018874 ); PROVIDE ( Cache_Enable_DCache_PreLock = 0x400189f0 ); PROVIDE ( Cache_Enable_Defalut_DCache_Mode = 0x40018170 ); @@ -46,7 +46,7 @@ PROVIDE ( Cache_Get_Virtual_Addr = 0x40019210 ); PROVIDE ( cache_ibus_mmu_set = 0x40018df4 ); PROVIDE ( Cache_ICache_Preload_Done = 0x4001859c ); PROVIDE ( cache_invalidate_addr = 0x400182e4 ); -PROVIDE ( Cache_Invalidate_DCache_All = 0x4001842c ); +PROVIDE ( cache_invalidate_dcache_all = 0x4001842c ); PROVIDE ( Cache_Invalidate_DCache_Items = 0x40018208 ); PROVIDE ( cache_invalidate_icache_all = 0x40018420 ); PROVIDE ( Cache_Invalidate_ICache_Items = 0x400181b8 ); @@ -60,7 +60,7 @@ PROVIDE ( Cache_Resume_DCache = 0x40018d3c ); PROVIDE ( Cache_Resume_DCache_Autoload = 0x4001850c ); PROVIDE ( cache_resume_icache = 0x40018cdc ); PROVIDE ( Cache_Resume_ICache_Autoload = 0x400184c4 ); -PROVIDE ( Cache_Set_DCache_Mode = 0x40018074 ); +PROVIDE ( cache_set_dcache_mode = 0x40018074 ); PROVIDE ( Cache_Set_Default_Mode = 0x4001810c ); PROVIDE ( cache_set_icache_mode = 0x4001803c ); PROVIDE ( Cache_Start_DCache_Preload = 0x400185c4 ); @@ -74,8 +74,8 @@ PROVIDE ( Cache_Unlock_Addr = 0x40018b9c ); PROVIDE ( Cache_Unlock_DCache_Items = 0x40018ac8 ); PROVIDE ( Cache_Unlock_ICache_Items = 0x40018998 ); PROVIDE ( Cache_UnMask_Drom0 = 0x40018480 ); -PROVIDE ( Cache_WriteBack_Addr = 0x400183c8 ); -PROVIDE ( Cache_WriteBack_All = 0x40018444 ); +PROVIDE ( cache_writeback_addr = 0x400183c8 ); +PROVIDE ( cache_writeback_all = 0x40018444 ); PROVIDE ( Cache_WriteBack_Items = 0x40018298 ); PROVIDE ( cacl_rtc_memory_crc = 0x4000ffa0 ); PROVIDE ( cdc_acm_class_handle_req = 0x40013050 ); @@ -211,6 +211,9 @@ PROVIDE ( esp_rom_spi_flash_update_id = 0x40016e44 ); PROVIDE ( esp_rom_spi_reset_rw_mode = 0x40017984 ); PROVIDE ( esp_rom_spi_set_dtr_swap_mode = 0x40017b60 ); PROVIDE ( esp_rom_spi_set_op_mode = 0x400179e8 ); +PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); +PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); +PROVIDE ( esp_rom_spiflash_select_qio_pins = SelectSpiQIO ); PROVIDE ( _etext = 0x4001bed0 ); PROVIDE ( ets_aes_block = 0x4000d610 ); PROVIDE ( ets_aes_disable = 0x4000d4f8 );