Add an NSH configuration for the NuTiny-SDK-NUC120. Still does not work
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5678 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
00143c4401
commit
c254d0bb3e
22
arch/Kconfig
22
arch/Kconfig
@ -303,12 +303,22 @@ config ARCH_RAMFUNCS
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comment "Board Settings"
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comment "Board Settings"
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config BOARD_LOOPSPERMSEC
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config BOARD_LOOPSPERMSEC
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int "Loops per millisecond"
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int "Delay loops per millisecond"
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help
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default 5000
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Must be calibrated for correct operation of delay loops.
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---help---
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You simply use a stop watch to measure the 100 second delay
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Simple delay loops are used by some logic, especially during boot-up,
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then adjust CONFIG_BOARD_LOOPSPERMSEC until it is actually
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driver initialization. These delay loops must be calibrated for each
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is 100 seconds.
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board in order to assure accurate timing by the delay loops.
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config ARCH_CALIBRATION
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bool "Calibrate delay loop"
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default n
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---help---
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Enables some built in instrumentation that causes a 100 second delay
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during boot-up. This 100 second delay serves no purpose other than it
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allows you to calibratre BOARD_LOOPSPERMSEC. You simply use a stop
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watch to measure the actual delay then adjust BOARD_LOOPSPERMSEC until
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the actual delay is 100 seconds.
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config DRAM_START
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config DRAM_START
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hex "DRAM start physical address"
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hex "DRAM start physical address"
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@ -251,22 +251,6 @@ config PAGING
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If set =y in your configation file, this setting will enable the on-demand
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If set =y in your configation file, this setting will enable the on-demand
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paging feature as described in http://www.nuttx.org/NuttXDemandPaging.html.
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paging feature as described in http://www.nuttx.org/NuttXDemandPaging.html.
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config BOARD_LOOPSPERMSEC
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int "Delay loops per millisecond"
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default 5000
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---help---
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Delay loops nust be calibrated for correct operation.
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config ARCH_CALIBRATION
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bool "Calibrate delay loop"
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default n
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---help---
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Enables some built in instrumentation that causes a 100 second delay
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during boot-up. This 100 second delay serves no purpose other than it
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allows you to calibratre BOARD_LOOPSPERMSEC. You simply use a stop
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watch to measure the 100 second delay then adjust BOARD_LOOPSPERMSEC until
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the delay actually is 100 seconds.
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config DEBUG_HARDFAULT
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config DEBUG_HARDFAULT
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bool "Verbose Hard-Fault Debug"
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bool "Verbose Hard-Fault Debug"
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default n
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default n
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@ -299,7 +299,7 @@ void nuc_lowsetup(void)
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#endif
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#endif
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#if NUC_CONSOLE_2STOP != 0
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#if NUC_CONSOLE_2STOP != 0
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revgval |= UART_LCR_NSB;
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regval |= UART_LCR_NSB;
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#endif
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#endif
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putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_LCR_OFFSET);
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putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_LCR_OFFSET);
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@ -242,86 +242,64 @@ static uart_dev_t g_uart2port =
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};
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};
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#endif /* CONFIG_NUC_UART2 */
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#endif /* CONFIG_NUC_UART2 */
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/* Which UART with be tty0/console and which tty1? tty2? */
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/* Which UART with be tty0/console and which tty1? tty2? The console, if it
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* exists, will always be ttyS0. If there is no console then will use the
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* lowest numbered UART.
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*/
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#ifdef HAVE_CONSOLE
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/* First pick the console and ttys0. This could be any of UART0-2 */
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# if defined(CONFIG_UART0_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart0port /* UART0=console */
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#if defined(CONFIG_UART0_SERIAL_CONSOLE)
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# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */
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# define CONSOLE_DEV g_uart0port /* UART0 is console */
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# ifdef CONFIG_NUC_UART1
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# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
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# define TTYS1_DEV g_uart1port /* UART0=ttyS0;UART1=ttyS1 */
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# define UART0_ASSIGNED 1
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# ifdef CONFIG_NUC_UART2
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define TTYS2_DEV g_uart2port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2 */
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# define CONSOLE_DEV g_uart1port /* UART1 is console */
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# else
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# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
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# undef TTYS2_DEV /* UART0=ttyS0;UART1=ttyS1;No ttyS2*/
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# define UART1_ASSIGNED 1
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart2port /* UART2 is console */
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# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
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# define UART2_ASSIGNED 1
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#else
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# undef CONSOLE_DEV /* No console */
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# if defined(CONFIG_NUC_UART0)
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# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
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# define UART0_ASSIGNED 1
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# elif defined(CONFIG_NUC_UART1)
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# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
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# define UART1_ASSIGNED 1
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# elif defined(CONFIG_NUC_UART2)
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# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
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# define UART2_ASSIGNED 1
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# endif
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# endif
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# else
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#endif
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# ifdef CONFIG_NUC_UART2
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# define TTYS1_DEV g_uart2port /* UART0=ttyS0;UART2=ttyS1 */
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/* Pick ttys1. This could be any two of UART0-2 excluding the console UART. */
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# undef TTYS2_DEV /* UART0=ttyS0;UART2=ttyS1;No ttyS2*/
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# else
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#if defined(CONFIG_NUC_UART0) && !defined(UART0_ASSIGNED)
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# undef TTYS1_DEV /* UART0=ttyS0;No ttyS1;No ttyS2 */
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# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */
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# undef TTYS2_DEV /* No ttyS2 */
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# define UART0_ASSIGNED 1
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# endif
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#elif defined(CONFIG_NUC_UART1) && !defined(UART1_ASSIGNED)
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# endif
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# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */
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# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define UART1_ASSIGNED 1
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# define CONSOLE_DEV g_uart1port /* UART1=console */
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#elif defined(CONFIG_NUC_UART2) && !defined(UART2_ASSIGNED)
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# define TTYS0_DEV g_uart1port /* UART1=ttyS0 */
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# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */
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# ifdef CONFIG_NUC_UART0
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# define UART2_ASSIGNED 1
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# define TTYS1_DEV g_uart0port /* UART1=ttyS0;UART0=ttyS1 */
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#endif
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# ifdef CONFIG_NUC_UART2
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# define TTYS2_DEV g_uart2port /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2 */
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/* Pick ttys2. This could be one of UART1-2. It can't be UART0 because that
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# else
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* was either assigned as ttyS0 or ttys1. One of UART 1-2 could also be the
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# undef TTYS2_DEV /* UART1=ttyS0;UART0=ttyS1;No ttyS2 */
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* console.
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# endif
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*/
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# else
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# ifdef CONFIG_NUC_UART2
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#if defined(CONFIG_NUC_UART1) && !defined(UART1_ASSIGNED)
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# define TTYS1_DEV g_uart2port /* UART1=ttyS0;UART2=ttyS1 */
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# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */
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# undef TTYS2_DEV /* UART1=ttyS0;UART2=ttyS1;No ttyS2 */
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# define UART1_ASSIGNED 1
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# else
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#elif defined(CONFIG_NUC_UART2) && !defined(UART2_ASSIGNED)
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# undef TTYS1_DEV /* UART1=ttyS0;No ttyS1;No ttyS2 */
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# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */
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# undef TTYS2_DEV /* No ttyS2 */
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# define UART2_ASSIGNED 1
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# endif
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#endif
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# endif
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# elif defined(CONFIG_UART2_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart2port /* UART2=console */
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# define TTYS0_DEV g_uart2port /* UART2=ttyS0 */
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# ifdef CONFIG_NUC_UART2
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# define TTYS1_DEV g_uart0port /* UART2=ttyS0;UART0=ttyS1 */
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# ifdef CONFIG_NUC_UART1
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# define TTYS2_DEV g_uart1port /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2 */
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# else
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# undef TTYS2_DEV /* UART2=ttyS0;UART0=ttyS1;No ttyS2 */
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# endif
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# else
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# ifdef CONFIG_NUC_UART1
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# define TTYS1_DEV g_uart1port /* UART2=ttyS0;UART1=ttyS1 */
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# undef TTYS2_DEV /* UART2=ttyS0;UART1=ttyS1;No ttyS2 */
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# else
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# undef TTYS1_DEV /* UART2=ttyS0;No ttyS1;No ttyS2 */
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# undef TTYS2_DEV /* No ttyS2 */
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# endif
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# endif
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# endif
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#else /* No console */
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# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */
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# ifdef CONFIG_NUC_UART1
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# define TTYS1_DEV g_uart1port /* UART0=ttyS0;UART1=ttyS1 */
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# ifdef CONFIG_NUC_UART2
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# define TTYS2_DEV g_uart2port /* UART0=ttyS0;UART1=ttyS1;UART2=ttyS2 */
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# else
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# undef TTYS2_DEV /* UART0=ttyS0;UART1=ttyS1;No ttyS2 */
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# endif
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# else
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# ifdef CONFIG_NUC_UART2
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# define TTYS1_DEV g_uart2port /* UART0=ttyS0;UART2=ttyS1 */
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# undef TTYS2_DEV /* UART0=ttyS0;UART2=ttyS1;No ttyS2 */
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# else
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# undef TTYS1_DEV /* UART0=ttyS0;No ttyS1;No ttyS2 */
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# undef TTYS2_DEV /* No ttyS2 */
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# endif
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# endif
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#endif /* HAVE_CONSOLE */
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/****************************************************************************
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/****************************************************************************
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* Inline Functions
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* Inline Functions
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@ -391,46 +369,61 @@ static int up_setup(struct uart_dev_s *dev)
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/* Reset the TX FIFO */
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/* Reset the TX FIFO */
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regval = up_serialin(priv, NUC_UART_FCR_OFFSET
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regval = up_serialin(priv, NUC_UART_FCR_OFFSET);
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regval |= UART_FCR_TFR
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up_serialout(priv, NUC_UART_FCR_OFFSET, regval | UART_FCR_TFR);
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up_serialout(priv, NUC_UART_FCR_OFFSET, regval);
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/* Reset the RX FIFO */
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/* Reset the RX FIFO */
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regval = up_serialin(priv, NUC_UART_FCR_OFFSET
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up_serialout(priv, NUC_UART_FCR_OFFSET, regval | UART_FCR_RFR);
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regval |= UART_FCR_RFR
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up_serialout(priv, NUC_UART_FCR_OFFSET, regval);
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/* Set Rx Trigger Level */
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/* Set Rx Trigger Level */
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regval &= ~UART_FCR_FRITL_MASK;
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regval &= ~(UART_FCR_FRITL_MASK | UART_FCR_TFR | UART_FCR_RFR);
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regval |= UART_FCR_FRITL_4;
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regval |= UART_FCR_FRITL_4;
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up_serialout(priv, NUC_UART_FCR_OFFSET, regval);
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up_serialout(priv, NUC_UART_FCR_OFFSET, regval);
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/* Set Parity & Data bits and Stop bits */
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/* Set Parity & Data bits and Stop bits */
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regval = 0;
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regval = 0;
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#if NUC_CONSOLE_BITS == 5
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switch (priv->bits)
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{
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case 5:
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regval |= UART_LCR_WLS_5;
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regval |= UART_LCR_WLS_5;
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#elif NUC_CONSOLE_BITS == 6
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break;
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case 6:
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regval |= UART_LCR_WLS_6;
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regval |= UART_LCR_WLS_6;
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#elif NUC_CONSOLE_BITS == 7
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break;
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case 7:
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regval |= UART_LCR_WLS_7;
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regval |= UART_LCR_WLS_7;
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#elif NUC_CONSOLE_BITS == 8
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break;
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default:
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case 8:
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regval |= UART_LCR_WLS_8;
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regval |= UART_LCR_WLS_8;
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#else
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break;
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error "Unknown console UART data width"
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}
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#endif
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#if NUC_CONSOLE_PARITY == 1
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switch (priv->parity)
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{
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default:
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case 0:
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break;
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case 1:
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regval |= UART_LCR_PBE;
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regval |= UART_LCR_PBE;
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#elif NUC_CONSOLE_PARITY == 2
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break;
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regval |= (UART_LCR_PBE | UART_LCR_EPE);
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#endif
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#if NUC_CONSOLE_2STOP != 0
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case 2:
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revgval |= UART_LCR_NSB;
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regval |= (UART_LCR_PBE | UART_LCR_EPE);
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#endif
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break;
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}
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if (priv->stopbits2)
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{
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regval |= UART_LCR_NSB;
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}
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up_serialout(priv, NUC_UART_LCR_OFFSET, regval);
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up_serialout(priv, NUC_UART_LCR_OFFSET, regval);
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@ -441,7 +434,7 @@ static int up_setup(struct uart_dev_s *dev)
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/* Set the baud */
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/* Set the baud */
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nuc_setbaud(CONSOLE_BASE, CONSOLE_BAUD);
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nuc_setbaud(priv->uartbase, priv->baud);
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/* Set up the IER */
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/* Set up the IER */
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@ -597,28 +590,25 @@ static int up_interrupt(int irq, void *context)
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{
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{
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/* REVISIT: Do we clear this be reading the modem status register? */
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/* REVISIT: Do we clear this be reading the modem status register? */
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volatile uint32_t status = up_serialin(priv, NUC_UART_MSR_OFFSET);
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(void)up_serialin(priv, NUC_UART_MSR_OFFSET);
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vdbg("MSR: %08x\n", status);
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}
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}
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/* Check for line status */
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/* Check for line status */
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if ((status & UART_ISR_RLS_INT) != 0)
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if ((status & UART_ISR_RLS_INT) != 0)
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{
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{
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/* REVISIT: Do we clear this be reading the line status register? */
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/* REVISIT: Do we clear this be reading the FIFO status register? */
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volatile uint32_t status = up_serialin(priv, NUC_UART_FSR_OFFSET);
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(void)up_serialin(priv, NUC_UART_FSR_OFFSET);
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vdbg("LSR: %08x\n", status);
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}
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}
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/* Check for buffer errors */
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/* Check for buffer errors */
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if ((status & UART_ISR_BUF_ERR_INT) != 0)
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if ((status & UART_ISR_BUF_ERR_INT) != 0)
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{
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{
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/* REVISIT: Do we clear this be reading the line status register? */
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/* REVISIT: Do we clear this by reading the FIFO status register? */
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volatile uint32_t status = up_serialin(priv, NUC_UART_MSR_OFFSET);
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(void)up_serialin(priv, NUC_UART_FSR_OFFSET);
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vdbg("MSR: %08x\n", status);
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}
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}
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}
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}
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@ -651,7 +641,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
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}
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}
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else
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else
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{
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{
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memcpy(user, dev, sizeof(struct nuc_dev_s));
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memcpy(user, priv, sizeof(struct nuc_dev_s));
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}
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}
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}
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}
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break;
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break;
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@ -754,7 +744,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
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{
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{
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#ifndef CONFIG_SUPPRESS_SERIAL_INTS
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#ifndef CONFIG_SUPPRESS_SERIAL_INTS
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priv->ier |= (UART_IER_RDA_IEN | UART_IER_RLS_IEN | UART_IER_RTO_IEN |
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priv->ier |= (UART_IER_RDA_IEN | UART_IER_RLS_IEN | UART_IER_RTO_IEN |
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UART_IER_BUF_ERR_IEN UART_IER_TIME_OUT_EN);
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UART_IER_BUF_ERR_IEN | UART_IER_TIME_OUT_EN);
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#endif
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#endif
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}
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}
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else
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else
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|
|||||||
@ -32,22 +32,6 @@ config ARCH_CHIP
|
|||||||
string
|
string
|
||||||
default "pic32mx" if ARCH_CHIP_PIC32MX
|
default "pic32mx" if ARCH_CHIP_PIC32MX
|
||||||
|
|
||||||
config BOARD_LOOPSPERMSEC
|
|
||||||
int "Delay loops per millisecond"
|
|
||||||
default 5000
|
|
||||||
---help---
|
|
||||||
Delay loops nust be calibrated for correct operation.
|
|
||||||
|
|
||||||
config ARCH_CALIBRATION
|
|
||||||
bool "Calibrate delay loop"
|
|
||||||
default n
|
|
||||||
---help---
|
|
||||||
Enables some built in instrumentation that causes a 100 second delay
|
|
||||||
during boot-up. This 100 second delay serves no purpose other than it
|
|
||||||
allows you to calibratre BOARD_LOOPSPERMSEC. You simply use a stop
|
|
||||||
watch to measure the 100 second delay then adjust BOARD_LOOPSPERMSEC until
|
|
||||||
the delay actually is 100 seconds.
|
|
||||||
|
|
||||||
source arch/mips/src/common/Kconfig
|
source arch/mips/src/common/Kconfig
|
||||||
source arch/mips/src/mips32/Kconfig
|
source arch/mips/src/mips32/Kconfig
|
||||||
source arch/mips/src/pic32mx/Kconfig
|
source arch/mips/src/pic32mx/Kconfig
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user