From c263fe1c8b60e663a25989aeaf091c2a48361a36 Mon Sep 17 00:00:00 2001 From: Frank Benkert Date: Wed, 24 Feb 2016 13:47:15 -0600 Subject: [PATCH] SAMV7 SPI: Add support for Peripheral Chip Select Decoding to address up to 15 slaved --- arch/arm/src/samv7/Kconfig | 6 +++ arch/arm/src/samv7/sam_spi.c | 12 ++++++ arch/arm/src/samv7/sam_spi.h | 81 ++++++++++++++++++++++++++++-------- 3 files changed, 81 insertions(+), 18 deletions(-) diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 0e50a701e1..54bafb2b81 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -738,6 +738,12 @@ endchoice # SPI1 Configuration if SAMV7_SPI_MASTER comment "SPI Master Configuration" +config SAMV7_SPI_CS_DECODING + bool "SPI Peripheral Chip Select Decoding" + default n + ---help--- + Use Peripheral Chip Select Decoding on SPI Master + config SAMV7_SPI_DMA bool "SPI DMA" default n diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 6862577b7f..86278209a4 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -601,7 +601,11 @@ static inline void spi_flush(struct sam_spidev_s *spi) static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics) { +#ifndef CONFIG_SAMV7_SPI_CS_DECODING return ((uint32_t)1 << (spics->cs)) - 1; +#else + return spics->cs; +#endif } /**************************************************************************** @@ -1843,6 +1847,14 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port) } #endif +#if defined(CONFIG_SAMV7_SPI_CS_DECODING) + /* Enable Peripheral Chip Select Decoding? */ + + regval = spi_getreg(spi, SAM_SPI_MR_OFFSET); + regval |= SPI_MR_PCSDEC; + spi_putreg(spi, regval, SAM_SPI_MR_OFFSET); +#endif + /* Disable SPI clocking */ spi_putreg(spi, SPI_CR_SPIDIS, SAM_SPI_CR_OFFSET); diff --git a/arch/arm/src/samv7/sam_spi.h b/arch/arm/src/samv7/sam_spi.h index 7bbb4d6f35..f3b15ab7f6 100644 --- a/arch/arm/src/samv7/sam_spi.h +++ b/arch/arm/src/samv7/sam_spi.h @@ -63,26 +63,71 @@ * sam_spibus_initialize(). */ -#define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */ -#define __SPI_CS_MASK (3 << __SPI_CS_SHIFT) -# define __SPI_CS0 (0 << __SPI_CS_SHIFT) -# define __SPI_CS1 (1 << __SPI_CS_SHIFT) -# define __SPI_CS2 (2 << __SPI_CS_SHIFT) -# define __SPI_CS3 (3 << __SPI_CS_SHIFT) -#define __SPI_SPI_SHIFT (2) /* Bit 2: SPI controller number */ -#define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT) -# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */ -# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */ +#ifdef CONFIG_SAMV7_SPI_CS_DECODING +# define __SPI_CS_SHIFT (0) /* Bits 0-3: SPI chip select number */ +# define __SPI_CS_MASK (15 << __SPI_CS_SHIFT) -#define SPI0_CS0 (__SPI_SPI0 | __SPI_CS0) -#define SPI0_CS1 (__SPI_SPI0 | __SPI_CS1) -#define SPI0_CS2 (__SPI_SPI0 | __SPI_CS2) -#define SPI0_CS3 (__SPI_SPI0 | __SPI_CS3) +# define __SPI_SPI_SHIFT (4) /* Bit 4: SPI controller number */ +# define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT) +# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */ +# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */ -#define SPI1_CS0 (__SPI_SPI1 | __SPI_CS0) -#define SPI1_CS1 (__SPI_SPI1 | __SPI_CS1) -#define SPI1_CS2 (__SPI_SPI1 | __SPI_CS2) -#define SPI1_CS3 (__SPI_SPI1 | __SPI_CS3) +# define SPI0_CS0 (__SPI_SPI0 | 1) +# define SPI0_CS1 (__SPI_SPI0 | 2) +# define SPI0_CS2 (__SPI_SPI0 | 3) +# define SPI0_CS3 (__SPI_SPI0 | 4) +# define SPI0_CS4 (__SPI_SPI0 | 5) +# define SPI0_CS5 (__SPI_SPI0 | 6) +# define SPI0_CS6 (__SPI_SPI0 | 7) +# define SPI0_CS7 (__SPI_SPI0 | 8) +# define SPI0_CS8 (__SPI_SPI0 | 9) +# define SPI0_CS9 (__SPI_SPI0 | 10) +# define SPI0_CS10 (__SPI_SPI0 | 11) +# define SPI0_CS11 (__SPI_SPI0 | 12) +# define SPI0_CS12 (__SPI_SPI0 | 13) +# define SPI0_CS13 (__SPI_SPI0 | 14) +# define SPI0_CS14 (__SPI_SPI0 | 15) + +# define SPI1_CS0 (__SPI_SPI1 | 1) +# define SPI1_CS1 (__SPI_SPI1 | 2) +# define SPI1_CS2 (__SPI_SPI1 | 3) +# define SPI1_CS3 (__SPI_SPI1 | 4) +# define SPI1_CS4 (__SPI_SPI1 | 5) +# define SPI1_CS5 (__SPI_SPI1 | 6) +# define SPI1_CS6 (__SPI_SPI1 | 7) +# define SPI1_CS7 (__SPI_SPI1 | 8) +# define SPI1_CS8 (__SPI_SPI1 | 9) +# define SPI1_CS9 (__SPI_SPI1 | 10) +# define SPI1_CS10 (__SPI_SPI1 | 11) +# define SPI1_CS11 (__SPI_SPI1 | 12) +# define SPI1_CS12 (__SPI_SPI1 | 13) +# define SPI1_CS13 (__SPI_SPI1 | 14) +# define SPI1_CS14 (__SPI_SPI1 | 15) + +#else /* CONFIG_SAMV7_SPI_CS_DECODING */ + +# define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */ +# define __SPI_CS_MASK (3 << __SPI_CS_SHIFT) +# define __SPI_CS0 (0 << __SPI_CS_SHIFT) +# define __SPI_CS1 (1 << __SPI_CS_SHIFT) +# define __SPI_CS2 (2 << __SPI_CS_SHIFT) +# define __SPI_CS3 (3 << __SPI_CS_SHIFT) +# define __SPI_SPI_SHIFT (2) /* Bit 2: SPI controller number */ +# define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT) +# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */ +# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */ + +# define SPI0_CS0 (__SPI_SPI0 | __SPI_CS0) +# define SPI0_CS1 (__SPI_SPI0 | __SPI_CS1) +# define SPI0_CS2 (__SPI_SPI0 | __SPI_CS2) +# define SPI0_CS3 (__SPI_SPI0 | __SPI_CS3) + +# define SPI1_CS0 (__SPI_SPI1 | __SPI_CS0) +# define SPI1_CS1 (__SPI_SPI1 | __SPI_CS1) +# define SPI1_CS2 (__SPI_SPI1 | __SPI_CS2) +# define SPI1_CS3 (__SPI_SPI1 | __SPI_CS3) + +#endif /* CONFIG_SAMV7_SPI_CS_DECODING */ /**************************************************************************** * Public Types