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Misc fixes to get SDRAM support and RAM test to build for the Open1788 platform

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5793 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-03-27 14:28:43 +00:00
parent 43fa294ec9
commit c28bc0f195
4 changed files with 82 additions and 83 deletions
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16
configs/open1788/README.txt
View File

@ -411,3 +411,19 @@ CONFIGURATION
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain
CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain
3. This NSH has support for built-in applications enabled, however,
no built-in configurations are built in the defulat configuration.
4. This configuration has been used for verifying SDRAM by modifying
the configuration in the following ways:
CONFIG_LPC17_EMC=y : Enable the EMC
CONFIG_ARCH_EXTDRAM=y : Configure external DRAM
CONFIG_ARCH_EXTDRAMSIZE=67108864 : DRAM size 2x256/8 = 64MB
CONFIG_SYSTEM_RAMTEST=y : Enable the RAM test built-in
In this configuration, the SDRAM is not added to heap and so is
not excessible to the applications. So the RAM test can be
freely executed against the SRAM memory beginning at address
0xa000:0000 (CS0).

42
configs/open1788/include/board.h
View File

@ -114,21 +114,29 @@
/* PLL1 : PLL1 is used to generate clock for the USB */
#undef CONFIG_LPC17_PLL1
//~ #define CONFIG_LPC17_PLL1 1
#define BOARD_PLL1CFG_MSEL 4
#define BOARD_PLL1CFG_PSEL 2
#define BOARD_PLL1CFG_VALUE \
(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
#if defined(CONFIG_LPC17_USBHOST) || (CONFIG_LPC17_USBDEV)
#ifdef CONFIG_LPC17_EMC
/* EMC clock selection.
*
* The EMC uses the CPU clock undivided.
*/
/* USB divider. The output of the PLL is used as the USB clock
# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV1
# define LPC17_EMCCLK LPC17_CCLK
#endif
#if defined(CONFIG_LPC17_USBHOST) || (CONFIG_LPC17_USBDEV)
/* USB divider. The output of the PLL is used as the USB clock
*
* USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz
*/
#define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \
# define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \
SYSCON_USBCLKSEL_USBSEL_PLL1)
#endif
@ -145,28 +153,30 @@
#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20
#ifdef CONFIG_LPC17_SDCARD
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
* to service FIFOs in interrupt driven mode.
* SDCARD_CLOCK=PCLK/(2*(SDCARD_CLKDIV+1))
*/
#define SDCARD_CLKDIV_INIT 74 /* 400Khz */
#define SDCARD_INIT_CLKDIV (SDCARD_CLKDIV_INIT)
# define SDCARD_CLKDIV_INIT 74 /* 400Khz */
# define SDCARD_INIT_CLKDIV (SDCARD_CLKDIV_INIT)
#define SDCARD_NORMAL_CLKDIV 1 /* DMA ON: SDCARD_CLOCK=15MHz */
# define SDCARD_NORMAL_CLKDIV 1 /* DMA ON: SDCARD_CLOCK=15MHz */
#define SDCARD_SLOW_CLKDIV 14 /* DMA OFF: SDCARD_CLOCK=2MHz */
#ifdef CONFIG_SDIO_DMA
# define SDCARD_MMCXFR_CLKDIV (SDCARD_NORMAL_CLKDIV)
#else
# define SDCARD_MMCXFR_CLKDIV (SDCARD_SLOW_CLKDIV)
#endif
# ifdef CONFIG_SDIO_DMA
# define SDCARD_MMCXFR_CLKDIV (SDCARD_NORMAL_CLKDIV)
# else
# define SDCARD_MMCXFR_CLKDIV (SDCARD_SLOW_CLKDIV)
# endif
#ifdef CONFIG_SDIO_DMA
# define SDCARD_SDXFR_CLKDIV (SDCARD_NORMAL_CLKDIV)
#else
# define SDCARD_SDXFR_CLKDIV (SDCARD_SLOW_CLKDIV)
# ifdef CONFIG_SDIO_DMA
# define SDCARD_SDXFR_CLKDIV (SDCARD_NORMAL_CLKDIV)
# else
# define SDCARD_SDXFR_CLKDIV (SDCARD_SLOW_CLKDIV)
# endif
#endif
/* Set EMC delay values:

54
configs/open1788/nsh/defconfig
View File

@ -92,6 +92,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
# CONFIG_GPIO_IRQ is not set
#
# LPC17xx Configuration Options
@ -169,54 +170,16 @@ CONFIG_LPC17_GPDMA=y
# CONFIG_SERIAL_TERMIOS is not set
# CONFIG_UART0_FLOWCONTROL is not set
#
# ADC driver options
#
#
# CAN driver options
#
# CONFIG_GPIO_IRQ is not set
#
# I2C driver options
#
#
# SDIO Configuration
#
# CONFIG_SDIO_DMA is not set
CONFIG_SDIO_DMAPRIO=0x0
# CONFIG_SDIO_WIDTH_D1_ONLY is not set
#
# Ethernet driver options
#
#
# USB device driver options
#
#
# USB host driver options
#
#
# External Memory Configuration
#
CONFIG_ARCH_HAVE_EXTNAND=y
CONFIG_ARCH_HAVE_EXTNOR=y
CONFIG_ARCH_HAVE_EXTDRAM=y
CONFIG_ARCH_HAVE_EXTSRAM0=y
CONFIG_ARCH_EXTNAND=y
CONFIG_ARCH_EXTNANDSIZE=134217728
CONFIG_ARCH_EXTNOR=y
CONFIG_ARCH_EXTNORSIZE=4194304
CONFIG_ARCH_EXTDRAM=y
CONFIG_ARCH_EXTDRAMSIZE=67108864
CONFIG_ARCH_EXTDRAMHEAP=y
CONFIG_ARCH_EXTSRAM0=y
CONFIG_ARCH_EXTSRAM0SIZE=131072
CONFIG_ARCH_EXTSRAM0HEAP=y
#
# Architecture Options
@ -231,6 +194,8 @@ CONFIG_ARCH_HAVE_VFORK=y
CONFIG_ARCH_STACKDUMP=y
# CONFIG_ENDIAN_BIG is not set
# CONFIG_ARCH_HAVE_RAMFUNCS is not set
CONFIG_ARCH_HAVE_RAMVECTORS=y
# CONFIG_ARCH_RAMVECTORS is not set
#
# Board Settings
@ -424,6 +389,7 @@ CONFIG_FAT_MAXFNAME=32
# CONFIG_FAT_DMAMEMORY is not set
# CONFIG_FS_NXFFS is not set
CONFIG_FS_ROMFS=y
# CONFIG_FS_BINFS is not set
#
# System Logging
@ -451,7 +417,7 @@ CONFIG_MM_REGIONS=2
# CONFIG_BINFMT_EXEPATH is not set
# CONFIG_NXFLAT is not set
# CONFIG_ELF is not set
# CONFIG_BUILTIN is not set
CONFIG_BUILTIN=y
# CONFIG_PIC is not set
CONFIG_SYMTAB_ORDEREDBYNAME=y
@ -507,6 +473,7 @@ CONFIG_SCHED_WORKSTACKSIZE=2048
#
# Built-In Applications
#
CONFIG_BUILTIN_PROXY_STACKSIZE=1024
#
# Examples
@ -541,7 +508,6 @@ CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_OSTEST is not set
# CONFIG_EXAMPLES_PASHELLO is not set
# CONFIG_EXAMPLES_PIPE is not set
# CONFIG_EXAMPLES_POLL is not set
# CONFIG_EXAMPLES_POSIXSPAWN is not set
# CONFIG_EXAMPLES_QENCODER is not set
# CONFIG_EXAMPLES_RGMP is not set
@ -600,6 +566,7 @@ CONFIG_EXAMPLES_NSH=y
# NSH Library
#
CONFIG_NSH_LIBRARY=y
CONFIG_NSH_BUILTIN_APPS=y
#
# Disable Individual commands
@ -680,6 +647,11 @@ CONFIG_NSH_ARCHINIT=y
#
# CONFIG_SYSTEM_INSTALL is not set
#
# RAM Test
#
# CONFIG_SYSTEM_RAMTEST is not set
#
# readline()
#

53
configs/open1788/src/lpc17_sdraminitialize.c
View File

@ -54,10 +54,24 @@
/************************************************************************************
* Definitions
************************************************************************************/
/* The core clock is LPC17_EMCCLK which may be either LPC17_CCLK* (undivided), or
* LPC17_CCLK / 2 as determined by settings in the board.h header file.
*
* For example:
* LPC17_CCLCK = 120,000,000
* EMCCLKSEL -> use LPC17_CCLK undivided
* LPC17_EMCCLK = 120,000,000
* LPC17_EMCCLK_MHZ = 120 (rounded)
* EMC_NSPERCLK = 8 (rounded)
*/
#define EMC_NS2CLK(ns, npc) ((ns + npc - 1) / npc)
#define LPC17_EMCCLK_MHZ ((LPC17_EMCCLK + 500000) / 1000000)
#define EMC_NSPERCLK ((1000 + (LPC17_EMCCLK_MHZ >> 1)) / LPC17_EMCCLK_MHZ)
#define EMC_NS2CLK(ns) ((ns + (EMC_NSPERCLK - 1)) / EMC_NSPERCLK)
#define MDKCFG_RASCAS0VAL 0x00000303
/* Set up for 32-bit SDRAM at CS0 */
#define CONFIG_ARCH_SDRAM_32BIT
#ifdef CONFIG_ARCH_SDRAM_16BIT
@ -88,8 +102,6 @@
void lpc17_sdram_initialize(void)
{
uint32_t mhz;
uint32_t ns_per_clk;
uint32_t regval;
#ifdef CONFIG_ARCH_SDRAM_16BIT
volatile uint16_t dummy;
@ -119,30 +131,19 @@ void lpc17_sdram_initialize(void)
SYSCON_EMCDLYCTL_CLKOUT1DLY(1);
putreg32(regval, LPC17_SYSCON_EMCDLYCTL);
/* The core clock is PLL0CLK:
*
* PLL0CLK = (2 * PLL0_M * SYSCLK) / PLL0_D
*/
mhz = PLL0CLK / 1000000;
#if BOARD_CLKSRCSEL_VALUE == SYSCON_CLKSRCSEL_MAIN
mhz >>= 1;
#endif
ns_per_clk = 1000 / mhz;
/* Configure the SDRAM */
putreg32( EMC_NS2CLK(20, ns_per_clk), LPC17_EMC_DYNAMICRP); /* TRP = 20 nS */
putreg32( 15, LPC17_EMC_DYNAMICRAS); /* RAS = 42ns to 100K ns, */
putreg32( 0, LPC17_EMC_DYNAMICSREX); /* TSREX = 1 clock */
putreg32( 1, LPC17_EMC_DYNAMICAPR); /* TAPR = 2 clocks? */
putreg32(EMC_NS2CLK(20, ns_per_clk) + 2, LPC17_EMC_DYNAMICDAL); /* TDAL = TRP + TDPL = 20ns + 2clk */
putreg32( 1, LPC17_EMC_DYNAMICWR); /* TWR = 2 clocks */
putreg32( EMC_NS2CLK(63, ns_per_clk), LPC17_EMC_DYNAMICRC); /* H57V2562GTR-75C TRC = 63ns(min)*/
putreg32( EMC_NS2CLK(63, ns_per_clk, LPC17_EMC_DYNAMICRFC); /* H57V2562GTR-75C TRFC = TRC */
putreg32( 15, LPC17_EMC_DYNAMICXSR); /* Exit self-refresh to active */
putreg32( EMC_NS2CLK(63, ns_per_clk), LPC17_EMC_DYNAMICRRD); /* 3 clock, TRRD = 15ns (min) */
putreg32( 1, LPC17_EMC_DYNAMICMRD); /* 2 clock, TMRD = 2 clocks (min) */
putreg32( EMC_NS2CLK(20), LPC17_EMC_DYNAMICRP); /* TRP = 20 nS */
putreg32( 15, LPC17_EMC_DYNAMICRAS); /* RAS = 42ns to 100K ns, */
putreg32( 0, LPC17_EMC_DYNAMICSREX); /* TSREX = 1 clock */
putreg32( 1, LPC17_EMC_DYNAMICAPR); /* TAPR = 2 clocks? */
putreg32(EMC_NS2CLK(20) + 2, LPC17_EMC_DYNAMICDAL); /* TDAL = TRP + TDPL = 20ns + 2clk */
putreg32( 1, LPC17_EMC_DYNAMICWR); /* TWR = 2 clocks */
putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRC); /* H57V2562GTR-75C TRC = 63ns(min)*/
putreg32( EMC_NS2CLK(63, LPC17_EMC_DYNAMICRFC); /* H57V2562GTR-75C TRFC = TRC */
putreg32( 15, LPC17_EMC_DYNAMICXSR); /* Exit self-refresh to active */
putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRRD); /* 3 clock, TRRD = 15ns (min) */
putreg32( 1, LPC17_EMC_DYNAMICMRD); /* 2 clock, TMRD = 2 clocks (min) */
/* Command delayed strategy, using EMCCLKDELAY */
@ -195,7 +196,7 @@ void lpc17_sdram_initialize(void)
regval = 64000000 / (1 << 13);
regval -= 16;
regval >>= 4;
regval = regval * mhz / 1000;
regval = regval * LPC17_EMCCLK_MHZ / 1000;
putreg32(regval, LPC17_EMC_DYNAMICREFRESH);
/* Issue MODE command */