SM4L: USB clock configuration and WDT register definition file
This commit is contained in:
Gregory Nutt
parent
0173b72281
commit
c28bf69735
@ -285,7 +285,7 @@ config SAM34_CATB
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depends on ARCH_CHIP_SAM4L
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config SAM34_LCDCA
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bool " LCD Controller A"
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bool "LCD Controller A"
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default n
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depends on ARCH_CHIP_SAM4L
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@ -349,7 +349,6 @@ config SAM34_AST
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config SAM34_WDT
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bool "Watchdog Timer"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_EIC
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bool "External Interrupt Controller"
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@ -363,7 +362,7 @@ config SAM34_HSMCI
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endmenu
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menu "AT91SAM3/4 USART Configuration"
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comment "AT91SAM3/4 USART Configuration"
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config USART0_ISUART
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bool "USART0 is a UART"
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@ -389,9 +388,7 @@ config USART3_ISUART
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depends on SAM34_USART3
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select ARCH_HAVE_USART2
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endmenu
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menu "AT91SAM3/4 GPIO Interrupt Configuration"
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comment "AT91SAM3/4 GPIO Interrupt Configuration"
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config GPIOA_IRQ
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bool "GPIOA interrupts"
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@ -405,4 +402,28 @@ config GPIOC_IRQ
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bool "GPIOC interrupts"
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default n
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endmenu
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if SAM34_WDT
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comment "AT91SAM3/4 Watchdog Configuration"|
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config WDT_ENABLED_ON_RESET
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bool "Enabled on reset"
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default n
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---help---
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The WDT can be enabled at reset. This is controlled by the WDTAUTO
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fuse. The WDT will be set in basic mode, RCSYS is set as source for
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CLK_CNT, and PSEL will be set to a value giving Tpsel above 100 ms
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(SAM4L)
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This setting informs that start-up logic that the watchdog is
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enabled.
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config WDT_DISABLE_ON_RESET
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bool "Disable on reset"
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default n
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depends on WDT_ENABLED_ON_RESET
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---help---
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If the WDT can be enabled at reset then this setting may be used to
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configure and disable the watchdog timer very early in the boot
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sequence.
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endif
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@ -1,5 +1,5 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_wdt.h
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* arch/arm/src/sam34/chip/sam3u_wdt.h
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -33,8 +33,8 @@
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H
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/****************************************************************************************
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* Included Files
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@ -93,4 +93,4 @@
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H */
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_WDT_H */
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@ -116,9 +116,9 @@
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#define BPM_PMCON_SLEEP_SHIFT (12) /* Bits 12-13: SLEEP mode Configuration */
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#define BPM_PMCON_SLEEP_MASK (3 << BPM_PMCON_SLEEP_SHIFT)
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# define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */
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# define BPM_PMCON_SLEEP_SLEEP0 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */
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# define BPM_PMCON_SLEEP_SLEEP0 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */
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# define BPM_PMCON_SLEEP_SLEEP0 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */
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# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */
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# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */
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# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */
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#define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */
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#define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */
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@ -48,7 +48,7 @@
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Alternate Pin Functions.
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/* Alternate Pin Functions.
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*
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* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
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* Drivers, however, will use the pin selection without the numeric suffix.
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@ -288,7 +288,7 @@
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# define SCIF_DFLL0STEP_FSTEP(n) ((n) << SCIF_DFLL0STEP_FSTEP_SHIFT)
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#define SCIF_DFLL0STEP_CSTEP_SHIFT (16) /* Bits 16-20: Coarse Maximum Step */
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#define SCIF_DFLL0STEP_CSTEP_MASK (31 << SCIF_DFLL0STEP_CSTEP_SHIFT)
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# define SCIF_DFLL0STEP_CSTEP(4) ((v) << SCIF_DFLL0STEP_CSTEP_SHIFT)
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# define SCIF_DFLL0STEP_CSTEP(n) ((n) << SCIF_DFLL0STEP_CSTEP_SHIFT)
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/* DFLL0 Spread Spectrum Generator Control Register */
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@ -391,6 +391,13 @@
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# define SCIF_GCCTRL_OSCSEL_PBCCLK (11 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus C clock */
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# define SCIF_GCCTRL_OSCSEL_PBDCLK (12 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Peripheral Bus D clock */
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# define SCIF_GCCTRL_OSCSEL_RC32K (13 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Output from 32kHz RCOSC */
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# define SCIF_GCCTRL_OSCSEL_1K (15 << SCIF_GCCTRL_OSCSEL_SHIFT) /* 1 kHz output from OSC32K */
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# define SCIF_GCCTRL_OSCSEL_PLL0 (16 << SCIF_GCCTRL_OSCSEL_SHIFT) /* PLL0 */
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# define SCIF_GCCTRL_OSCSEL_HRPCLK (17 << SCIF_GCCTRL_OSCSEL_SHIFT) /* High resolution prescaler */
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# define SCIF_GCCTRL_OSCSEL_FPCLK (18 << SCIF_GCCTRL_OSCSEL_SHIFT) /* Fractional prescaler */
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# define SCIF_GCCTRL_OSCSEL_GCLKIN0 (19 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN0 */
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# define SCIF_GCCTRL_OSCSEL_GCLKIN1 (20 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN1 */
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# define SCIF_GCCTRL_OSCSEL_GCLK11 (21 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLK11 */
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#define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */
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#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT)
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# define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT)
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137
arch/arm/src/sam34/chip/sam4l_wdt.h
Normal file
137
arch/arm/src/sam34/chip/sam4l_wdt.h
Normal file
@ -0,0 +1,137 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam4l_wdt.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* WDT register offsets ****************************************************************/
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#define SAM_WDT_CTRL_OFFSET 0x0000 /* Control Register */
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#define SAM_WDT_CLR_OFFSET 0x0004 /* Clear Register */
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#define SAM_WDT_SR_OFFSET 0x0008 /* Status Register */
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#define SAM_WDT_IER_OFFSET 0x000c /* Interrupt Enable Register */
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#define SAM_WDT_IDR_OFFSET 0x0010 /* Interrupt Disable Register */
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#define SAM_WDT_IMR_OFFSET 0x0014 /* Interrupt Mask Register */
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#define SAM_WDT_ISR_OFFSET 0x0018 /* Interrupt Status Register */
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#define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */
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#define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */
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/* WDT register adresses ***************************************************************/
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#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET)
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#define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET)
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#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET)
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#define SAM_WDT_IER (SAM_WDT_BASE+SAM_WDT_IER_OFFSET)
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#define SAM_WDT_IDR (SAM_WDT_BASE+SAM_WDT_IDR_OFFSET)
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#define SAM_WDT_IMR (SAM_WDT_BASE+SAM_WDT_IMR_OFFSET)
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#define SAM_WDT_ISR (SAM_WDT_BASE+SAM_WDT_ISR_OFFSET)
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#define SAM_WDT_ICR (SAM_WDT_BASE+SAM_WDT_ICR_OFFSET)
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#define SAM_WDT_VERSION (SAM_WDT_BASE+SAM_WDT_VERSION_OFFSET)
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/* WDT register bit definitions ********************************************************/
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/* Control Register */
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#define WDT_CTRL_EN (1 << 0) /* Bit 0: WDT Enable */
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#define WDT_CTRL_DAR (1 << 1) /* Bit 1: WDT Disable After Reset */
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#define WDT_CTRL_MODE (1 << 2) /* Bit 2: WDT Mode */
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#define WDT_CTRL_SFV (1 << 3) /* Bit 3: WDT Control Register Store Final Value */
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#define WDT_CTRL_IM (1 << 4) /* Bit 4: Interrupt Mode */
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#define WDT_CTRL_FCD (1 << 7) /* Bit 7: Flash Calibration Done */
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#define WDT_CTRL_PSEL_SHIFT (8) /* Bits 8-12: Time Out Prescale Select */
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#define WDT_CTRL_PSEL_MASK (31 << WDT_CTRL_PSEL_SHIFT)
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#define WDT_CTRL_CEN (1 << 16) /* Bit 16: Clock Enable */
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#define WDT_CTRL_CSSEL (1 << 17) /* Bit 17: Clock Source Select */
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#define WDT_CTRL_TBAN_SHIFT (18) /* Bits 18-22: Time Ban Prescale Select */
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#define WDT_CTRL_TBAN_MASK (31 << WDT_CTRL_TBAN_SHIFT)
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#define WDT_CTRL_KEY_SHIFT (24) /* Bits 24-31: Key */
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#define WDT_CTRL_KEY_MASK (0xff << WDT_CTRL_KEY_SHIFT)
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# define WDT_CTRL_KEY_FIRST (0x55 << WDT_CTRL_KEY_SHIFT)
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# define WDT_CTRL_KEY_SECOND (0xaa << WDT_CTRL_KEY_SHIFT)
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/* Clear Register */
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#define WDT_CLR_WDTCLR (1 << 0) /* Bit 0: Watchdog Clear */
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#define WDT_CLR_KEY_SHIFT (24) /* Bits 24-31: Key */
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#define WDT_CLR_KEY_MASK (0xff << WDT_CLR_KEY_SHIFT)
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# define WDT_CLR_KEY_FIRST (0x55 << WDT_CLR_KEY_SHIFT)
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# define WDT_CLR_KEY_SECOND (0xaa << WDT_CLR_KEY_SHIFT)
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/* Status Register */
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#define WDT_SR_WINDOW (1 << 0) /* Bit 0: Within Window */
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#define WDT_SR_CLEARED (1 << 1) /* Bit 1: WDT Counter Cleared */
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/* Interrupt Enable Register */
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/* Interrupt Disable Register */
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/* Interrupt Mask Register */
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/* Interrupt Status Register */
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/* Interrupt Clear Register */
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#define WDT_WINT (1 << 2) /* Bit 2: WINT */
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/* Version Register */
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#define WDT_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
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#define WDT_VERSION_MASK (0xfff << WDT_VERSION_VERSION_SHIFT)
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#define WDT_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
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#define WDT_VARIANT_MASK (15 << WDT_VARIANT_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H */
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@ -45,6 +45,8 @@
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# include "chip/sam3u_pinmap.h"
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#elif defined(CONFIG_ARCH_CHIP_SAM4L)
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# include "chip/sam4l_pinmap.h"
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#else
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# error Unrecognized SAM architecture
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#endif
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@ -1,71 +0,0 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_pio.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# include "chip/sam3u_vectors.h"
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#elif defined(CONFIG_ARCH_CHIP_SAM4S)
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# include "chip/sam4s_vectors.h"
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#else
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# error Unrecognized SAM architecture
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#endif
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H */
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@ -51,7 +51,7 @@
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#include "sam_clockconfig.h"
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#include "chip/sam_pmc.h"
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#include "chip/sam3u_eefc.h"
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#include "chip/sam_wdt.h"
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#include "chip/sam3u_wdt.h"
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#include "chip/sam3u_supc.h"
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#include "chip/sam_matrix.h"
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@ -52,7 +52,7 @@
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#include "chip.h"
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#include "sam_gpio.h"
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#include "chip/sam_pio.h"
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#include "chip/sam3u_pio.h"
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/****************************************************************************
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* Definitions
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@ -41,6 +41,9 @@
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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@ -53,7 +56,7 @@
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#include "chip/sam4l_bscif.h"
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#include "chip/sam4l_flashcalw.h"
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#include "sam_periphclks.h"
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#include "sam4l_periphclks.h"
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#include "sam_clockconfig.h"
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/****************************************************************************
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@ -284,6 +287,7 @@
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#ifdef BOARD_PLL0_SOURCE_GCLK9
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# define NEED_GLCK9 1
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#endif
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#ifdef NEED_GLCK9
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# if defined(BOARD_GLCK9_SOURCE_RCSYS)
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@ -410,8 +414,12 @@
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# define SAM_PLL0_OPTIONS 0
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# endif
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# endif
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#endif
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/* DPLL0 reference clock */
|
||||
/* DFLL0 */
|
||||
|
||||
#ifdef BOARD_SYSCLK_SOURCE_DFLL0
|
||||
/* DFLL0 reference clock */
|
||||
|
||||
# if defined(BOARD_DFLL0_SOURCE_RCSYS)
|
||||
# define SAM_DFLLO_REFCLK SCIF_GCCTRL_OSCSEL_RCSYS
|
||||
@ -529,7 +537,7 @@ static inline void sam_enableosc32(void)
|
||||
|
||||
/* Wait for OSC32 to be ready */
|
||||
|
||||
while (getreg32(SAM_BSCIF_PCLKSR) & BSCIF_INT_OSC32RDY) == 0);
|
||||
while ((getreg32(SAM_BSCIF_PCLKSR) & BSCIF_INT_OSC32RDY) == 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -752,7 +760,7 @@ static inline void sam_enabledfll0(void)
|
||||
* and divider.
|
||||
*/
|
||||
|
||||
putreg(0, SAM_SCIF_GCCTRL0);
|
||||
putreg32(0, SAM_SCIF_GCCTRL0);
|
||||
|
||||
/* Set the generic clock 0 source */
|
||||
|
||||
@ -776,11 +784,11 @@ static inline void sam_enabledfll0(void)
|
||||
/* Sync before reading a dfll conf register */
|
||||
|
||||
putreg32(SCIF_DFLL0SYNC_SYNC, SAM_SCIF_DFLL0SYNC);
|
||||
while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0);
|
||||
while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_DFLL0RDY) == 0);
|
||||
|
||||
/* Select Closed Loop Mode */
|
||||
|
||||
conf = getreg(SAM_SCIF_DFLL0CONF);
|
||||
conf = getreg32(SAM_SCIF_DFLL0CONF);
|
||||
conf &= ~SCIF_DFLL0CONF_RANGE_MASK;
|
||||
conf |= SCIF_DFLL0CONF_MODE;
|
||||
|
||||
@ -794,7 +802,7 @@ static inline void sam_enabledfll0(void)
|
||||
conf |= SCIF_DFLL0CONF_RANGE1;
|
||||
#else
|
||||
conf |= SCIF_DFLL0CONF_RANGE0;
|
||||
#ednif
|
||||
#endif
|
||||
|
||||
/* Enable the reference generic clock 0 */
|
||||
|
||||
@ -817,7 +825,7 @@ static inline void sam_enabledfll0(void)
|
||||
* too high, DFLL0 may fail to lock.
|
||||
*/
|
||||
|
||||
sam_dfll0_putreg32((SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4),
|
||||
sam_dfll0_putreg32(SCIF_DFLL0STEP_CSTEP(4) | SCIF_DFLL0STEP_FSTEP(4),
|
||||
SAM_SCIF_DFLL0STEP,
|
||||
SAM_SCIF_DFLL0STEP_OFFSET);
|
||||
|
||||
@ -1056,7 +1064,7 @@ static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwk
|
||||
{
|
||||
/* Set one wait state */
|
||||
|
||||
waistate = true;
|
||||
waitstate = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1073,7 +1081,7 @@ static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwk
|
||||
{
|
||||
/* Set one wait state */
|
||||
|
||||
waistate = true;
|
||||
waitstate = true;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1117,7 +1125,7 @@ static inline void sam_mainclk(uint32_t mcsel)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static __ramfunc__ void sam_instantiatepsm(Bpm *bpm, uint32_t regval)
|
||||
static __ramfunc__ void sam_instantiatepsm(uint32_t regval)
|
||||
{
|
||||
/* Set the BMP PCOM register (containing the new power scaling mode) */
|
||||
|
||||
@ -1144,7 +1152,7 @@ static inline void sam_setpsm(uint32_t psm)
|
||||
|
||||
/* Then call the RAMFUNC sam_setpsm() to set the new power scaling mode */
|
||||
|
||||
sam_instantiatepsm(bpm, regval);
|
||||
sam_instantiatepsm(regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1286,7 +1294,7 @@ void sam_clockconfig(void)
|
||||
sam_enableosc32();
|
||||
#endif
|
||||
|
||||
#ifdef NEED_OSC32K
|
||||
#ifdef NEED_RC80M
|
||||
/* Enable the 32KHz oscillator using the settings in board.h */
|
||||
|
||||
sam_enablerc80m();
|
||||
@ -1407,7 +1415,9 @@ void sam_clockconfig(void)
|
||||
|
||||
sam_init_periphclks();
|
||||
|
||||
/* Configure clocking to the USB controller */
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
void sam_usbclock();
|
||||
sam_usbc_enableclk();
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -54,6 +54,21 @@
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* USBC source clock selection */
|
||||
|
||||
#ifdef CONFIG_SAM34_USBC
|
||||
# if defined(BOARD_USBC_SRC_OSC0)
|
||||
# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_OSC0
|
||||
# elif defined(BOARD_USBC_SRC_PLL0)
|
||||
# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_PLL0
|
||||
# elif defined(BOARD_USBC_SRC_DFLL)
|
||||
# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_DFLL0
|
||||
# elif defined(BOARD_USBC_SRC_GCLKIN0)
|
||||
# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_GCLKIN0
|
||||
# else
|
||||
# error No USBC GCLK7 source clock defined
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
@ -115,7 +130,7 @@ static inline void sam_init_hsbmask(void)
|
||||
/* Select the non-optional peripherals */
|
||||
|
||||
uint32_t mask = (PM_HSBMASK_FLASHCALW | PM_HSBMASK_APBB |
|
||||
PM_HSBMASK_APBC | PM_HSBMASK_APBD)
|
||||
PM_HSBMASK_APBC | PM_HSBMASK_APBD);
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
@ -191,19 +206,19 @@ static inline void sam_init_pbamask(void)
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART0
|
||||
mask |= PM_PBAMASK_USART0; /* USART0 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
divmask |= PM_PBADIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART1
|
||||
mask |= PM_PBAMASK_USART1; /* USART1 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
divmask |= PM_PBADIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART2
|
||||
mask |= PM_PBAMASK_USART2; /* USART2 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
divmask |= PM_PBADIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART3
|
||||
mask |= PM_PBAMASK_USART3; /* USART3 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
divmask |= PM_PBADIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_ADCIFE
|
||||
mask |= PM_PBAMASK_ADCIFE; /* ADCIFE */
|
||||
@ -579,3 +594,86 @@ void sam_pbb_disableperipheral(uint32_t bitset)
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_usbc_enableclk
|
||||
*
|
||||
* Description:
|
||||
* Enable clocking for the USBC using settings from the board.h header files.
|
||||
*
|
||||
* "The USBC has two bus clocks connected: One High Speed Bus clock
|
||||
* (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks
|
||||
* are generated by the Power Manager. Both clocks are enabled at reset
|
||||
* and can be disabled by the Power Manager. It is recommended to disable
|
||||
* the USBC before disabling the clocks, to avoid freezing the USBC in
|
||||
* an undefined state.
|
||||
*
|
||||
* "To follow the usb data rate at 12Mbit/s in full-speed mode, the
|
||||
* CLK_USBC_AHB clock should be at minimum 12MHz.
|
||||
*
|
||||
* "The 48MHz USB clock is generated by a dedicated generic clock from
|
||||
* the SCIF module. Before using the USB, the user must ensure that the
|
||||
* USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module."
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_USBC
|
||||
void sam_usbc_enableclk(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable USBC clocking (possibly along with the PBB peripheral bridge) */
|
||||
|
||||
flags = irqsave();
|
||||
sam_hsb_enableperipheral(PM_HSBMASK_USBC);
|
||||
sam_pbb_enableperipheral(PM_PBBMASK_USBC);
|
||||
|
||||
/* Reset generic clock 7 */
|
||||
|
||||
putreg32(0, SAM_SCIF_GCCTRL7);
|
||||
|
||||
/* Set the generic clock source */
|
||||
|
||||
regval = getreg32(SAM_SCIF_GCCTRL7);
|
||||
regval &= ~SCIF_GCCTRL_OSCSEL_MASK;
|
||||
regval |= SAM_USBC_GCLK_SOURCE;
|
||||
putreg32(regval, SAM_SCIF_GCCTRL7);
|
||||
|
||||
/* Set the generic clock divider */
|
||||
|
||||
regval = getreg32(SAM_SCIF_GCCTRL7);
|
||||
regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK);
|
||||
|
||||
#if BOARD_USBC_GCLK_DIV > 1
|
||||
regval |= SCIF_GCCTRL_DIVEN;
|
||||
regval |= SCIF_GCCTRL_DIV(((divider + 1) / 2) - 1);
|
||||
#endif
|
||||
|
||||
putreg32(regval, SAM_SCIF_GCCTRL7);
|
||||
|
||||
/* Enable the generic clock */
|
||||
|
||||
regval = getreg32(SAM_SCIF_GCCTRL7);
|
||||
regval |= SCIF_GCCTRL_CEN;
|
||||
putreg32(regval, SAM_SCIF_GCCTRL7);
|
||||
irqrestore(flags);
|
||||
}
|
||||
#endif /* CONFIG_SAM34_USBC */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_usbc_disableclk
|
||||
*
|
||||
* Description:
|
||||
* Disable clocking to the USBC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_USBC
|
||||
void sam_usbc_disableclk(void)
|
||||
{
|
||||
putreg32(0, SAM_SCIF_GCCTRL7);
|
||||
sam_pbb_enableperipheral(PM_PBBMASK_USBC);
|
||||
sam_hsb_enableperipheral(PM_HSBMASK_USBC);
|
||||
}
|
||||
#endif /* CONFIG_SAM34_USBC */
|
||||
|
||||
@ -151,12 +151,6 @@
|
||||
sam_pbb_enableperipheral(PM_PBBMASK_CRCCU); \
|
||||
} while (0)
|
||||
|
||||
#define sam_usbc_enableclk() \
|
||||
do { \
|
||||
sam_hsb_enableperipheral(PM_HSBMASK_USBC); \
|
||||
sam_pbb_enableperipheral(PM_PBBMASK_USBC); \
|
||||
} while (0)
|
||||
|
||||
#define sam_pevc_enableclk() sam_pbb_enableperipheral(PM_PBBMASK_PEVC)
|
||||
#define sam_pm_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_PM)
|
||||
#define sam_chipid_enableclk() sam_pbc_enableperipheral(PM_PBCMASK_CHIPID)
|
||||
@ -218,12 +212,6 @@
|
||||
sam_pbb_disableperipheral(PM_PBBMASK_CRCCU); \
|
||||
} while (0)
|
||||
|
||||
#define sam_usbc_disableclk() \
|
||||
do { \
|
||||
sam_hsb_disableperipheral(PM_HSBMASK_USBC); \
|
||||
sam_pbb_disableperipheral(PM_PBBMASK_USBC); \
|
||||
} while (0)
|
||||
|
||||
#define sam_pevc_disableclk() sam_pbb_disableperipheral(PM_PBBMASK_PEVC)
|
||||
#define sam_pm_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_PM)
|
||||
#define sam_chipid_disableclk() sam_pbc_disableperipheral(PM_PBCMASK_CHIPID)
|
||||
@ -336,6 +324,44 @@ void sam_pbb_enableperipheral(uint32_t bitset);
|
||||
|
||||
void sam_pbb_disableperipheral(uint32_t bitset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_usbc_enableclk
|
||||
*
|
||||
* Description:
|
||||
* Enable clocking for the USBC using settings from the board.h header files.
|
||||
*
|
||||
* "The USBC has two bus clocks connected: One High Speed Bus clock
|
||||
* (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks
|
||||
* are generated by the Power Manager. Both clocks are enabled at reset
|
||||
* and can be disabled by the Power Manager. It is recommended to disable
|
||||
* the USBC before disabling the clocks, to avoid freezing the USBC in
|
||||
* an undefined state.
|
||||
*
|
||||
* "To follow the usb data rate at 12Mbit/s in full-speed mode, the
|
||||
* CLK_USBC_AHB clock should be at minimum 12MHz.
|
||||
*
|
||||
* "The 48MHz USB clock is generated by a dedicated generic clock from
|
||||
* the SCIF module. Before using the USB, the user must ensure that the
|
||||
* USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module."
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_USBC
|
||||
void sam_usbc_enableclk(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_usbc_disableclk
|
||||
*
|
||||
* Description:
|
||||
* Disable clocking to the USBC.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_USBC
|
||||
void sam_usbc_disableclk(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
@ -54,7 +54,7 @@
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "sam_gpio.h"
|
||||
#include "chip/sam_pio.h"
|
||||
#include "chip/sam3u_pio.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
|
||||
@ -54,8 +54,11 @@
|
||||
#include "sam_userspace.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Definitions
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
#if defined(CONFIG_WDT_ENABLED_ON_RESET) && defined(CONFIG_WDT_DISABLE_ON_RESET)
|
||||
# define NEED_WDT_DISABLE
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
@ -120,6 +123,11 @@ void __start(void)
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
#ifdef NEED_WDT_DISABLE
|
||||
/* Disable the watchdog timer */
|
||||
# warning Missing logic
|
||||
#endif
|
||||
|
||||
/* Copy any necessary code sections from FLASH to RAM. The correct
|
||||
* destination in SRAM is geive by _sramfuncs and _eramfuncs. The
|
||||
* temporary location is in flash after the data initalization code
|
||||
|
||||
Loading…
Reference in New Issue
Block a user