diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
index 0bc6b93c5e..fcf5652418 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
+++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
@@ -132,79 +132,6 @@
 #define STM32_HRTIM_CMN_BDTEUPR_OFFSET  0x006C /* HRTIM Timer E Update Register */
 #define STM32_HRTIM_CMN_BDMADR_OFFSET   0x0070 /* HRTIM DMA Data Register */
 
-/* Register Addresses *******************************************************************************/
-
-/* HRTIM1 Timer A */
-/* remove ? */
-
-#define STM32_HRTIM1_TIMERA_CR          (STM32_HRTIM_TIM_CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_ISR         (STM32_HRTIM_TIM_ISR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_ICR         (STM32_HRTIM_TIM_ICR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_DIER        (STM32_HRTIM_TIM_DIER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CNTR        (STM32_HRTIM_TIM_CNTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_PER         (STM32_HRTIM_TIM_PER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_REP         (STM32_HRTIM_TIM_REP_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CMP1R       (STM32_HRTIM_TIM_CMP1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CMP1CR      (STM32_HRTIM_TIM_CMP1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CMP2R       (STM32_HRTIM_TIM_CMP2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CMP3R       (STM32_HRTIM_TIM_CMP3R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CMP4R       (STM32_HRTIM_TIM_CMP4R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CPT1R       (STM32_HRTIM_TIM_CMPT1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CPT2R       (STM32_HRTIM_TIM_CMPT2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_DTR         (STM32_HRTIM_TIM_DTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_SET1R       (STM32_HRTIM_TIM_SET1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_RST1R       (STM32_HRTIM_TIM_RST1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_SET2R       (STM32_HRTIM_TIM_SET2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_RST2R       (STM32_HRTIM_TIM_RST2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_EEFR1       (STM32_HRTIM_TIM_EEFR1_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_EEFR2       (STM32_HRTIM_TIM_EEFR2_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_RSTR        (STM32_HRTIM_TIM_RSTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CHPR        (STM32_HRTIM_TIM_CHPR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CPT1CR      (STM32_HRTIM_TIM_CPT1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_CPT2CR      (STM32_HRTIM_TIM_CPT2CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_OUTR        (STM32_HRTIM_TIM_OUTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-#define STM32_HRTIM1_TIMERA_FLTR        (STM32_HRTIM_TIM_FLTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
-
-/* HRTIM1 Timer B */
-
-/* HRTIM1 Timer C */
-
-/* HRTIM1 Timer D */
-
-/* HRTIM1 Timer E */
-
-/* HRTIM1 Common Registers  */
-
-#define STM32_HRTIM_CMN_CR1             (STM32_HRTIM_CMN_CR1_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_CR2             (STM32_HRTIM_CMN_CR2_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_ISR             (STM32_HRTIM_CMN_ISR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_ICR             (STM32_HRTIM_CMN_ICR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_IER             (STM32_HRTIM_CMN_IER_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_OENR            (STM32_HRTIM_CMN_OENR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_DISR            (STM32_HRTIM_CMN_DISR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_ODSR            (STM32_HRTIM_CMN_ODSR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BMCR            (STM32_HRTIM_CMN_BMCR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BMTGR           (STM32_HRTIM_CMN_BMTGR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BMCMPR          (STM32_HRTIM_CMN_MBCMPR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BMPER           (STM32_HRTIM_CMN_BMPER_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_EECR1           (STM32_HRTIM_CMN_EECR1_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_EECR2           (STM32_HRTIM_CMN_EECR2_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_EECR3           (STM32_HRTIM_CMN_EECR3_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_ADC1R           (STM32_HRTIM_CMN_ADC1R_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_ADC2R           (STM32_HRTIM_CMN_ADC2R_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_ADC3R           (STM32_HRTIM_CMN_ADC3R_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_ADC4R           (STM32_HRTIM_CMN_ADC4R_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_DLLCR           (STM32_HRTIM_CMN_DLLCR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_FLTINR1         (STM32_HRTIM_CMN_FTLINR1_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_FLTINR2         (STM32_HRTIM_CMN_FLTINR2_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BDMUPDR         (STM32_HRTIM_CMN_BDMUPDR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BDTAUPR         (STM32_HRTIM_CMN_BDTAUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BDTBUPR         (STM32_HRTIM_CMN_BDTBUR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BDTCUPR         (STM32_HRTIM_CMN_BDTCUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BDTDUPR         (STM32_HRTIM_CMN_BDTDUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BDTEUPR         (STM32_HRTIM_CMN_BDTEUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
-#define STM32_HRTIM_CMN_BDMADR          (STM32_HRTIM_CMN_BDMADR_OFFSET+STM32_HRTIM1_CMN_BASE)
-
 /* Register Bitfield Definitions ****************************************************/
 
 /* Control Register Bits Common to Master Timer and Timer A-E */