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arch/arm/src/stm32h7/stm32_i2c.c: Fix syslog formats

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YAMAMOTO Takashi 2020-11-21 07:45:16 +09:00 committed by Xiang Xiao
parent 9d293a88f9
commit c2b06fe219
1 changed files with 36 additions and 25 deletions
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61
arch/arm/src/stm32h7/stm32_i2c.c
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@ -199,6 +199,7 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <sys/types.h> #include <sys/types.h>
#include <inttypes.h>
#include <stdio.h> #include <stdio.h>
#include <stdlib.h> #include <stdlib.h>
#include <stdint.h> #include <stdint.h>
@ -1026,7 +1027,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
* still pending. * still pending.
*/ */
i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr); i2cinfo("Timeout with CR: %04" PRIx32 " SR: %04" PRIx32 "\n", cr, sr);
} }
/************************************************************************************ /************************************************************************************
@ -1532,7 +1533,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
i2cinfo("ENTER: status = 0x%08x\n", status); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status);
/* Update private version of the state assuming a good state */ /* Update private version of the state assuming a good state */
@ -1580,15 +1581,17 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
{ {
/* NACK received on first (address) byte: address is invalid */ /* NACK received on first (address) byte: address is invalid */
i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n", i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i "
priv->dcnt, priv->msgc, status); "status=0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status);
stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
} }
else else
{ {
/* NACK received on regular byte */ /* NACK received on regular byte */
i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n", i2cinfo("NACK: NACK received: dcnt=%i msgc=%i "
"status=0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
} }
@ -1642,7 +1645,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
/* TXIS interrupt occurred, address valid, ready to transmit */ /* TXIS interrupt occurred, address valid, ready to transmit */
stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0);
i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
/* The first event after the address byte is sent will be either TXIS /* The first event after the address byte is sent will be either TXIS
@ -1699,8 +1702,9 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
{ {
/* Unsupported state */ /* Unsupported state */
i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n", i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, "
priv->dcnt, status); "status 0x%08" PRIx32 "\n",
priv->dcnt, status);
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
/* Indicate the bad state, so that on termination HW will be reset */ /* Indicate the bad state, so that on termination HW will be reset */
@ -1708,7 +1712,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->status |= I2C_INT_BAD_STATE; priv->status |= I2C_INT_BAD_STATE;
} }
i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
} }
@ -1749,7 +1753,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
*/ */
stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); stm32_i2c_traceevent(priv, I2CEVENT_READ, 0);
i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
/* If more bytes in the current message */ /* If more bytes in the current message */
@ -1789,7 +1793,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, "
"status 0x%08" PRIx32 "\n",
priv->dcnt, status); priv->dcnt, status);
/* Set signals that will terminate ISR and wake waiting thread */ /* Set signals that will terminate ISR and wake waiting thread */
@ -1799,7 +1804,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->msgc = 0; priv->msgc = 0;
} }
i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
} }
@ -1834,7 +1839,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
else if ((status & I2C_ISR_TC) != 0) else if ((status & I2C_ISR_TC) != 0)
{ {
i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
/* Prior message has been sent successfully. Or there could have /* Prior message has been sent successfully. Or there could have
@ -1891,7 +1896,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->msgc = 0; priv->msgc = 0;
} }
i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
} }
@ -1932,8 +1937,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
else if ((status & I2C_ISR_TCR) != 0) else if ((status & I2C_ISR_TCR) != 0)
{ {
i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
/* If no more bytes in the current message to transfer */ /* If no more bytes in the current message to transfer */
@ -2018,8 +2023,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
} }
i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n", i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n",
priv->dcnt, priv->msgc, status); priv->dcnt, priv->msgc, status);
} }
} }
@ -2032,7 +2037,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
else if (priv->dcnt == -1 && priv->msgc == 0) else if (priv->dcnt == -1 && priv->msgc == 0)
{ {
status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n",
status);
stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0);
} }
@ -2055,7 +2061,8 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n",
status);
/* set condition to terminate ISR and wake waiting thread */ /* set condition to terminate ISR and wake waiting thread */
@ -2129,7 +2136,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
} }
status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
i2cinfo("EXIT: status = 0x%08x\n", status); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status);
return OK; return OK;
} }
@ -2344,19 +2351,23 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev,
/* Connection timed out */ /* Connection timed out */
errval = ETIMEDOUT; errval = ETIMEDOUT;
i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", i2cerr("ERROR: Waitdone timed out CR1: 0x%08" PRIx32
" CR2: 0x%08" PRIx32
" status: 0x%08" PRIx32 "\n",
cr1, cr2, status); cr1, cr2, status);
} }
else else
{ {
i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", i2cinfo("Waitdone success: CR1: 0x%08" PRIx32
cr1, cr2, status); " CR2: 0x%08" PRIx32
" status: 0x%08" PRIx32 "\n",
cr1, cr2, status);
} }
UNUSED(cr1); UNUSED(cr1);
UNUSED(cr2); UNUSED(cr2);
i2cinfo("priv->status: 0x%08x\n", priv->status); i2cinfo("priv->status: 0x%08" PRIx32 "\n", priv->status);
/* Check for error status conditions */ /* Check for error status conditions */