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RISC-V: mtimer register via SBI when S-mode is in use

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Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
This commit is contained in:
Ville Juven 2022-04-14 09:22:26 +03:00 committed by Xiang Xiao
parent 3d6ab5c804
commit c2b69cc2c9
1 changed files with 15 additions and 0 deletions
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15
arch/risc-v/src/common/riscv_mtimer.c
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@ -80,6 +80,7 @@ static const struct oneshot_operations_s g_riscv_mtimer_ops =
* Private Functions
****************************************************************************/
#ifndef CONFIG_ARCH_USE_S_MODE
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
{
#ifdef CONFIG_ARCH_RV64
@ -114,6 +115,20 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
__DMB();
}
#else
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
{
UNUSED(priv);
return riscv_sbi_get_time();
}
static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
uint64_t value)
{
UNUSED(priv);
riscv_sbi_set_timer(value);
}
#endif
/****************************************************************************
* Name: riscv_mtimer_max_delay