From c2b69cc2c9a0a26da8d2d26e5d41f02cb6715e76 Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Thu, 14 Apr 2022 09:22:26 +0300 Subject: [PATCH] RISC-V: mtimer register via SBI when S-mode is in use Cannot access the memory mapped registers directly when the kernel runs in S-mode, must forward the access to SBI. --- arch/risc-v/src/common/riscv_mtimer.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/risc-v/src/common/riscv_mtimer.c b/arch/risc-v/src/common/riscv_mtimer.c index 27ce9e4e41..c78919763e 100644 --- a/arch/risc-v/src/common/riscv_mtimer.c +++ b/arch/risc-v/src/common/riscv_mtimer.c @@ -80,6 +80,7 @@ static const struct oneshot_operations_s g_riscv_mtimer_ops = * Private Functions ****************************************************************************/ +#ifndef CONFIG_ARCH_USE_S_MODE static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv) { #ifdef CONFIG_ARCH_RV64 @@ -114,6 +115,20 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv, __DMB(); } +#else +static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv) +{ + UNUSED(priv); + return riscv_sbi_get_time(); +} + +static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv, + uint64_t value) +{ + UNUSED(priv); + riscv_sbi_set_timer(value); +} +#endif /**************************************************************************** * Name: riscv_mtimer_max_delay