SAMA5D SSC: Needs to account for data offset in audio buffer.
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@ -1182,7 +1182,8 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
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/* No data received yet */
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apb->nbytes = 0;
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apb->nbytes = 0;
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apb->curbyte = 0;
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/* Physical address of the SSC RHR register and of the buffer location
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* in RAM.
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@ -1551,9 +1552,11 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
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{
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struct sam_buffer_s *bfcontainer;
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struct ap_buffer_s *apb;
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uintptr_t samp;
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uintptr_t paddr;
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uintptr_t maddr;
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uint32_t timeout;
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apb_samp_t nbytes;
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bool notimeout;
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int ret;
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@ -1592,17 +1595,21 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
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apb = bfcontainer->apb;
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DEBUGASSERT(((uintptr_t)apb->samp & 3) == 0);
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/* Get the transfer information, accounting for any data offset */
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samp = (uintptr_t)&apb->samp[apb->curbyte];
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nbytes = apb->nbytes - apb->curbyte;
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/* Physical address of the SSC THR register and of the buffer location
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* in
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* RAM.
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* in RAM.
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*/
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paddr = ssc_physregaddr(priv, SAM_SSC_THR_OFFSET);
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maddr = sam_physramaddr((uintptr_t)apb->samp);
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maddr = sam_physramaddr(samp);
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/* Configure the TX DMA */
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sam_dmatxsetup(priv->tx.dma, paddr, maddr, apb->nbytes);
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sam_dmatxsetup(priv->tx.dma, paddr, maddr, nbytes);
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/* Increment the DMA timeout */
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@ -1623,9 +1630,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
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* before starting the DMA.
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*/
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arch_clean_dcache((uintptr_t)apb->samp,
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(uintptr_t)apb->samp + apb->nbytes);
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arch_clean_dcache(samp, samp + nbytes);
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}
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#if 1 /* REVISIT: Chained TX transfers */
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while (0);
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