Fix error in last update to a README
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@ -752,7 +752,7 @@ Selecting the GMAC peripheral
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SAMV71 Versions
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SAMV71 Versions
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WARNING: "The newer SAMV71 have 6 GMAC queues, not 5. All queues must be
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WARNING: The newer SAMV71 have 6 GMAC queues, not 3. All queues must be
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configured for the GMAC to work correctly, even the queues that you are not
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configured for the GMAC to work correctly, even the queues that you are not
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using (you can just configure these queues with a very small ring buffer.)
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using (you can just configure these queues with a very small ring buffer.)
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@ -760,7 +760,7 @@ The older uses the Cortex-M7 core r0p1 and the newer r1p1 revisions. The
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SAMV71 revisions are called "rev A" (or sometimes "MRLA") and "rev B"
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SAMV71 revisions are called "rev A" (or sometimes "MRLA") and "rev B"
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("MRLB"). There should be a small "A" or "B" on the chip package just below
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("MRLB"). There should be a small "A" or "B" on the chip package just below
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the reference and you can also differentiate them at runtime with the
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the reference and you can also differentiate them at runtime with the
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VERSION field in the CHIPID CIDR register."
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VERSION field in the CHIPID CIDR register.
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Cache-Related Issues
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Cache-Related Issues
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