SAMA5D2: Update boot logic, AXIMX, SFR, and WDT register definition files for SAMA5D2
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Gregory Nutt
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76ab22debf
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/sama5/chip/sam_sfr.h
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*
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -58,20 +58,33 @@
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/* 0x002c: Reserved */
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#define SAM_SFR_UTMICKTRIM_OFFSET 0x0030 /* UTMI Clock Trimming Register */
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SAM_SFR_UTMIHSTRIM_OFFSET 0x0034 /* UTMI High Speed Trimming Register */
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# define SAM_SFR_UTMIFSTRIM_OFFSET 0x0038 /* UTMI Full Speed Trimming Register */
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# define SAM_SFR_UTMISWAP_OFFSET 0x003c /* UTMI DP/DM Pin Swapping Register */
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#endif
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#define SAM_SFR_EBICFG_OFFSET 0x0040 /* EBI Configuration Register */
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/* 0x0044-0x3ffc: Reserved */
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#ifdef ATSAMA5D4
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#ifdef ATSAMA5D2
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# define SAM_SFR_ANACFG_OFFSET 0x0044 /* Analog Configuration Register */
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# define SAM_SFR_CAN_OFFSET 0x0048 /* CAN Memories Address-based Register */
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#endif
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SAM_SFR_SN0_OFFSET 0x004c /* Serial Number 0 Register */
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# define SAM_SFR_SN1_OFFSET 0x0050 /* Serial Number 1 Register */
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# define SAM_SFR_AICREDIR_OFFSET 0x0054 /* AIC Redirection Register */
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#endif
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#ifdef ATSAMA5D2
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# define SAM_SFR_L2CCHRAMC_OFFSET 0x0044 /* L2CC HRAMC1 */
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/* 0x005c-0x008c: Reserved */
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# define SAM_SFR_I2SCLKSEL_OFFSET 0x0090 /* I2SC Register */
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# define SAM_SFR_QSPICLK_OFFSET 0x0094 /* QSPI Clock Pad Supply Select Register */
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#endif
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/* 0x0098-0x3ffc: Reserved */
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/* SFR Register Addresses ***********************************************************/
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#define SAM_SFR_DDRCFG (SAM_SFR_VBASE+SAM_SFR_DDRCFG_OFFSET) /* REVISIT */
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@ -80,7 +93,7 @@
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#define SAM_SFR_SECURE (SAM_SFR_VBASE+SAM_SFR_SECURE_OFFSET)
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#define SAM_SFR_UTMICKTRIM (SAM_SFR_VBASE+SAM_SFR_UTMICKTRIM_OFFSET)
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SAM_SFR_UTMIHSTRIM (SAM_SFR_VBASE+SAM_SFR_UTMIHSTRIM_OFFSET)
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# define SAM_SFR_UTMIFSTRIM (SAM_SFR_VBASE+SAM_SFR_UTMIFSTRIM_OFFSET)
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# define SAM_SFR_UTMISWAP (SAM_SFR_VBASE+SAM_SFR_UTMISWAP_OFFSET)
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@ -88,12 +101,23 @@
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#define SAM_SFR_EBICFG (SAM_SFR_VBASE+SAM_SFR_EBICFG_OFFSET)
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#ifdef ATSAMA5D4
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#ifdef ATSAMA5D2
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# define SAM_SFR_ANACFG (SAM_SFR_VBASE+SAM_SFR_ANACFG_OFFSET)
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# define SAM_SFR_CAN (SAM_SFR_VBASE+SAM_SFR_CAN_OFFSET)
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#endif
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SAM_SFR_SN0 (SAM_SFR_VBASE+SAM_SFR_SN0_OFFSET)
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# define SAM_SFR_SN1 (SAM_SFR_VBASE+SAM_SFR_SN1_OFFSET)
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# define SAM_SFR_AICREDIR (SAM_SFR_VBASE+SAM_SFR_AICREDIR_OFFSET)
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#endif
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#ifdef ATSAMA5D2
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# define SAM_SFR_L2CCHRAMC (SAM_SFR_VBASE+SAM_SFR_L2CCHRAMC_OFFSET)
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# define SAM_SFR_I2SCLKSEL (SAM_SFR_VBASE+SAM_SFR_I2SCLKSEL_OFFSET)
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# define SAM_SFR_QSPICLK (SAM_SFR_VBASE+SAM_SFR_QSPICLK_OFFSET)
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#endif
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/* SFR Register Bit Definitions *****************************************************/
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/* DDR Configuration register */
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@ -109,8 +133,20 @@
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# define SFR_OHCIICR_RES2 (1 << 2) /* Bit 2: USB port 2 reset */
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#define SFR_OHCIICR_ARIE (1 << 4) /* Bit 4: OHCI asynchronous resume interrupt enable */
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#define SFR_OHCIICR_APPSTART (0) /* Bit 5: Reserved, must write 0 */
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#ifdef ATSAMA5D2
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# define SFR_OHCIICR_SUSPEND(n) (1 << ((n)+8))
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# define SFR_OHCIICR_SUSPENDA (1 << 8) /* Bit 8: Suspend USB port A */
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# define SFR_OHCIICR_SUSPENDB (1 << 9) /* Bit 9: Suspend USB port B */
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# define SFR_OHCIICR_SUSPENDC (1 << 10) /* Bit 10: Suspend USB port C */
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#endif
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#define SFR_OHCIICR_UDPPUDIS (1 << 23) /* Bit 23: USB device pull-up disable */
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#ifdef ATSAMA5D2
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# define SFR_OHCIICR_HSIC_SEL (0) /* Bit 27: Reserved (must write 0) */
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#endif
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/* OHCI Interrupt Status Register */
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#define SFR_OHCIISR_RIS0 (1 << 0) /* Bit 0: USB port 0 resume detected */
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@ -129,15 +165,17 @@
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# define SFR_UTMICKTRIM_FREQ_12MHZ (0 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 12 MHz reference clock */
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# define SFR_UTMICKTRIM_FREQ_16MHZ (1 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 16 MHz reference clock */
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# define SFR_UTMICKTRIM_FREQ_24MHZ (2 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 24 MHz reference clock */
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#ifndef ATSAMA5D2
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# define SFR_UTMICKTRIM_FREQ_48MHZ (3 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 48 MHz reference clock */
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#endif
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SFR_UTMICKTRIM_VBG_SHIFT (16) /* Bits 16-19: UTMI Band Gap Voltage Trimming */
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# define SFR_UTMICKTRIM_VBG_MASK (15 << SFR_UTMICKTRIM_VBG_SHIFT)
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# define SFR_UTMICKTRIM_VBG(n) ((uint32_t)(n) << SFR_UTMICKTRIM_VBG_SHIFT)
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#endif
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* UTMI High Speed Trimming Register */
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# define SFR_UTMIHSTRIM_SQUELCH_SHIFT (0) /* Bits 0-2: UTMI HS SQUELCH Voltage Trimming */
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@ -157,7 +195,7 @@
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# define SFR_UTMIHSTRIM_SLOPE2(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT)
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#endif
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* UTMI Full Speed Trimming Register */
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# define SFR_UTMIFSTRIM_RISE_SHIFT (0) /* Bits 0-2: FS Transceiver Output Rising Slope Trimming */
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@ -177,12 +215,13 @@
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# define SFR_UTMIFSTRIM_ZP(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT)
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#endif
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#ifdef ATSAMA5D4
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* UTMI DP/DM Pin Swapping Register */
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# define SFR_UTMISWAP_PORT0 (1 << 0) /* Bit 0: PORT 0 DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT1 (1 << 1) /* Bit 1: PORT 1 DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT2 (1 << 2) /* Bit 2: PORT 2 DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT(n) (1 << (n)) /* Bit n: PORT n DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT0 (1 << 0) /* Bit 0: PORT 0 DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT1 (1 << 1) /* Bit 1: PORT 1 DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT2 (1 << 2) /* Bit 2: PORT 2 DP/DM Pin Swapping */
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#endif
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/* EBI Configuration Register */
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@ -214,16 +253,61 @@
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# define SFR_EBICFG_BMS (1 << 16) /* Bit 16: BMS Sampled Value (Read Only) */
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#endif
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#ifdef ATSAMA5D4
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#ifdef ATSAMA5D2
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/* Analog Configuration Register */
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# define SFR_ANACFG_SMDDREN (1 << 0) /* Bit 0: DDR Supply Monitor Enable */
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#endif
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#ifdef ATSAMA5D2
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/* CAN Memories Address-based Register */
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# define SFR_CAN0_EXTMEMADDR_SHIFT (0) /* Bits 0-15: MSB CAN0 Base Address */
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# define SFR_CAN0_EXTMEMADDR_MASK (0xffff << SFR_CAN0_EXTMEMADDR_SHIFT)
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# define SFR_CAN0_EXTMEMADDR(n) ((uint32_t)(n) << SFR_CAN0_EXTMEMADDR_SHIFT)
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# define SFR_CAN1_EXTMEMADDR_SHIFT (16) /* Bits 16-31: MSB CAN0 Base Address */
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# define SFR_CAN1_EXTMEMADDR_MASK (0xffff << SFR_CAN1_EXTMEMADDR_SHIFT)
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# define SFR_CAN1_EXTMEMADDR(n) ((uint32_t)(n) << SFR_CAN1_EXTMEMADDR_SHIFT)
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#endif
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* Serial Number 0 Register (32-bit value) */
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/* Serial Number 1 Register (32-bit value) */
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/* AIC Redirection Register */
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# define SFR_AICREDIR_ENABLE (1 << 0) /* Bit 0: 1=All interrupts to AIC */
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# define SFR_AICREDIR_DISABLE (0) /* Bit 0: 0=Secure interrupts to SAIC */
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# define SFR_AICREDIR_NSAIC (1 << 0) /* Bit 0: Interrupt redirection to Non-Secure AIC */
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# define SFR_AICREDIR_ENABLE (1 << 0) /* Bit 0: 1=All interrupts to AIC */
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# define SFR_AICREDIR_DISABLE (0) /* Bit 0: 0=Secure interrupts to SAIC */
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# define SFR_AICREDIR_KEY (0x5f67b102) /* Bits 1-31: Access key */
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#endif
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#ifdef ATSAMA5D2
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/* L2CC HRAMC1 */
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# define SFR_L2CCHRAMC_SRAMSEL (1 << 0) /* Bit 0: SRAM selector */
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# define SFR_L2CCHRAMC_SRAM (0) /* Bit 0: 0=Selects SRAM */
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# define SFR_L2CCHRAMC_L2CC (1 << 0) /* Bit 0: 1=Selects L2CC */
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#endif
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#ifdef ATSAMA5D2
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/* I2SC Register */
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# define SFR_I2S_CLKSEL0 (1 << 0) /* Bit 0: Clock selection 0 */
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# define SFR_I2S_CLKSEL0_GCLK (0) /* Bit 0: 0=Selects GCLK */
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# define SFR_I2S_CLKSEL0_PCLK (1 << 0) /* Bit 0: 1=Selects PCLK */
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# define SFR_I2S_CLKSEL1 (1 << 1) /* Bit 1: Clock selection 1 */
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# define SFR_I2S_CLKSEL1_GCLK (0) /* Bit 0: 0=Selects GCLK */
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# define SFR_I2S_CLKSEL1_PCLK (1 << 1) /* Bit 0: 1=Selects PCLK */
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#endif
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#ifdef ATSAMA5D2
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/* QSPI Clock Pad Supply Select Register */
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# define SFR_QSPICLK_SUPSEL (1 << 0) /* Bit 0: Supply selection */
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# define SFR_QSPICLK_1p8V (0) /* Bit 0: 0=1.8V */
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# define SFR_QSPICLK_3p3V (1 << 0) /* Bit 0: 1=3.3V */
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#endif
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H */
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@ -2,7 +2,7 @@
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* arch/arm/src/sama5/chip/sam_wdt.h
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* Watchdog Timer (WDT) definitions for the SAMA5D3
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -65,7 +65,12 @@
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/* WDT register bit definitions ********************************************************/
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/* Watchdog Timer Control Register */
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#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
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#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Restart */
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#ifdef ATSAMA5D2
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#define WDT_CR_LOCKMR (1 << 4) /* Bit 4: Lock Mode Register Write Access */
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#endif
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#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
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#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
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# define WDT_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT)
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@ -59,6 +59,7 @@
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#include "chip/sam_wdt.h"
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#include "chip/sam_aximx.h"
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#include "chip/sam_sfr.h"
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#include "sam_clockconfig.h"
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#include "sam_memorymap.h"
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@ -412,17 +413,8 @@ void up_boot(void)
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const uint32_t *src;
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uint32_t *dest;
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAMA5D2) && !defined(CONFIG_ARCH_L2CACHE)
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/* The SAMA5D2 features a second 128-Kbyte SRAM that can be allocated
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* either to the L2 cache controller or used as an internal SRAM. After
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* reset, this block is connected to the L2 cache controller. The
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* SRAM_SEL bit, located in the SFR_L2CC_HRAMC register, is used to
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* reassign this memory as system SRAM, making the two 128-Kbyte
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* RAMs contiguous.
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*/
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# warning Missing Logic
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#ifdef ATSAMA5D2
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uint32_t regval;
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#endif
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#ifndef CONFIG_ARCH_ROMPGTABLE
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@ -440,6 +432,26 @@ void up_boot(void)
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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#ifdef ATSAMA5D2
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/* The SAMA5D2 features a second 128-Kbyte SRAM that can be allocated
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* either to the L2 cache controller or used as an internal SRAM. After
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* reset, this block is connected to the L2 cache controller. The
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* SRAM_SEL bit, located in the SFR_L2CC_HRAMC register, is used to
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* reassign this memory as system SRAM, making the two 128-Kbyte
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* RAMs contiguous.
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*/
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regval = getreg32(SAM_SFR_L2CCHRAMC);
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#ifdef CONFIG_ARCH_L2CACHE
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regval |= SFR_L2CCHRAMC_SRAMSEL; /* 1=Selects L2CC */
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#else
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regval &= ~SFR_L2CCHRAMC_SRAMSEL; /* 0=Selects SRAM */
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#endif
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putreg32(regval, SAM_SFR_L2CCHRAMC);
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#endif
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#ifdef CONFIG_ARCH_RAMFUNCS
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/* Copy any necessary code sections from FLASH to RAM. The correct
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* destination in SRAM is given by _sramfuncs and _eramfuncs. The
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