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ARMv7-A: If the page table does not like in same address range as .text and primary RAM, then we will need to set up an additional mapping for the page table at boot time.

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This commit is contained in:
Gregory Nutt 2013-12-16 08:26:07 -06:00
parent 7fdf57b7bb
commit c4380b5a8f
4 changed files with 109 additions and 12 deletions
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27
arch/arm/src/a1x/chip/a10_memorymap.h
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@ -447,6 +447,8 @@
# error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined"
# endif
#else /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */
/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
* map probably do not apply because paging logic will probably partition
* the SRAM section differently. In particular, if the page table is located
@ -459,20 +461,31 @@
* in the way at that position.
*/
#elif defined(CONFIG_ARCH_LOWVECTORS)
#if defined(CONFIG_ARCH_LOWVECTORS)
/* In this case, table must lie in SRAM A1 after the vectors */
# define PGTABLE_BASE_PADDR (A1X_SRAMA1_PADDR + 16384)
# define PGTABLE_BASE_VADDR (A1X_SRAMA1_VADDR + 16384)
# define PGTABLE_BASE_PADDR (A1X_SRAMA1_PADDR + 16384)
# define PGTABLE_BASE_VADDR (A1X_SRAMA1_VADDR + 16384)
# else /* CONFIG_ARCH_LOWVECTORS */
#else
/* Otherwise, the vectors lie at another location. The page table will
* then be positioned at the beginning of SRAM A1.
*/
# define PGTABLE_BASE_PADDR A1X_SRAMA1_PADDR
# define PGTABLE_BASE_VADDR A1X_SRAMA1_VADDR
#endif
# define PGTABLE_BASE_PADDR A1X_SRAMA1_PADDR
# define PGTABLE_BASE_VADDR A1X_SRAMA1_VADDR
# endif /* CONFIG_ARCH_LOWVECTORS */
/* Note that the page table does not lie in the same address space as does the
* mapped RAM in either case. So we will need to create a special mapping for
* the page table at boot time.
*/
# define ARMV7A_PGTABLE_MAPPING 1
#endif /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */
/* Level 2 Page table start addresses.
*

48
arch/arm/src/armv7-a/arm_head.S
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@ -220,6 +220,31 @@ __start:
teq r0, r2
bne .Lpgtableclear
#ifdef ARMV7A_PGTABLE_MAPPING
/* If the page table does not lie in the same address space as does the
* mapped RAM in either case. So we will need to create a special
* mapping for the page table.
*
* Load informtion needed to map the page table. After the ldmia, we
* will have
*
* R1 = The aligned, physical base address of the page table
* R2 = The aligned, virtual base address of the page table
* R3 = The MMU flags to use with the .text space mapping
* R5 = The physical address of the L1 page table (from above)
*
* The value in R1 could have been obtained by simply masking R5.
*/
adr r0, .LCptinfo /* Address of page table description */
ldmia r0, {r1, r2, r3} /* Load the page table description */
/* A single page is sufficient to map the page table */
orr r0, r1, r3 /* OR MMU flags into physical address */
str r0, [r5, r2, lsr #18] /* Map using the virtual address as an index */
#endif
/* Load information needed to map the .text region. After the ldmia, we
* will have:
*
@ -234,7 +259,7 @@ __start:
ldmia r0, {r1, r2, r3, r4} /* Load the text description */
/* Create identity mapping for first MB of the .text section to support
* this startup logic executing out of the physical address space. This
* this start-up logic executing out of the physical address space. This
* identity mapping will be removed by .Lvstart (see below). Of course,
* we would only do this if the physical-virtual mapping is not already
* the identity mapping.
@ -245,7 +270,7 @@ __start:
str r0, [r5, r1, lsr #18] /* Identity mapping */
#endif
/* Map the entire .text regtion. We do this before enabling caches so
/* Map the entire .text region. We do this before enabling caches so
* we know that the data will be in place in the data cache. We map the
* entire text region because we don't know which parts are needed for
* start-up.
@ -496,6 +521,23 @@ __start:
.long PGTABLE_BASE_PADDR /* Physical start of page table */
.size .LCppgtable, . -.LCppgtable
#ifdef ARMV7A_PGTABLE_MAPPING
/* Page table region description. The order of these fields must not
* change because the values are loaded using ldmia:
*
* 1) The aligned, physical base address of the page table
* 2) The aligned, virtual base address of the page table
* 3) The MMU flags to use with the .text space mapping
*/
.type .LCptinfo, %object
.LCptinfo:
.long (PGTABLE_BASE_PADDR & 0xfff00000) /* Physical base address */
.long (PGTABLE_BASE_VADDR & 0xfff00000) /* Virtual base address */
.long MMU_MEMFLAGS /* MMU flags for text section in RAM */
.size .LCptinfo, . -.LCptinfo
#endif
#ifndef CONFIG_ARCH_ROMPGTABLE
/* Text region description. The order of these fields must not change
* because the values are loaded using ldmia:
@ -595,7 +637,7 @@ __start:
strcc fp, [r0],#4
bcc .Lbssinit
/* If the .data section is in a separate, unitialized address space,
/* If the .data section is in a separate, uninitialized address space,
* then we will also need to copy the initial values of of the .data
* section from the .text region into that .data region. This would
* be the case if we are executing from FLASH and the .data section

44
arch/arm/src/armv7-a/arm_pghead.S
View File

@ -247,8 +247,33 @@ __start:
teq r0, r2
bne .Lpgtableclear
#ifdef ARMV7A_PGTABLE_MAPPING
/* If the page table does not lie in the same address space as does the
* mapped RAM in either case. So we will need to create a special
* mapping for the page table.
*
* Load information needed to map the page table. After the ldmia, we
* will have
*
* R1 = The aligned, physical base address of the page table
* R2 = The aligned, virtual base address of the page table
* R3 = The MMU flags to use with the .text space mapping
* R5 = The physical address of the L1 page table (from above)
*
* The value in R1 could have been obtained by simply masking R5.
*/
adr r0, .LCptinfo /* Address of page table description */
ldmia r0, {r1, r2, r3} /* Load the page table description */
/* A single page is sufficient to map the page table */
orr r0, r1, r3 /* OR MMU flags into physical address */
str r0, [r5, r2, lsr #18] /* Map using the virtual address as an index */
#endif
/* Create identity mapping for first MB of the .text section to support
* this startup logic executing out of the physical address space. This
* this start-up logic executing out of the physical address space. This
* identity mapping will be removed by .Lvstart (see below). Of course,
* we would only do this if the physical-virtual mapping is not already
* the identity mapping.
@ -482,6 +507,23 @@ __start:
.long .Lvstart
.size .LCvstart, . -.LCvstart
#ifdef ARMV7A_PGTABLE_MAPPING
/* Page table region description. The order of these fields must not
* change because the values are loaded using ldmia:
*
* 1) The aligned, physical base address of the page table
* 2) The aligned, virtual base address of the page table
* 3) The MMU flags to use with the .text space mapping
*/
.type .LCptinfo, %object
.LCptinfo:
.long (PGTABLE_BASE_PADDR & 0xfff00000) /* Physical base address */
.long (PGTABLE_BASE_VADDR & 0xfff00000) /* Virtual base address */
.long MMU_MEMFLAGS /* MMU flags for text section in RAM */
.size .LCptinfo, . -.LCptinfo
#endif
/* The aligned, physical base address of the .text section */
.type .LCptextbase, %object

2
libc/stdio/lib_sscanf.c
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@ -456,7 +456,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap)
return count;
}
set_errno(errno);
set_errno(errsave);
/* We have to check whether we need to return a long
* or an int.