Complete replacement of PHY logic for Am79c874
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1573 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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dc036906b7
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@ -123,12 +123,28 @@
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# error "Unsupported CONFIG_EZ80_PKTBUFSIZE value"
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#endif
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/* Am79c874 PHY configuration */
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#define EZ80_EMAC_AUTONEG 0
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#define EZ80_EMAC_100BFD 1
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#define EZ80_EMAC_100BHD 2
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#define EZ80_EMAC_10BFD 3
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#define EZ80_EMAC_10BHD 4
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#ifndef CONFIG_EZ80_PHYCONFIG
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# define CONFIG_EZ80_PHYCONFIG EZ80_EMAC_10BFD
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#endif
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/* Select the fastest MDC clock that does not exceed 25MHz. The MDC
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* clock derives from the SCLK divided by 4, 6, 8, 10, 14, 20, or 28.
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*/
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#ifndef CONFIG_EZ80_MDCDIV
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# define CONFIG_EZ80_MDCDIV EMAC_MDC_DIV4
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# ifdef CONFIG_EZ80_PHYAM79C874
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# define CONFIG_EZ80_MDCDIV EMAC_MDC_DIV20
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# else
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# define CONFIG_EZ80_MDCDIV EMAC_MDC_DIV4
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# endif
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#endif
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/* Select the Tx poll timer. If not specified, a 10MS timer is set */
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@ -319,7 +335,7 @@ static void ez80emac_miiwrite(FAR struct ez80emac_driver_s *priv, ubyte offse
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static uint16 ez80emac_miiread(FAR struct ez80emac_driver_s *priv, uint32 offset);
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static boolean ez80emac_miipoll(FAR struct ez80emac_driver_s *priv, uint32 offset,
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uint16 bits, boolean bclear);
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static void ez80emac_miiautonegotiate(FAR struct ez80emac_driver_s *priv);
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static int ez80emac_miiautonegotiate(FAR struct ez80emac_driver_s *priv);
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/* Multi-cast filtering */
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@ -523,7 +539,156 @@ static boolean ez80emac_miipoll(FAR struct ez80emac_driver_s *priv, uint32 offse
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*
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****************************************************************************/
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static void ez80emac_miiautonegotiate(FAR struct ez80emac_driver_s *priv)
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#ifdef CONFIG_EZ80_PHYAM79C874
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static int ez80emac_miiautonegotiate(FAR struct ez80emac_driver_s *priv)
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{
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uint16 phyval;
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boolean bauto;
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int ret = OK;
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int i;
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/* Verify that the detect PHY is an AMD Am87c874 as expected */
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#ifdef CONFIG_DEBUG /* Parameter checking only done when DEBUG is enabled */
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phyval = ez80emac_miiread(priv, MII_PHYID1);
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if (phyval != MII_PHYID1_AM79C874)
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{
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ndbg("Not an Am79c874 PHY: PHY1=%04x vs %04x\n", phyval, MII_PHYID1_AM79C874);
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ret = -ENODEV;
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goto dumpregs;
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}
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phyval = ez80emac_miiread(priv, MII_PHYID2);
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if (phyval != MII_PHYID2_AM79C874)
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{
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ndbg("Not an Am79c874 PHY: PHY2=%04x vs %04x\n", phyval, MII_PHYID2_AM79C874);
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ret = -ENODEV;
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goto dumpregs;
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}
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#endif
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/* Check if the PHY can do auto-negotiation */
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phyval = ez80emac_miiread(priv, MII_MSR);
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if (phyval & MII_MSR_ANEGABLE)
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{
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phyval = MII_MCR_ANRESTART | MII_MCR_ANENABLE;
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bauto = TRUE;
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}
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else
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{
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phyval = 0;
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bauto = FALSE;
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/* PADEN - EMAC pads all short frames by adding zeroes to the end of
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* the data field. This bit is used in conjunction with ADPADN
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* and VLPAD.
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* CRCEN - Append CRC to every frame regardless of padding options.
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*/
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outp(EZ80_EMAC_CFG1, EMAC_CFG1_PADEN|EMAC_CFG1_CRCEN);
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}
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/* Set the configured link capabilities */
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#if CONFIG_EZ80_PHYCONFIG == EZ80_EMAC_AUTONEG
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ndbg("Configure autonegotiation\n");
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if (bauto)
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{
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ez80emac_miiwrite(priv, MII_ADVERTISE,
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MII_ADVERTISE_100BASETXFULL|MII_ADVERTISE_100BASETXHALF|
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MII_ADVERTISE_10BASETXFULL|MII_ADVERTISE_10BASETXHALF|
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MII_ADVERTISE_CSMA);
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}
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else
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{
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ndbg("Am79c784 is not capable of autonegotiation\n");
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}
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#elif CONFIG_EZ80_PHYCONFIG == EZ80_EMAC_100BFD
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ndbg("100BASETX full duplex\n");
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phyval |= MII_MCR_SPEED100 | MII_MCR_FULLDPLX;
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ez80emac_miiwrite(priv, MII_ADVERTISE,
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MII_ADVERTISE_100BASETXFULL|MII_ADVERTISE_100BASETXHALF|
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MII_ADVERTISE_10BASETXFULL|MII_ADVERTISE_10BASETXHALF|
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MII_ADVERTISE_CSMA);
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#elif CONFIG_EZ80_PHYCONFIG == EZ80_EMAC_100BHD
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ndbg("100BASETX half duplex\n");
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phyval |= MII_MCR_SPEED100;
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ez80emac_miiwrite(priv, MII_ADVERTISE,
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MII_ADVERTISE_100BASETXHALF|MII_ADVERTISE_10BASETXFULL|
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MII_ADVERTISE_10BASETXHALF|MII_ADVERTISE_CSMA);
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#elif CONFIG_EZ80_PHYCONFIG == EZ80_EMAC_10BFD
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ndbg("10BASETX full duplex\n");
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phyval |= MII_MCR_FULLDPLX;
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ez80emac_miiwrite(priv, MII_ADVERTISE,
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MII_ADVERTISE_10BASETXFULL|MII_ADVERTISE_10BASETXHALF|MII_ADVERTISE_CSMA);
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#elif CONFIG_EZ80_PHYCONFIG == EZ80_EMAC_10BHD
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ndbg("10BASETX half duplex\n");
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ez80emac_miiwrite(priv, MII_ADVERTISE,
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MII_ADVERTISE_10BASETXHALF|MII_ADVERTISE_CSMA);
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#else
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# error "No recognized value of CONFIG_EZ80_PHYCONFIG"
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#endif
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ez80emac_miiwrite(priv, MII_MCR, phyval);
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/* Wait for a link to be established */
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for (i = 0; i < 50; i++)
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{
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phyval = ez80emac_miiread(priv, MII_MSR);
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if ((phyval & (MII_MSR_ANEGCOMPLETE | MII_MSR_LINKSTATUS)) != 0)
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{
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break;
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}
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up_mdelay(10);
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}
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if ((phyval & MII_MSR_LINKSTATUS) == 0)
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{
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ndbg("Failed to establish link\n");
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ret = -ETIMEDOUT;
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}
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else
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{
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/* Read the Am79c874 diagnostics register for link settings */
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phyval = ez80emac_miiread(priv, MII_AM79C874_DIAGNOSTIC);
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if (phyval & AM79C874_DIAG_FULLDPLX)
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{
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outp(EZ80_EMAC_CFG1, EMAC_CFG1_PADEN|EMAC_CFG1_CRCEN|EMAC_CFG1_FULLHD);
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}
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else
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{
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outp(EZ80_EMAC_CFG1, EMAC_CFG1_PADEN|EMAC_CFG1_CRCEN);
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}
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}
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dumpregs:
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nvdbg("Am79c874 MII registers (FIAD=%lx)\n", CONFIG_EZ80_FIAD);
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nvdbg(" MII_MCR: %04x\n", ez80emac_miiread(priv, MII_MCR));
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nvdbg(" MII_MSR: %04x\n", ez80emac_miiread(priv, MII_MSR));
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nvdbg(" MII_PHYID1: %04x\n", ez80emac_miiread(priv, MII_PHYID1));
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nvdbg(" MII_PHYID2: %04x\n", ez80emac_miiread(priv, MII_PHYID2));
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nvdbg(" MII_ADVERTISE: %04x\n", ez80emac_miiread(priv, MII_ADVERTISE));
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nvdbg(" MII_LPA: %04x\n", ez80emac_miiread(priv, MII_LPA));
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nvdbg(" MII_EXPANSION: %04x\n", ez80emac_miiread(priv, MII_EXPANSION));
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nvdbg(" MII_DIAGNOSTICS: %04x\n", ez80emac_miiread(priv, MII_AM79C874_DIAGNOSTIC));
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nvdbg("EMAC CFG1: %02x\n", inp(EZ80_EMAC_CFG1));
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return ret;
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}
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#else
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static int ez80emac_miiautonegotiate(FAR struct ez80emac_driver_s *priv)
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{
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uint16 advertise;
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uint16 lpa;
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@ -656,7 +821,10 @@ static void ez80emac_miiautonegotiate(FAR struct ez80emac_driver_s *priv)
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nvdbg(" MII_ADVERTISE: %04x\n", ez80emac_miiread(priv, MII_ADVERTISE));
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nvdbg(" MII_LPA: %04x\n", ez80emac_miiread(priv, MII_LPA));
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nvdbg(" MII_EXPANSION: %04x\n", ez80emac_miiread(priv, MII_EXPANSION));
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nvdbg("EMAC CFG1: %02x\n", inp(EZ80_EMAC_CFG11));
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return OK;
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}
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#endif
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/****************************************************************************
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* Function: ez80emac_machash
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@ -1308,9 +1476,13 @@ static int ez80emac_ifup(FAR struct uip_driver_s *dev)
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ubyte regval;
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int ret;
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24)
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ndbg("Bringing up: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
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dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
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dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
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dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
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ndbg(" IP %d.%d.%d.%d\n",
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dev->d_ipaddr >> 24, (dev->d_ipaddr >> 16) & 0xff,
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(dev->d_ipaddr >> 8) & 0xff, dev->d_ipaddr & 0xff);
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/* Bring up the interface -- Must be down right now */
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@ -1678,7 +1850,7 @@ static int ez80_emacinitialize(void)
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/* Set auto-negotion */
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ez80emac_miiautonegotiate(priv);
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ret = ez80emac_miiautonegotiate(priv);
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/* Initialize DMA / FIFO */
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