sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

boards/xtensa/esp32: Change the name of the flash segment to irom_0_0

Browse Source 
instead of iram_0_2.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-06-23 12:32:46 +01:00 committed by Xiang Xiao
parent 4c559c8324
commit c4b0a85841
3 changed files with 12 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld
View File

@ -28,17 +28,16 @@ MEMORY
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
/* Even though the segment name is iram, it is actually mapped to flash.
/* Flash mapped instruction data.
*
* NOTE: (0x20 offset above is a convenience for the app binary image
* generation.
* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@ -79,7 +78,7 @@ MEMORY
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
REGION_ALIAS("default_code_seg", iram0_2_seg);
REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */
/* Heap ends at top of dram0_0_seg */

9
boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld
View File

@ -28,17 +28,16 @@ MEMORY
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
/* Even though the segment name is iram, it is actually mapped to flash.
/* Flash mapped instruction data.
*
* NOTE: (0x20 offset above is a convenience for the app binary image
* generation.
* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@ -79,7 +78,7 @@ MEMORY
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
REGION_ALIAS("default_code_seg", iram0_2_seg);
REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */
/* Heap ends at top of dram0_0_seg */

9
boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld
View File

@ -28,17 +28,16 @@ MEMORY
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
/* Even though the segment name is iram, it is actually mapped to flash.
/* Flash mapped instruction data.
*
* NOTE: (0x20 offset above is a convenience for the app binary image
* generation.
* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@ -79,7 +78,7 @@ MEMORY
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
REGION_ALIAS("default_code_seg", iram0_2_seg);
REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */
/* Heap ends at top of dram0_0_seg */