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More DAC changes from John Wharington

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This commit is contained in:
Gregory Nutt 2013-07-30 11:41:53 -06:00
parent 2c6b370c4a
commit c4c222ca3a
1 changed files with 3 additions and 1 deletions
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4
arch/arm/src/stm32/stm32_dac.c
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@ -333,10 +333,10 @@ struct stm32_chan_s
#endif #endif
uint8_t intf; /* DAC zero-based interface number (0 or 1) */ uint8_t intf; /* DAC zero-based interface number (0 or 1) */
uint32_t dro; /* Data output register */ uint32_t dro; /* Data output register */
uint32_t tsel; /* CR trigger select value */
#ifdef HAVE_DMA #ifdef HAVE_DMA
uint16_t dmachan; /* DMA channel needed by this DAC */ uint16_t dmachan; /* DMA channel needed by this DAC */
DMA_HANDLE dma; /* Allocated DMA channel */ DMA_HANDLE dma; /* Allocated DMA channel */
uint32_t tsel; /* CR trigger select value */
uint32_t tbase; /* Timer base address */ uint32_t tbase; /* Timer base address */
uint32_t tfrequency; /* Timer frequency */ uint32_t tfrequency; /* Timer frequency */
uint16_t dmabuffer[CONFIG_STM32_DAC_DMA_BUFFER_SIZE]; /* DMA transfer buffer */ uint16_t dmabuffer[CONFIG_STM32_DAC_DMA_BUFFER_SIZE]; /* DMA transfer buffer */
@ -741,7 +741,9 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
/* Reset counters (generate an update) */ /* Reset counters (generate an update) */
#ifdef HAVE_DMA
tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG); tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG);
#endif
return OK; return OK;
} }