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Early bringup bugfixes

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2752 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-06-19 17:19:34 +00:00
parent 8f979150db
commit c4d5f3b90b
4 changed files with 15 additions and 23 deletions
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30
arch/arm/src/lpc17xx/lpc17_allocateheap.c
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@ -77,25 +77,11 @@
#ifdef LPC17_HAVE_BANK0
# if CONFIG_MM_REGIONS < 2
# warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank0 not included in HEAP"
# warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank(s) not included in HEAP"
# endif
#else
# if CONFIG_MM_REGIONS > 1
# warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 1
# endif
#endif
#ifdef LPC17_HAVE_BANK1
# if CONFIG_MM_REGIONS < 3
# warning "CONFIG_MM_REGIONS < 3: AHB SRAM Bank1 not included in HEAP"
# endif
#else
# if CONFIG_MM_REGIONS > 2
# warning "CONFIG_MM_REGIONS > 2: This MCU has no AHB SRAM Bank1"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
# warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0/1"
# endif
#endif
@ -141,10 +127,16 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
mm_addregion((FAR void*)LPC17_HAVE_BANK0, 16*1024);
/* Banks 0 and 1 are each 16Kb. If both are present, they occupy a
* contiguous 32Kb memory region.
*/
#if CONFIG_MM_REGIONS > 2
mm_addregion((FAR void*)LPC17_HAVE_BANK1, 16*1024);
#ifdef LPC17_HAVE_BANK0
# ifdef LPC17_HAVE_BANK1
mm_addregion((FAR void*)LPC17_SRAM_BANK0, 32*1024);
# else
mm_addregion((FAR void*)LPC17_SRAM_BANK0, 16*1024);
# endif
#endif
}
#endif

4
arch/arm/src/lpc17xx/lpc17_gpio.c
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@ -110,9 +110,9 @@ const uint32_t g_fiobase[GPIO_NPORTS] =
const uint32_t g_intbase[GPIO_NPORTS] =
{
LPC17_GPIOINT0_OFFSET,
LPC17_GPIOINT0_BASE,
0,
LPC17_GPIOINT2_OFFSET,
LPC17_GPIOINT2_BASE,
0,
0
};

2
arch/arm/src/lpc17xx/lpc17_memorymap.h
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@ -54,7 +54,7 @@
#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
# define LPC17_SRAM_BANK0 0x20070000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */
#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */
#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */

2
configs/nucleus2g/ostest/defconfig
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@ -299,7 +299,7 @@ CONFIG_EXAMPLE=ostest
CONFIG_DEBUG=n
CONFIG_DEBUG_VERBOSE=n
CONFIG_DEBUG_SYMBOLS=n
CONFIG_MM_REGIONS=3
CONFIG_MM_REGIONS=2
CONFIG_ARCH_LOWPUTC=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_INSTRUMENTATION=n