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Centralize definitions associated with CONFIG_DEBUG_IRQ

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This commit is contained in:
Gregory Nutt 2016-06-15 08:35:22 -06:00
parent de008c284a
commit c4e6f50eac
33 changed files with 708 additions and 765 deletions
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29
Kconfig
View File

@ -806,9 +806,11 @@ config DEBUG_HEAP
Enable hooks to check heap usage. Only supported by a few architectures.
config DEBUG_IRQ
bool "Interrupt Controller Debug Output"
bool "Interrupt Controller Debug Features"
default n
---help---
Enable interrupt controller debug features.
Some (but not all) architectures support debug output to verify
interrupt controller logic. If supported, then option will enable
that output. This may interfere with normal operations! You
@ -816,6 +818,31 @@ config DEBUG_IRQ
that here is a problem with that logic. On some platforms, this
option may even cause crashes! Use with care!
if DEBUG_IRQ
config DEBUG_IRQ_ERROR
bool "DMA Error Output"
default n
depends on DEBUG_ERROR
---help---
Enable interrupt controller error output to SYSLOG.
config DEBUG_IRQ_WARN
bool "DMA Warnings Output"
default n
depends on DEBUG_WARN
---help---
Enable interrupt controller warning output to SYSLOG.
config DEBUG_IRQ_INFO
bool "DMA Informational Output"
default n
depends on DEBUG_INFO
---help---
Enable interrupt controller informational output to SYSLOG.
endif # DEBUG_IRQ
config DEBUG_PAGING
bool "Paging Debug Features"
default n

66
arch/arm/src/a1x/a1x_irq.c
View File

@ -77,7 +77,7 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void a1x_dumpintc(const char *msg, int irq)
{
irqstate_t flags;
@ -85,40 +85,42 @@ static void a1x_dumpintc(const char *msg, int irq)
/* Dump some relevant ARMv7 register contents */
flags = enter_critical_section();
llerr("ARMv7 (%s, irq=%d):\n", msg, irq);
llerr(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
irqinfo("ARMv7 (%s, irq=%d):\n", msg, irq);
irqinfo(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
/* Dump all of the (readable) INTC register contents */
llerr("INTC (%s, irq=%d):\n", msg, irq);
llerr(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
llerr(" IRQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
getreg32(A1X_INTC_IRQ_PEND2));
llerr(" FIQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
getreg32(A1X_INTC_FIQ_PEND2));
llerr(" SEL: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
getreg32(A1X_INTC_IRQ_SEL2));
llerr(" EN: %08x %08x %08x\n",
getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
getreg32(A1X_INTC_EN2));
llerr(" MASK: %08x %08x %08x\n",
getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
getreg32(A1X_INTC_MASK2));
llerr(" RESP: %08x %08x %08x\n",
getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
getreg32(A1X_INTC_RESP2));
llerr(" FF: %08x %08x %08x\n",
getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
getreg32(A1X_INTC_FF2));
llerr(" PRIO: %08x %08x %08x %08x %08x\n",
getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
getreg32(A1X_INTC_PRIO4));
irqinfo("INTC (%s, irq=%d):\n", msg, irq);
irqinfo(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
irqinfo(" IRQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
getreg32(A1X_INTC_IRQ_PEND2));
irqinfo(" FIQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
getreg32(A1X_INTC_FIQ_PEND2));
irqinfo(" SEL: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
getreg32(A1X_INTC_IRQ_SEL2));
irqinfo(" EN: %08x %08x %08x\n",
getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
getreg32(A1X_INTC_EN2));
irqinfo(" MASK: %08x %08x %08x\n",
getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
getreg32(A1X_INTC_MASK2));
irqinfo(" RESP: %08x %08x %08x\n",
getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
getreg32(A1X_INTC_RESP2));
irqinfo(" FF: %08x %08x %08x\n",
getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
getreg32(A1X_INTC_FF2));
irqinfo(" PRIO: %08x %08x %08x %08x %08x\n",
getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
getreg32(A1X_INTC_PRIO4));
leave_critical_section(flags);
}
#else

2
arch/arm/src/armv7-a/arm_gicv2.c
View File

@ -387,7 +387,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
regval = getreg32(GIC_ICCIAR);
irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
gicllinfo("irq=%d\n", irq);
irqllinfo("irq=%d\n", irq);
/* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
* interrupt.

52
arch/arm/src/armv7-a/arm_gicv2_dump.c
View File

@ -40,12 +40,12 @@
#include <nuttx/config.h>
#include <stdint.h>
#include <syslog.h>
#include <debug.h>
#include "up_arch.h"
#include "gic.h"
#if defined(CONFIG_ARMV7A_HAVE_GICv2) && defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_ARMV7A_HAVE_GICv2) && defined(CONFIG_DEBUG_IRQ_INFO)
/****************************************************************************
* Private Functions
@ -69,20 +69,20 @@
static inline void arm_gic_dump_cpu(bool all, int irq, int nlines)
{
lowsyslog(LOG_INFO, " CPU Interface Registers:\n");
lowsyslog(LOG_INFO, " ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
irqllinfo(" CPU Interface Registers:\n");
irqllinfo(" ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
lowsyslog(LOG_INFO, " RPR: %08x HPIR: %08x ABPR: %08x\n",
irqllinfo(" RPR: %08x HPIR: %08x ABPR: %08x\n",
getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
getreg32(GIC_ICCABPR));
lowsyslog(LOG_INFO, " AIAR: %08x AHPIR: %08x IDR: %08x\n",
irqllinfo(" AIAR: %08x AHPIR: %08x IDR: %08x\n",
getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
getreg32(GIC_ICCIDR));
lowsyslog(LOG_INFO, " APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
irqllinfo(" APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
lowsyslog(LOG_INFO, " NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
irqllinfo(" NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
}
@ -110,7 +110,7 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
incr <<= 2;
for (i = 0; i < nlines; i += incr, regaddr += 16)
{
lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(regaddr), getreg32(regaddr + 4),
getreg32(regaddr + 8), getreg32(regaddr + 12));
}
@ -135,7 +135,7 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
int nlines)
{
lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 4);
}
@ -158,7 +158,7 @@ static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
int nlines)
{
lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 8);
}
@ -181,7 +181,7 @@ static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
int nlines)
{
lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 16);
}
@ -204,7 +204,7 @@ static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
int nlines)
{
lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 32);
}
@ -226,8 +226,8 @@ static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
{
lowsyslog(LOG_INFO, " Distributor Registers:\n");
lowsyslog(LOG_INFO, " DCR: %08x ICTR: %08x IIDR: %08x\n",
irqllinfo(" Distributor Registers:\n");
irqllinfo(" DCR: %08x ICTR: %08x IIDR: %08x\n",
getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
getreg32(GIC_ICDIIDR));
@ -246,25 +246,25 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
}
else
{
lowsyslog(LOG_INFO, " ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
irqllinfo(" ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
lowsyslog(LOG_INFO, " IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
irqllinfo(" IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
lowsyslog(LOG_INFO, " NSACR: %08x SCPR: %08x\n",
irqllinfo(" NSACR: %08x SCPR: %08x\n",
getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
}
lowsyslog(LOG_INFO, " PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
irqllinfo(" PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
getreg32(GIC_ICDPIDR(6)));
lowsyslog(LOG_INFO, " CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
irqllinfo(" CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
irqllinfo(" %08x %08x %08x %08x\n",
getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
}
@ -295,15 +295,15 @@ void arm_gic_dump(const char *msg, bool all, int irq)
if (all)
{
lowsyslog(LOG_INFO, "GIC: %s NLINES=%u\n", msg, nlines);
irqllinfo("GIC: %s NLINES=%u\n", msg, nlines);
}
else
{
lowsyslog(LOG_INFO, "GIC: %s IRQ=%d\n", msg, irq);
irqllinfo("GIC: %s IRQ=%d\n", msg, irq);
}
arm_gic_dump_cpu(all, irq, nlines);
arm_gic_dump_distributor(all, irq, nlines);
}
#endif /* CONFIG_ARMV7A_HAVE_GICv2 && CONFIG_DEBUG_IRQ */
#endif /* CONFIG_ARMV7A_HAVE_GICv2 && CONFIG_DEBUG_IRQ_INFO */

17
arch/arm/src/armv7-a/gic.h
View File

@ -590,21 +590,6 @@
#define GIC_IRQ_SPI 32 /* First SPI interrupt ID */
/* General Macro Definitions ************************************************/
/* Debug */
#ifdef CONFIG_DEBUG_IRQ
# define gicerr(format, ...) err(format, ##__VA_ARGS__)
# define gicllerr(format, ...) llerr(format, ##__VA_ARGS__)
# define gicinfo(format, ...) info(format, ##__VA_ARGS__)
# define gicllinfo(format, ...) llinfo(format, ##__VA_ARGS__)
#else
# define gicerr(x...)
# define gicllerr(x...)
# define gicinfo(x...)
# define gicllinfo(x...)
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
@ -817,7 +802,7 @@ int arm_pause_handler(int irq, FAR void *context);
*
****************************************************************************/
#ifdef CONFIG_DEBUG_IRQ
#ifdef CONFIG_DEBUG_IRQ_INFO
void arm_gic_dump(const char *msg, bool all, int irq);
#else
# define arm_gic_dump(m,a,i)

35
arch/arm/src/armv7-m/up_ramvec_attach.c
View File

@ -49,39 +49,6 @@
#ifdef CONFIG_ARCH_RAMVECTORS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Debug ********************************************************************/
/* Non-standard debug that may be enabled just for testing the interrupt
* config. NOTE: that only llerr types are used so that the output is
* immediately available.
*/
#ifdef CONFIG_DEBUG_IRQ
# define interr llerr
# define intinfo llinfo
#else
# define interr(x...)
# define intinfo(x...)
#endif
/****************************************************************************
* Private Type Declarations
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@ -103,7 +70,7 @@ int up_ramvec_attach(int irq, up_vector_t vector)
{
int ret = -EINVAL;
intinfo("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
irqinfo("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
if ((unsigned)irq < NR_VECTORS)
{

22
arch/arm/src/armv7-m/up_ramvec_initialize.c
View File

@ -71,24 +71,6 @@
#define RAMVEC_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
/* Debug ********************************************************************/
/* Non-standard debug that may be enabled just for testing the interrupt
* config. NOTE: that only llerr types are used so that the output is
* immediately available.
*/
#ifdef CONFIG_DEBUG_IRQ
# define interr llerr
# define intinfo llinfo
#else
# define interr(x...)
# define intinfo(x...)
#endif
/****************************************************************************
* Private Type Declarations
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
@ -147,7 +129,7 @@ void up_ramvec_initialize(void)
src = (const CODE up_vector_t *)getreg32(NVIC_VECTAB);
dest = g_ram_vectors;
intinfo("src=%p dest=%p\n", src, dest);
irqinfo("src=%p dest=%p\n", src, dest);
for (i = 0; i < ARMV7M_VECTAB_SIZE; i++)
{
@ -163,7 +145,7 @@ void up_ramvec_initialize(void)
* the table alignment is insufficient.
*/
intinfo("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
irqinfo("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
DEBUGASSERT(getreg32(NVIC_VECTAB) == (uint32_t)g_ram_vectors);
}

56
arch/arm/src/efm32/efm32_irq.c
View File

@ -109,44 +109,46 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void efm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
llerr(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 48)
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
llerr(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
#endif
#endif
#endif
leave_critical_section(flags);
}
#else

2
arch/arm/src/imx6/Make.defs
View File

@ -83,7 +83,7 @@ ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
endif
ifeq ($(CONFIG_DEBUG_IRQ),y)
ifeq ($(CONFIG_DEBUG_IRQ_INFO),y)
CMN_CSRCS += arm_gicv2_dump.c
endif

73
arch/arm/src/kinetis/kinetis_irq.c
View File

@ -105,50 +105,51 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void kinetis_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#if NR_VECTORS > 111
llerr(" %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
irqinfo(" %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
#endif
leave_critical_section(flags);

42
arch/arm/src/kl/kl_irq.c
View File

@ -90,34 +90,34 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void kl_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
llerr(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
llerr(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
irqinfo(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
llerr("SYSCON:\n");
llerr(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
llerr(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
llerr(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
llerr(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
irqinfo("SYSCON:\n");
irqinfo(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
irqinfo(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
irqinfo(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}

42
arch/arm/src/lpc11xx/lpc11_irq.c
View File

@ -86,34 +86,34 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void lpc11_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
llerr(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
llerr(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
irqinfo(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
llerr("SYSCON:\n");
llerr(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
llerr(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
llerr(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
llerr(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
irqinfo("SYSCON:\n");
irqinfo(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
irqinfo(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
irqinfo(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}

42
arch/arm/src/lpc17xx/lpc17_irq.c
View File

@ -102,33 +102,35 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void lpc17_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x\n", getreg32(NVIC_IRQ0_31_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" IRQ ENABLE: %08x\n", getreg32(NVIC_IRQ0_31_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
leave_critical_section(flags);
}
#else

50
arch/arm/src/lpc43xx/lpc43_irq.c
View File

@ -107,37 +107,39 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void lpc43_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
llerr(" %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
irqinfo(" IRQ ENABLE: %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
}
#else

42
arch/arm/src/nuc1xx/nuc_irq.c
View File

@ -90,34 +90,34 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void nuc_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
llerr(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
llerr(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
irqinfo(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
llerr("SYSCON:\n");
llerr(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
llerr(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
llerr(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
llerr(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
irqinfo("SYSCON:\n");
irqinfo(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
irqinfo(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
irqinfo(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}

58
arch/arm/src/sam34/sam_irq.c
View File

@ -108,52 +108,54 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if SAM_IRQ_NEXTINT > 15
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 31
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 47
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 63
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 79
# warning Missing logic
#endif
leave_critical_section(flags);
}
#else

66
arch/arm/src/sama5/sam_irq.c
View File

@ -125,13 +125,13 @@ static const uint32_t g_h64mxpids[3] =
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void sam_dumpaic(const char *msg, uintptr_t base, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("AIC (%s, base=%08x irq=%d):\n", msg, base, irq);
irqinfo("AIC (%s, base=%08x irq=%d):\n", msg, base, irq);
/* Select the register set associated with this irq */
@ -139,39 +139,39 @@ static void sam_dumpaic(const char *msg, uintptr_t base, int irq)
/* Then dump all of the (readable) register contents */
llerr(" SSR: %08x SMR: %08x SVR: %08x IVR: %08x\n",
getreg32(base + SAM_AIC_SSR_OFFSET),
getreg32(base + SAM_AIC_SMR_OFFSET),
getreg32(base + SAM_AIC_SVR_OFFSET),
getreg32(base + SAM_AIC_IVR_OFFSET));
llerr(" FVR: %08x ISR: %08x\n",
getreg32(base + SAM_AIC_FVR_OFFSET),
getreg32(base + SAM_AIC_ISR_OFFSET));
llerr(" IPR: %08x %08x %08x %08x\n",
getreg32(base + SAM_AIC_IPR0_OFFSET),
getreg32(base + SAM_AIC_IPR1_OFFSET),
getreg32(base + SAM_AIC_IPR2_OFFSET),
getreg32(base + SAM_AIC_IPR3_OFFSET));
irqinfo(" SSR: %08x SMR: %08x SVR: %08x IVR: %08x\n",
getreg32(base + SAM_AIC_SSR_OFFSET),
getreg32(base + SAM_AIC_SMR_OFFSET),
getreg32(base + SAM_AIC_SVR_OFFSET),
getreg32(base + SAM_AIC_IVR_OFFSET));
irqinfo(" FVR: %08x ISR: %08x\n",
getreg32(base + SAM_AIC_FVR_OFFSET),
getreg32(base + SAM_AIC_ISR_OFFSET));
irqinfo(" IPR: %08x %08x %08x %08x\n",
getreg32(base + SAM_AIC_IPR0_OFFSET),
getreg32(base + SAM_AIC_IPR1_OFFSET),
getreg32(base + SAM_AIC_IPR2_OFFSET),
getreg32(base + SAM_AIC_IPR3_OFFSET));
/* SAMA5D4 does not have the FFSR register */
#if defined(SAM_AIC_FFSR)
llerr(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n",
getreg32(base + SAM_AIC_IMR_OFFSET),
getreg32(base + SAM_AIC_CISR_OFFSET),
getreg32(base + SAM_AIC_SPU_OFFSET),
getreg32(base + SAM_AIC_FFSR_OFFSET));
irqinfo(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n",
getreg32(base + SAM_AIC_IMR_OFFSET),
getreg32(base + SAM_AIC_CISR_OFFSET),
getreg32(base + SAM_AIC_SPU_OFFSET),
getreg32(base + SAM_AIC_FFSR_OFFSET));
#else
llerr(" IMR: %08x CISR: %08x SPU: %08x\n",
getreg32(base + SAM_AIC_IMR_OFFSET),
getreg32(base + SAM_AIC_CISR_OFFSET),
getreg32(base + SAM_AIC_SPU_OFFSET));
irqinfo(" IMR: %08x CISR: %08x SPU: %08x\n",
getreg32(base + SAM_AIC_IMR_OFFSET),
getreg32(base + SAM_AIC_CISR_OFFSET),
getreg32(base + SAM_AIC_SPU_OFFSET));
#endif
llerr(" DCR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(base + SAM_AIC_DCR_OFFSET),
getreg32(base + SAM_AIC_WPMR_OFFSET),
getreg32(base + SAM_AIC_WPSR_OFFSET));
irqinfo(" DCR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(base + SAM_AIC_DCR_OFFSET),
getreg32(base + SAM_AIC_WPMR_OFFSET),
getreg32(base + SAM_AIC_WPSR_OFFSET));
leave_critical_section(flags);
}
@ -234,8 +234,8 @@ static uint32_t *sam_spurious(int irq, uint32_t *regs)
* in this implementation. The value of AIC_IVR is ignored.
*/
#if defined(CONFIG_DEBUG_IRQ)
llerr("Spurious interrupt: IRQ %d\n", irq);
#if defined(CONFIG_DEBUG_IRQ_INFO)
irqinfo("Spurious interrupt: IRQ %d\n", irq);
#endif
return regs;
}
@ -327,12 +327,12 @@ static void sam_aic_redirection(void)
regval |= SFR_AICREDIR_ENABLE;
putreg32(regval, SAM_SFR_AICREDIR);
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
/* Check if redirection was successfully enabled */
regval = getreg32(SAM_SFR_AICREDIR);
llerr("Interrupts %s redirected to the AIC\n",
(regval & SFR_AICREDIR_ENABLE) != 0 ? "ARE" : "NOT");
irqinfo("Interrupts %s redirected to the AIC\n",
(regval & SFR_AICREDIR_ENABLE) != 0 ? "ARE" : "NOT");
#endif
}
}

42
arch/arm/src/samdl/sam_irq.c
View File

@ -299,34 +299,34 @@ void up_ack_irq(int irq)
*
****************************************************************************/
#ifdef CONFIG_DEBUG_IRQ
#ifdef CONFIG_DEBUG_IRQ_INFO
void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
llerr(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
llerr(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
irqinfo(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
llerr("SYSCON:\n");
llerr(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
llerr(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
llerr(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
llerr(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
irqinfo("SYSCON:\n");
irqinfo(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
irqinfo(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
irqinfo(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}

20
arch/arm/src/samdl/sam_irq.h
View File

@ -43,23 +43,7 @@
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Functions
* Public Function Prototypes
************************************************************************************/
/****************************************************************************
@ -70,7 +54,7 @@
*
****************************************************************************/
#ifdef CONFIG_DEBUG_IRQ
#ifdef CONFIG_DEBUG_IRQ_INFO
void sam_dumpnvic(const char *msg, int irq);
#else
# define sam_dumpnvic(msg, irq)

56
arch/arm/src/samv7/sam_irq.c
View File

@ -108,52 +108,54 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void sam_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if SAM_IRQ_NEXTINT > 15
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 31
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 47
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 63
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if SAM_IRQ_NEXTINT > 79
# warning Missing logic
#endif
leave_critical_section(flags);
}
#else

56
arch/arm/src/stm32/stm32_irq.c
View File

@ -107,40 +107,42 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
llerr(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
}
#else

70
arch/arm/src/stm32f7/stm32_irq.c
View File

@ -110,62 +110,64 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if NR_INTERRUPTS > 15
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if NR_INTERRUPTS > 31
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if NR_INTERRUPTS > 47
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if NR_INTERRUPTS > 63
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if NR_INTERRUPTS > 79
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if NR_INTERRUPTS > 95
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if NR_INTERRUPTS > 111
# warning Missing logic
#endif
leave_critical_section(flags);
}
#else

56
arch/arm/src/stm32l4/stm32l4_irq.c
View File

@ -106,40 +106,42 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void stm32l4_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
llerr(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
llerr(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
}
#else

8
arch/arm/src/tiva/Kconfig
View File

@ -783,7 +783,7 @@ config TIVA_I2C_HIGHSPEED
config TIVA_I2C_REGDEBUG
bool "Register level debug"
default n
depends on DEBUG_FEATURES
depends on DEBUG_INFO
---help---
Enables extremely detailed register access debug output.
@ -840,7 +840,7 @@ endif # TIVA_TIMER_16BIT
config TIVA_TIMER_REGDEBUG
bool "Register level debug"
default n
depends on DEBUG_FEATURES
depends on DEBUG_INFO
---help---
Enables extremely detailed register access debug output.
@ -853,7 +853,7 @@ menu "ADC Configuration"
config TIVA_ADC_REGDEBUG
bool "Register level debug"
default n
depends on DEBUG_FEATURES
depends on DEBUG_INFO
---help---
Enables extremely detailed register access debug output.
@ -1103,7 +1103,7 @@ config TIVA_EMAC_HWCHECKSUM
config TIVA_ETHERNET_REGDEBUG
bool "Register-Level Debug"
default n
depends on DEBUG_FEATURES
depends on DEBUG_INFO
---help---
Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES.

68
arch/arm/src/tiva/tiva_irq.c
View File

@ -107,71 +107,71 @@ extern uint32_t _vectors[];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void tiva_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
llerr("NVIC (%s, irq=%d):\n", msg, irq);
llerr(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
llerr(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
#if NR_VECTORS < 64
llerr(" IRQ ENABLE: %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
irqinfo(" IRQ ENABLE: %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
#elif NR_VECTORS < 96
llerr(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
#elif NR_VECTORS < 128
llerr(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
#endif
#if NR_VECTORS > 127
# warning Missing output
#endif
llerr(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
llerr(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#if NR_VECTORS > 47
llerr(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if NR_VECTORS > 63
llerr(" %08x %08x %08x %08x\n",
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if NR_VECTORS > 79
llerr(" %08x %08x %08x %08x\n",
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if NR_VECTORS > 95
llerr(" %08x %08x %08x %08x\n",
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if NR_VECTORS > 111
llerr(" %08x %08x %08x %08x\n",
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY),
getreg32(NVIC_IRQ120_123_PRIORITY), getreg32(NVIC_IRQ124_127_PRIORITY));
#endif

17
arch/arm/src/tiva/tiva_ssi.c
View File

@ -841,7 +841,8 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer,
#endif
int ntxd;
ssierr("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords);
ssiinfo("txbuffer: %p rxbuffer: %p nwords: %d\n",
txbuffer, rxbuffer, nwords);
/* Set up to perform the transfer */
@ -913,7 +914,7 @@ static int ssi_transfer(struct tiva_ssidev_s *priv, const void *txbuffer,
ssi_semtake(&priv->xfrsem);
}
while (priv->nrxwords < priv->nwords);
ssierr("Transfer complete\n");
ssiinfo("Transfer complete\n");
#else
/* Perform the transfer using polling logic. This will totally
@ -1025,7 +1026,7 @@ static int ssi_interrupt(int irq, void *context)
#ifdef CONFIG_DEBUG_SPI
if ((regval & SSI_RIS_ROR) != 0)
{
ssierr("Rx FIFO Overrun!\n");
ssierr("ERROR: Rx FIFO Overrun!\n");
}
#endif
@ -1056,7 +1057,7 @@ static int ssi_interrupt(int irq, void *context)
/* Wake up the waiting thread */
ssierr("Transfer complete\n");
ssiinfo("Transfer complete\n");
ssi_semgive(&priv->xfrsem);
}
@ -1137,7 +1138,7 @@ static uint32_t ssi_setfrequencyinternal(struct tiva_ssidev_s *priv,
uint32_t scr;
uint32_t actual;
ssierr("frequency: %d\n", frequency);
ssiinfo("frequency: %d\n", frequency);
DEBUGASSERT(frequency);
/* Has the frequency changed? */
@ -1261,7 +1262,7 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv, enum spi_mode_e mode
uint32_t modebits;
uint32_t regval;
ssierr("mode: %d\n", mode);
ssiinfo("mode: %d\n", mode);
DEBUGASSERT(priv);
/* Has the number of bits per word changed? */
@ -1340,7 +1341,7 @@ static void ssi_setbitsinternal(struct tiva_ssidev_s *priv, int nbits)
{
uint32_t regval;
ssierr("nbits: %d\n", nbits);
ssiinfo("nbits: %d\n", nbits);
DEBUGASSERT(priv);
if (nbits != priv->nbits && nbits >= 4 && nbits <= 16)
{
@ -1507,7 +1508,7 @@ FAR struct spi_dev_s *tiva_ssibus_initialize(int port)
struct tiva_ssidev_s *priv;
irqstate_t flags;
ssierr("port: %d\n", port);
ssiinfo("port: %d\n", port);
/* Set up for the selected port */

60
arch/arm/src/tiva/tiva_timerlib.c
View File

@ -63,6 +63,10 @@
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_DEBUG_INFO
# undef CONFIG_TIVA_TIMER_REGDEBUG
#endif
/****************************************************************************
* Private Types
****************************************************************************/
@ -393,7 +397,7 @@ static bool tiva_timer_checkreg(struct tiva_gptmstate_s *priv, bool wr,
{
/* Yes... show how many times we did it */
llerr("...[Repeats %d times]...\n", priv->ntimes);
llinfo("...[Repeats %d times]...\n", priv->ntimes);
}
/* Save information about the new access */
@ -426,7 +430,7 @@ static uint32_t tiva_getreg(struct tiva_gptmstate_s *priv, unsigned int offset)
#ifdef CONFIG_TIVA_TIMER_REGDEBUG
if (tiva_timer_checkreg(priv, false, regval, regaddr))
{
llerr("%08x->%08x\n", regaddr, regval);
llinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@ -449,7 +453,7 @@ static void tiva_putreg(struct tiva_gptmstate_s *priv, unsigned int offset,
#ifdef CONFIG_TIVA_TIMER_REGDEBUG
if (tiva_timer_checkreg(priv, true, regval, regaddr))
{
llerr("%08x<-%08x\n", regaddr, regval);
llinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@ -2378,14 +2382,14 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval)
#ifdef CONFIG_TIVA_TIMER_REGDEBUG
/* Generate low-level debug output outside of the critical section */
llerr("%08x<-%08x\n", loadr, interval);
llinfo("%08x<-%08x\n", loadr, interval);
if (toints)
{
# ifdef CONFIG_ARCH_CHIP_TM4C129
llerr("%08x->%08x\n", moder, modev1);
llerr("%08x<-%08x\n", moder, modev2);
llinfo("%08x->%08x\n", moder, modev1);
llinfo("%08x<-%08x\n", moder, modev2);
# endif /* CONFIG_ARCH_CHIP_TM4C129 */
llerr("%08x<-%08x\n", imrr, priv->imr);
llinfo("%08x<-%08x\n", imrr, priv->imr);
}
#endif
}
@ -2525,14 +2529,14 @@ void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx)
#ifdef CONFIG_TIVA_TIMER_REGDEBUG
/* Generate low-level debug output outside of the critical section */
llerr("%08x<-%08x\n", loadr, interval);
llinfo("%08x<-%08x\n", loadr, interval);
if (toints)
{
#ifdef CONFIG_ARCH_CHIP_TM4C129
llerr("%08x->%08x\n", moder, modev1);
llerr("%08x<-%08x\n", moder, modev2);
llinfo("%08x->%08x\n", moder, modev1);
llinfo("%08x<-%08x\n", moder, modev2);
#endif
llerr("%08x<-%08x\n", imrr, priv->imr);
llinfo("%08x<-%08x\n", imrr, priv->imr);
}
#endif
}
@ -2730,13 +2734,13 @@ void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay)
#ifdef CONFIG_TIVA_TIMER_REGDEBUG
/* Generate low-level debug output outside of the critical section */
llerr("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter);
llerr("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match);
llinfo("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter);
llinfo("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match);
#ifdef CONFIG_ARCH_CHIP_TM4C129
llerr("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev);
llerr("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits);
llinfo("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev);
llinfo("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits);
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
llerr("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr);
llinfo("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr);
#endif
}
#endif
@ -2834,13 +2838,13 @@ void tiva_timer32_relmatch(TIMER_HANDLE handle, uint32_t relmatch)
#ifdef CONFIG_TIVA_TIMER_REGDEBUG
/* Generate low-level debug output outside of the critical section */
llerr("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter);
llerr("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match);
llinfo("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter);
llinfo("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match);
#ifdef CONFIG_ARCH_CHIP_TM4C129
llerr("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev);
llerr("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits);
llinfo("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev);
llinfo("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits);
#endif /* CONFIG_ARCH_CHIP_TM4C129 */
llerr("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr);
llinfo("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr);
#endif /* CONFIG_TIVA_TIMER_REGDEBUG */
}
@ -3036,15 +3040,15 @@ void tiva_timer16_relmatch(TIMER_HANDLE handle, uint32_t relmatch, int tmndx)
#ifdef CONFIG_TIVA_TIMER_REGDEBUG
/* Generate low-level debug output outside of the critical section */
llerr("%08x->%08x\n", timerr, timerv);
llerr("%08x->%08x\n", prescr, prescv);
llerr("%08x<-%08x\n", matchr, matchv);
llerr("%08x<-%08x\n", prematchr, prematchv);
llinfo("%08x->%08x\n", timerr, timerv);
llinfo("%08x->%08x\n", prescr, prescv);
llinfo("%08x<-%08x\n", matchr, matchv);
llinfo("%08x<-%08x\n", prematchr, prematchv);
#ifdef CONFIG_ARCH_CHIP_TM4C129
llerr("%08x->%08x\n", adcevr, adcevv);
llerr("%08x<-%08x\n", adcevr, adcevv | adcbits);
llinfo("%08x->%08x\n", adcevr, adcevv);
llinfo("%08x<-%08x\n", adcevr, adcevv | adcbits);
#endif
llerr("%08x<-%08x\n", imr, priv->imr);
llinfo("%08x<-%08x\n", imr, priv->imr);
#endif
}
#endif

70
arch/arm/src/tiva/tm4c_ethernet.c
View File

@ -247,7 +247,7 @@
* enabled.
*/
#ifndef CONFIG_DEBUG_FEATURES
#ifndef CONFIG_DEBUG_INFO
# undef CONFIG_TIVA_ETHERNET_REGDEBUG
#endif
@ -667,7 +667,7 @@ static struct tiva_ethmac_s g_tiva_ethmac[TIVA_NETHCONTROLLERS];
****************************************************************************/
/* Register operations ******************************************************/
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_INFO)
static uint32_t tiva_getreg(uint32_t addr);
static void tiva_putreg(uint32_t val, uint32_t addr);
static void tiva_checksetup(void);
@ -787,7 +787,7 @@ static int tive_emac_configure(FAR struct tiva_ethmac_s *priv);
*
****************************************************************************/
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_INFO)
static uint32_t tiva_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -808,7 +808,7 @@ static uint32_t tiva_getreg(uint32_t addr)
{
if (count == 4)
{
llerr("...\n");
llinfo("...\n");
}
return val;
@ -825,7 +825,7 @@ static uint32_t tiva_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
llerr("[repeats %d more times]\n", count-3);
llinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@ -837,7 +837,7 @@ static uint32_t tiva_getreg(uint32_t addr)
/* Show the register value read */
llerr("%08x->%08x\n", addr, val);
llinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@ -859,12 +859,12 @@ static uint32_t tiva_getreg(uint32_t addr)
*
****************************************************************************/
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_INFO)
static void tiva_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
llerr("%08x<-%08x\n", addr, val);
llinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@ -886,7 +886,7 @@ static void tiva_putreg(uint32_t val, uint32_t addr)
*
****************************************************************************/
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_INFO)
static void tiva_checksetup(void)
{
}
@ -1544,7 +1544,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
if (!tiva_isfreebuffer(priv))
{
nllerr("No free buffers\n");
nllerr("ERROR: No free buffers\n");
return -ENOMEM;
}
@ -1651,7 +1651,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
* scanning logic, and continue scanning with the next frame.
*/
nllerr("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
nllwarn("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
tiva_freesegment(priv, rxcurr, priv->segments);
}
}
@ -1712,7 +1712,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
nllerr("DROPPED: Too big: %d\n", dev->d_len);
nllwarn("DROPPED: Too big: %d\n", dev->d_len);
}
else
@ -1815,7 +1815,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
else
#endif
{
nllerr("DROPPED: Unknown type: %04x\n", BUF->type);
nllwarn("DROPPED: Unknown type: %04x\n", BUF->type);
}
/* We are finished with the RX buffer. NOTE: If the buffer is
@ -2067,7 +2067,7 @@ static inline void tiva_interrupt_process(FAR struct tiva_ethmac_s *priv)
{
/* Just let the user know what happened */
nllerr("Abnormal event(s): %08x\n", dmaris);
nllerr("ERROR: Abnormal event(s): %08x\n", dmaris);
/* Clear all pending abnormal events */
@ -2287,7 +2287,7 @@ static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...)
{
FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg;
nllerr("Timeout!\n");
nllerr("ERROR: Timeout!\n");
#ifdef CONFIG_NET_NOINTS
/* Disable further Ethernet interrupts. This will prevent some race
@ -2488,15 +2488,15 @@ static int tiva_ifup(struct net_driver_s *dev)
int ret;
#ifdef CONFIG_NET_IPv4
nerr("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
ninfo("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
#endif
#ifdef CONFIG_NET_IPv6
nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Configure the Ethernet interface for DMA operation. */
@ -3236,7 +3236,7 @@ static int tiva_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *valu
}
}
nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
phydevaddr, phyregaddr);
return -ETIMEDOUT;
@ -3295,7 +3295,7 @@ static int tiva_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t valu
}
}
nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
phydevaddr, phyregaddr, value);
return -ETIMEDOUT;
@ -3343,7 +3343,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
ret = tiva_phywrite(CONFIG_TIVA_PHYADDR, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
nerr("Failed to reset the PHY: %d\n", ret);
nerr("ERROR: Failed to reset the PHY: %d\n", ret);
return ret;
}
@ -3359,7 +3359,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
ret = tiva_phyread(CONFIG_TIVA_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
nerr("Failed to read the PHY MSR: %d\n", ret);
nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
return ret;
}
else if ((phyval & MII_MSR_LINKSTATUS) != 0)
@ -3370,7 +3370,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
if (timeout >= PHY_RETRY_TIMEOUT)
{
nerr("Timed out waiting for link status: %04x\n", phyval);
nerr("ERROR: Timed out waiting for link status: %04x\n", phyval);
return -ETIMEDOUT;
}
@ -3379,7 +3379,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
ret = tiva_phywrite(CONFIG_TIVA_PHYADDR, MII_MCR, MII_MCR_ANENABLE);
if (ret < 0)
{
nerr("Failed to enable auto-negotiation: %d\n", ret);
nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret);
return ret;
}
@ -3390,7 +3390,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
ret = tiva_phyread(CONFIG_TIVA_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
nerr("Failed to read the PHY MSR: %d\n", ret);
nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
return ret;
}
else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0)
@ -3401,7 +3401,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
if (timeout >= PHY_RETRY_TIMEOUT)
{
nerr("Timed out waiting for auto-negotiation\n");
nerr("ERROR: Timed out waiting for auto-negotiation\n");
return -ETIMEDOUT;
}
@ -3410,7 +3410,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
ret = tiva_phyread(CONFIG_TIVA_PHYADDR, CONFIG_TIVA_PHYSR, &phyval);
if (ret < 0)
{
nerr("Failed to read PHY status register\n");
nerr("ERROR: Failed to read PHY status register\n");
return ret;
}
@ -3480,7 +3480,7 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
ret = tiva_phywrite(CONFIG_TIVA_PHYADDR, MII_MCR, phyval);
if (ret < 0)
{
nerr("Failed to write the PHY MCR: %d\n", ret);
nerr("ERROR: Failed to write the PHY MCR: %d\n", ret);
return ret;
}
up_mdelay(PHY_CONFIG_DELAY);
@ -3495,9 +3495,9 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
#endif
#endif
nerr("Duplex: %s Speed: %d MBps\n",
priv->fduplex ? "FULL" : "HALF",
priv->mbps100 ? 100 : 10);
ninfo("Duplex: %s Speed: %d MBps\n",
priv->fduplex ? "FULL" : "HALF",
priv->mbps100 ? 100 : 10);
return OK;
}

2
arch/arm/src/tms570/tms570_esm.c
View File

@ -155,7 +155,7 @@ int tms570_esm_interrupt(int irq, void *context)
/* Crash -- possibly showing diagnostic debug information. */
llerr("ESM Interrupt. PC: %08x\n", CURRENT_REGS[REG_PC]);
llerr("ERROR: ESM Interrupt. PC: %08x\n", CURRENT_REGS[REG_PC]);
PANIC();
return OK; /* To keep the compiler happy */
}

30
arch/arm/src/tms570/tms570_gio.c
View File

@ -58,7 +58,7 @@
* Private Data
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO
#ifdef CONFIG_DEBUG_GPIO_INFO
static const char g_portchar[TMS570_NPORTS] =
{
'A'
@ -289,15 +289,15 @@ bool tms570_gioread(gio_pinset_t pinset)
*
************************************************************************************/
#ifdef CONFIG_DEBUG_GPIO
#ifdef CONFIG_DEBUG_GPIO_INFO
int tms570_dumpgio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uintptr_t base;
unsigned int port;
llerr("GIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
llinfo("GIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
/* Get the base address associated with the GIO port */
@ -310,20 +310,20 @@ int tms570_dumpgio(uint32_t pinset, const char *msg)
/* Show global GIO registers */
llerr(" GCR0: %08x INTDET: %08x POL: %08x ENA: %08x\n",
getreg32(TMS570_GIO_GCR0), getreg32(TMS570_GIO_INTDET),
getreg32(TMS570_GIO_POL), getreg32(TMS570_GIO_ENASET));
llerr(" LVL: %08x FLG: %08x EMU1: %08x EMU2: %08x\n",
getreg32(TMS570_GIO_LVLSET), getreg32(TMS570_GIO_FLG),
getreg32(TMS570_GIO_EMU1), getreg32(TMS570_GIO_EMU2));
llinfo(" GCR0: %08x INTDET: %08x POL: %08x ENA: %08x\n",
getreg32(TMS570_GIO_GCR0), getreg32(TMS570_GIO_INTDET),
getreg32(TMS570_GIO_POL), getreg32(TMS570_GIO_ENASET));
llinfo(" LVL: %08x FLG: %08x EMU1: %08x EMU2: %08x\n",
getreg32(TMS570_GIO_LVLSET), getreg32(TMS570_GIO_FLG),
getreg32(TMS570_GIO_EMU1), getreg32(TMS570_GIO_EMU2));
/* Port specific registers */
llerr(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n",
getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET),
getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET));
llerr(" PULDIS: %08x PSL: %08x\n",
getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET));
llinfo(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n",
getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET),
getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET));
llinfo(" PULDIS: %08x PSL: %08x\n",
getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET));
leave_critical_section(flags);
return OK;

2
arch/arm/src/tms570/tms570_gio.h
View File

@ -328,7 +328,7 @@ void tms570_gioirqdisable(int irq);
*
************************************************************************************/
#ifdef CONFIG_DEBUG_GPIO
#ifdef CONFIG_DEBUG_GPIO_INFO
int tms570_dumpgio(uint32_t pinset, const char *msg);
#else
# define tms570_dumpgio(p,m)

144
include/debug.h
View File

@ -261,30 +261,6 @@
# define pgllerr(x...)
#endif
#ifdef CONFIG_DEBUG_DMA_ERROR
# define dmaerr(format, ...) err(format, ##__VA_ARGS__)
# define dmallerr(format, ...) llerr(format, ##__VA_ARGS__)
#else
# define dmaerr(x...)
# define dmallerr(x...)
#endif
#ifdef CONFIG_DEBUG_DMA_WARN
# define dmawarn(format, ...) warn(format, ##__VA_ARGS__)
# define dmallwarn(format, ...) llwarn(format, ##__VA_ARGS__)
#else
# define dmawarn(x...)
# define dmallwarn(x...)
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
# define dmainfo(format, ...) info(format, ##__VA_ARGS__)
# define dmallinfo(format, ...) llinfo(format, ##__VA_ARGS__)
#else
# define dmainfo(x...)
# define dmallinfo(x...)
#endif
#ifdef CONFIG_DEBUG_NET_ERROR
# define nerr(format, ...) err(format, ##__VA_ARGS__)
# define nllerr(format, ...) llerr(format, ##__VA_ARGS__)
@ -549,6 +525,54 @@
# define audllinfo(x...)
#endif
#ifdef CONFIG_DEBUG_DMA_ERROR
# define dmaerr(format, ...) err(format, ##__VA_ARGS__)
# define dmallerr(format, ...) llerr(format, ##__VA_ARGS__)
#else
# define dmaerr(x...)
# define dmallerr(x...)
#endif
#ifdef CONFIG_DEBUG_DMA_WARN
# define dmawarn(format, ...) warn(format, ##__VA_ARGS__)
# define dmallwarn(format, ...) llwarn(format, ##__VA_ARGS__)
#else
# define dmawarn(x...)
# define dmallwarn(x...)
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
# define dmainfo(format, ...) info(format, ##__VA_ARGS__)
# define dmallinfo(format, ...) llinfo(format, ##__VA_ARGS__)
#else
# define dmainfo(x...)
# define dmallinfo(x...)
#endif
#ifdef CONFIG_DEBUG_IRQ_ERROR
# define dmaerr(format, ...) err(format, ##__VA_ARGS__)
# define dmallerr(format, ...) llerr(format, ##__VA_ARGS__)
#else
# define dmaerr(x...)
# define dmallerr(x...)
#endif
#ifdef CONFIG_DEBUG_IRQ_WARN
# define irqwarn(format, ...) warn(format, ##__VA_ARGS__)
# define irqllwarn(format, ...) llwarn(format, ##__VA_ARGS__)
#else
# define irqwarn(x...)
# define irqllwarn(x...)
#endif
#ifdef CONFIG_DEBUG_IRQ_INFO
# define irqinfo(format, ...) info(format, ##__VA_ARGS__)
# define irqllinfo(format, ...) llinfo(format, ##__VA_ARGS__)
#else
# define irqinfo(x...)
# define irqllinfo(x...)
#endif
#else /* CONFIG_CPP_HAVE_VARARGS */
/* Variadic macros NOT supported */
@ -658,30 +682,6 @@
# define pgllinfo (void)
#endif
#ifdef CONFIG_DEBUG_DMA_ERROR
# define dmaerr err
# define dmallerr llerr
#else
# define dmaerr (void)
# define dmallerr (void)
#endif
#ifdef CONFIG_DEBUG_DMA_WARN
# define dmawarn warn
# define dmallwarn llwarn
#else
# define dmawarn (void)
# define dmallwarn (void)
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
# define dmainfo info
# define dmallinfo llinfo
#else
# define dmainfo (void)
# define dmallinfo (void)
#endif
#ifdef CONFIG_DEBUG_NET_ERROR
# define nerr err
# define nllerr llerr
@ -946,6 +946,54 @@
# define audllinfo (void)
#endif
#ifdef CONFIG_DEBUG_DMA_ERROR
# define dmaerr err
# define dmallerr llerr
#else
# define dmaerr (void)
# define dmallerr (void)
#endif
#ifdef CONFIG_DEBUG_DMA_WARN
# define dmawarn warn
# define dmallwarn llwarn
#else
# define dmawarn (void)
# define dmallwarn (void)
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
# define dmainfo info
# define dmallinfo llinfo
#else
# define dmainfo (void)
# define dmallinfo (void)
#endif
#ifdef CONFIG_DEBUG_IRQ_ERROR
# define irqerr err
# define irqllerr llerr
#else
# define irqerr (void)
# define irqllerr (void)
#endif
#ifdef CONFIG_DEBUG_IRQ_WARN
# define irqwarn warn
# define irqllwarn llwarn
#else
# define irqwarn (void)
# define irqllwarn (void)
#endif
#ifdef CONFIG_DEBUG_IRQ_INFO
# define irqinfo info
# define irqllinfo llinfo
#else
# define irqinfo (void)
# define irqllinfo (void)
#endif
#endif /* CONFIG_CPP_HAVE_VARARGS */
/* Buffer dumping macros do not depend on varargs */

76
tools/mkconfig.c
View File

@ -184,11 +184,6 @@ int main(int argc, char **argv, char **envp)
printf("# define CONFIG_NFILE_STREAMS 0\n");
printf("#endif\n\n");
printf("/* There must be at least one memory region. */\n\n");
printf("#ifndef CONFIG_MM_REGIONS\n");
printf("# define CONFIG_MM_REGIONS 1\n");
printf("#endif\n\n");
printf("/* If the end of RAM is not specified then it is assumed to be the beginning\n");
printf(" * of RAM plus the RAM size.\n");
printf(" */\n\n");
@ -214,13 +209,6 @@ int main(int argc, char **argv, char **envp)
printf("# define CONFIG_STDIO_BUFFER_SIZE 0\n");
printf("#endif\n\n");
printf("/* If no standard C buffered I/O is not supported, then line-oriented buffering\n");
printf(" * cannot be supported.\n");
printf(" */\n\n");
printf("#if CONFIG_STDIO_BUFFER_SIZE == 0\n");
printf("# undef CONFIG_STDIO_LINEBUFFER\n");
printf("#endif\n\n");
printf("/* If the maximum message size is zero, then we assume that message queues\n");
printf(" * support should be disabled\n");
printf(" */\n\n");
@ -232,19 +220,6 @@ int main(int argc, char **argv, char **envp)
printf("# define CONFIG_DISABLE_MQUEUE 1\n");
printf("#endif\n\n");
printf("/* If mountpoint support in not included, then no filesystem can be supported */\n\n");
printf("#ifdef CONFIG_DISABLE_MOUNTPOINT\n");
printf("# undef CONFIG_FS_BINFS\n");
printf("# undef CONFIG_FS_FAT\n");
printf("# undef CONFIG_FS_HOSTFS\n");
printf("# undef CONFIG_NFS\n");
printf("# undef CONFIG_FS_NXFFS\n");
printf("# undef CONFIG_FS_PROCFS\n");
printf("# undef CONFIG_FS_ROMFS\n");
printf("# undef CONFIG_FS_SMARTFS\n");
printf("# undef CONFIG_FS_TMPFS\n");
printf("#endif\n\n");
printf("/* There can be no network support with no socket descriptors */\n\n");
printf("#if CONFIG_NSOCKET_DESCRIPTORS <= 0\n");
printf("# undef CONFIG_NET\n");
@ -253,59 +228,10 @@ int main(int argc, char **argv, char **envp)
printf(" * socket descriptors\n");
printf(" */\n\n");
printf("#ifndef CONFIG_NET\n");
printf("# undef CONFIG_NSOCKET_DESCRIPTORS\n");
printf("# undef CONFIG_NSOCKET_DESCRIPTORS\n");
printf("# define CONFIG_NSOCKET_DESCRIPTORS 0\n");
printf("#endif\n\n");
printf("/* Protocol support can only be provided on top of basic network support */\n\n");
printf("#ifndef CONFIG_NET\n");
printf("# undef CONFIG_NET_TCP\n");
printf("# undef CONFIG_NET_UDP\n");
printf("# undef CONFIG_NET_ICMP\n");
printf("#endif\n\n");
printf("/* NFS client can only be provided on top of UDP network support */\n\n");
printf("#if !defined(CONFIG_NET) || !defined(CONFIG_NET_UDP)\n");
printf("# undef CONFIG_NFS\n");
printf("#endif\n\n");
printf("/* Verbose debug and sub-system debug only make sense if debug is enabled */\n\n");
printf("#ifndef CONFIG_DEBUG_FEATURES\n");
printf("# undef CONFIG_DEBUG_INFO\n");
printf("# undef CONFIG_DEBUG_ANALOG\n");
printf("# undef CONFIG_DEBUG_AUDIO\n");
printf("# undef CONFIG_DEBUG_BINFMT\n");
printf("# undef CONFIG_DEBUG_CRYPTO\n");
printf("# undef CONFIG_DEBUG_CAN\n");
printf("# undef CONFIG_DEBUG_DMA\n");
printf("# undef CONFIG_DEBUG_FS\n");
printf("# undef CONFIG_DEBUG_GPIO\n");
printf("# undef CONFIG_DEBUG_GRAPHICS\n");
printf("# undef CONFIG_DEBUG_HEAP\n");
printf("# undef CONFIG_DEBUG_I2C\n");
printf("# undef CONFIG_DEBUG_I2S\n");
printf("# undef CONFIG_DEBUG_INPUT\n");
printf("# undef CONFIG_DEBUG_IRQ\n");
printf("# undef CONFIG_DEBUG_LCD\n");
printf("# undef CONFIG_DEBUG_LEDS\n");
printf("# undef CONFIG_DEBUG_LIB\n");
printf("# undef CONFIG_DEBUG_MM\n");
printf("# undef CONFIG_DEBUG_NET\n");
printf("# undef CONFIG_DEBUG_PAGING\n");
printf("# undef CONFIG_DEBUG_PWM\n");
printf("# undef CONFIG_DEBUG_RTC\n");
printf("# undef CONFIG_DEBUG_SCHED\n");
printf("# undef CONFIG_DEBUG_SDIO\n");
printf("# undef CONFIG_DEBUG_SENSORS\n");
printf("# undef CONFIG_DEBUG_SHM\n");
printf("# undef CONFIG_DEBUG_SPI\n");
printf("# undef CONFIG_DEBUG_SYSCALL\n");
printf("# undef CONFIG_DEBUG_TIMER\n");
printf("# undef CONFIG_DEBUG_USB\n");
printf("# undef CONFIG_DEBUG_WATCHDOG\n");
printf("# undef CONFIG_DEBUG_WIRELESS\n");
printf("#endif\n\n");
printf("#endif /* __INCLUDE_NUTTX_CONFIG_H */\n");
fclose(stream);