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SAMA5D4: Bootloader needs to flush D-Cache to memory before disabling the caches

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This commit is contained in:
Gregory Nutt 2014-06-27 14:09:02 -06:00
parent 8c0fb3f9e7
commit c509cd55b2
1 changed files with 12 additions and 1 deletions
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13
configs/sama5d4-ek/src/dram_main.c
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@ -103,6 +103,10 @@ int dram_main(int argc, char *argv)
/* DRAM was already initialized at boot time, so we are ready to load the
* Intel HEX stream into DRAM.
*
* Hmm.. With no hardware handshake, there is a possibility of data loss
* to overruning incoming data buffer. So far I have not seen this at
* 115200 8N1, but still it is a possibility.
*/
printf("Send Intel HEX file now\n");
@ -121,11 +125,18 @@ int dram_main(int argc, char *argv)
for(;;);
}
/* No success indication.. The following cache/MMu operations will clobber
/* No success indication.. The following cache/MMU operations will clobber
* any I/O that we attempt (Hmm.. unless, perhaps, if we delayed. But who
* wants a delay?).
*/
/* Flush the entire data cache assure that everything is in memory before
* we disable caching.
*/
cp15_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION,
(uintptr_t)(SAM_DDRCS_VSECTION + CONFIG_SAMA5_DDRCS_SIZE));
/* Interrupts must be disabled through the following. In this configuration,
* there should only be timer interrupts. Your NuttX configuration must use
* CONFIG_SERIAL_LOWCONSOLE=y or printf() will hang when the interrupts