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arch/arm/src/kinetis: Add PMC register definitions for the K28F.

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This commit is contained in:
Gregory Nutt 2018-05-03 13:38:28 -06:00
parent 0f2b8b0ca2
commit c5a92c883a
8 changed files with 145 additions and 58 deletions
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63
arch/arm/include/kinetis/kinetis_pmc.h
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@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/kinetis/kinetis_pmc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@ -72,6 +72,9 @@
* KINETIS_PMC_HAS_REGSC_BGEN - SoC has REGSC[BGEN]
* KINETIS_PMC_HAS_REGSC_TRAMPO - SoC has REGSC[TRAMPO]
* KINETIS_PMC_HAS_REGSC_REGONS - SoC has REGSC[REGONS]
*
* KINETIS_PMC_HAS_HVDSC1 - SoC has HVDSC1 Register
* KINETIS_PMC_HAS_SRAMCTL - SoC has SRAMCTL Register
*/
/* Describe the version of the PMC
@ -86,6 +89,7 @@
* K20P64M72SF1RM Rev. 1.1, Dec 2012
* K64P144M120SF5RM Rev. 2, January 2014
* K66P144M180SF5RMV2 Rev. 2, May 2015 */
#define KINETIS_PMC_VERSION_05 5 /* Verified to Document Number: K28P210M150SF5RM Rev. 4, August 2017 */
/* MK20DX/DN---VLH5
*
@ -132,19 +136,54 @@
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# undef KINETIS_PMC_HAS_HVDSC1 /* SoC does not have HVDSC1 Register */
# undef KINETIS_PMC_HAS_SRAMCTL /* SoC does not have SRAMCTL Register */
#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
/* MK28FN2M0---15-
*
* --------------- ------- --- ------- ------ ------- ------ -----
* PART NUMBER CPU PIN PACKAGE PROGRAM EEPROM SRAM GPIO
* FREQ CNT FLASH
* --------------- ------- --- ------- ------ ------- ------ -----
* MK28FN2M0VMI15 150 MHz 169 MAPBGA 2 MB None 1 MB 120
* MK28FN2M0CAU15R 150 MHz 210 WLCSP 2 MB None 1 MB 120
* --------------- ------- --- ------- ------ ------- ------ -----
*/
#elif defined(CONFIG_ARCH_CHIP_MK28FN2M0VMI15) || \
defined(CONFIG_ARCH_CHIP_MK28FN2M0CAU15R)
/* Verified to Document Number: Verified to Document Number: K28P210M150SF5RM Rev. 4, August 2017 */
# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_05
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_HVDSC1 1 /* SoC has HVDSC1 Register */
# define KINETIS_PMC_HAS_SRAMCTL 1 /* SoC has SRAMCTL Register */
#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
@ -230,13 +269,16 @@
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# undef KINETIS_PMC_HAS_HVDSC1 /* SoC does not have HVDSC1 Register */
# undef KINETIS_PMC_HAS_SRAMCTL /* SoC does not have SRAMCTL Register */
#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
@ -250,13 +292,16 @@
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# undef KINETIS_PMC_HAS_HVDSC1 /* SoC does not have HVDSC1 Register */
# undef KINETIS_PMC_HAS_SRAMCTL /* SoC does not have SRAMCTL Register */
/* MK66F N/X 1M0/2M0 V MD/LQ 18
*
@ -280,13 +325,16 @@
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# undef KINETIS_PMC_HAS_HVDSC1 /* SoC does not have HVDSC1 Register */
# undef KINETIS_PMC_HAS_SRAMCTL /* SoC does not have SRAMCTL Register */
#else
# error "Unsupported Kinetis chip"
@ -299,13 +347,16 @@
/* PMC Register Configuration */
# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# undef KINETIS_PMC_HAS_REGSC_ACKISO /* SoC has REGSC[ACKISO] */
# define KINETIS_PMC_HAS_REGSC_VLPRS 1 /* SoC has REGSC[VLPRS] */
# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
# define KINETIS_PMC_HAS_REGSC_TRAMPO 1 /* SoC has REGSC[TRAMPO] */
# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
# undef KINETIS_PMC_HAS_HVDSC1 /* SoC does not have HVDSC1 Register */
# undef KINETIS_PMC_HAS_SRAMCTL /* SoC does not have SRAMCTL Register */
#endif

2
arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
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@ -108,7 +108,7 @@
#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
#define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */

2
arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
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@ -115,7 +115,7 @@
#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
#define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */

2
arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
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@ -110,7 +110,7 @@
#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
#define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */

2
arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
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@ -115,7 +115,7 @@
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */

2
arch/arm/src/kinetis/chip/kinetis_k66memorymap.h
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@ -137,7 +137,7 @@
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */
# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */

13
arch/arm/src/kinetis/chip/kinetis_lptmr.h
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@ -57,10 +57,15 @@
/* Register Addresses *******************************************************************************/
#define KINETIS_LPTMR0_CSR (KINETIS_LPTMR_BASE+KINETIS_LPTMR_CSR_OFFSET)
#define KINETIS_LPTMR0_PSR (KINETIS_LPTMR_BASE+KINETIS_LPTMR_PSR_OFFSET)
#define KINETIS_LPTMR0_CMR (KINETIS_LPTMR_BASE+KINETIS_LPTMR_CMR_OFFSET)
#define KINETIS_LPTMR0_CNR (KINETIS_LPTMR_BASE+KINETIS_LPTMR_CNR_OFFSET)
#define KINETIS_LPTMR0_CSR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_CSR_OFFSET)
#define KINETIS_LPTMR0_PSR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_PSR_OFFSET)
#define KINETIS_LPTMR0_CMR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_CMR_OFFSET)
#define KINETIS_LPTMR0_CNR (KINETIS_LPTMR0_BASE+KINETIS_LPTMR_CNR_OFFSET)
#define KINETIS_LPTMR1_CSR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_CSR_OFFSET)
#define KINETIS_LPTMR1_PSR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_PSR_OFFSET)
#define KINETIS_LPTMR1_CMR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_CMR_OFFSET)
#define KINETIS_LPTMR1_CNR (KINETIS_LPTMR1_BASE+KINETIS_LPTMR_CNR_OFFSET)
/* Register Bit Definitions *************************************************************************/

117
arch/arm/src/kinetis/chip/kinetis_pmc.h
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@ -1,7 +1,7 @@
/************************************************************************************
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_pmc.h
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2016, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -31,81 +31,112 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H
/************************************************************************************
/********************************************************************************************
* Included Files
************************************************************************************/
********************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/********************************************************************************************
* Pre-processor Definitions
************************************************************************************/
********************************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *************************************************************************/
#define KINETIS_PMC_LVDSC1_OFFSET 0x0000 /* Low Voltage Detect Status and Control 1 Register */
#define KINETIS_PMC_LVDSC2_OFFSET 0x0001 /* Low Voltage Detect Status and Control 2 Register */
#define KINETIS_PMC_REGSC_OFFSET 0x0002 /* Regulator Status and Control Register */
#define KINETIS_PMC_LVDSC1_OFFSET 0x0000 /* Low Voltage Detect Status and Control 1 Register */
#define KINETIS_PMC_LVDSC2_OFFSET 0x0001 /* Low Voltage Detect Status and Control 2 Register */
#define KINETIS_PMC_REGSC_OFFSET 0x0002 /* Regulator Status and Control Register */
#if defined(KINETIS_PMC_HAS_HVDSC1)
# define KINETIS_PMC_HVDSC1_OFFSET 0x000b /* High Voltage Detect Status And Control 1 register */
#endif
#if defined(KINETIS_PMC_HAS_SRAMCTL)
# define KINETIS_PMC_SRAMCTL_OFFSET 0x000c /* SRAM VLLS2 Control register */
#endif
/* Register Addresses ***************************************************************/
/* Register Addresses ***********************************************************************/
#define KINETIS_PMC_LVDSC1 (KINETIS_PMC_BASE+KINETIS_PMC_LVDSC1_OFFSET)
#define KINETIS_PMC_LVDSC2 (KINETIS_PMC_BASE+KINETIS_PMC_LVDSC2_OFFSET)
#define KINETIS_PMC_REGSC (KINETIS_PMC_BASE+KINETIS_PMC_REGSC_OFFSET)
#define KINETIS_PMC_LVDSC1 (KINETIS_PMC_BASE + KINETIS_PMC_LVDSC1_OFFSET)
#define KINETIS_PMC_LVDSC2 (KINETIS_PMC_BASE + KINETIS_PMC_LVDSC2_OFFSET)
#define KINETIS_PMC_REGSC (KINETIS_PMC_BASE + KINETIS_PMC_REGSC_OFFSET)
#if defined(KINETIS_PMC_HAS_HVDSC1)
# define KINETIS_PMC_HVDSC1 (KINETIS_PMC_BASE + KINETIS_PMC_HVDSC1_OFFSET)
#endif
#if defined(KINETIS_PMC_HAS_SRAMCTL)
# define KINETIS_PMC_SRAMCTL (KINETIS_PMC_BASE + KINETIS_PMC_SRAMCTL_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *****************************************************************/
/* Low Voltage Detect Status and Control 1 Register */
#define PMC_LVDSC1_LVDV_SHIFT (0) /* Bits 0-1: Low-Voltage Detect Voltage Select */
#define PMC_LVDSC1_LVDV_MASK (3 << PMC_LVDSC1_LVDV_SHIFT)
# define PMC_LVDSC1_LVDV_LOW (0 << PMC_LVDSC1_LVDV_SHIFT) /* Low trip point selected (VLVD = VLVDL) */
# define PMC_LVDSC1_LVDV_HIGH (1 << PMC_LVDSC1_LVDV_SHIFT) /* High trip point selected (VLVD = VLVDH) */
/* Bits 2-3: Reserved */
#define PMC_LVDSC1_LVDRE (1 << 4) /* Bit 4: Low-Voltage Detect Reset Enable */
#define PMC_LVDSC1_LVDIE (1 << 5) /* Bit 5: Low-Voltage Detect Interrupt Enable */
#define PMC_LVDSC1_LVDACK (1 << 6) /* Bit 6: Low-Voltage Detect Acknowledge */
#define PMC_LVDSC1_LVDF (1 << 7) /* Bit 7: Low-Voltage Detect Flag */
#define PMC_LVDSC1_LVDV_SHIFT (0) /* Bits 0-1: Low-Voltage Detect Voltage Select */
#define PMC_LVDSC1_LVDV_MASK (3 << PMC_LVDSC1_LVDV_SHIFT)
# define PMC_LVDSC1_LVDV_LOW (0 << PMC_LVDSC1_LVDV_SHIFT) /* Low trip point selected (VLVD = VLVDL) */
# define PMC_LVDSC1_LVDV_HIGH (1 << PMC_LVDSC1_LVDV_SHIFT) /* High trip point selected (VLVD = VLVDH) */
/* Bits 2-3: Reserved */
#define PMC_LVDSC1_LVDRE (1 << 4) /* Bit 4: Low-Voltage Detect Reset Enable */
#define PMC_LVDSC1_LVDIE (1 << 5) /* Bit 5: Low-Voltage Detect Interrupt Enable */
#define PMC_LVDSC1_LVDACK (1 << 6) /* Bit 6: Low-Voltage Detect Acknowledge */
#define PMC_LVDSC1_LVDF (1 << 7) /* Bit 7: Low-Voltage Detect Flag */
/* Low Voltage Detect Status and Control 2 Register */
#define PMC_LVDSC2_LVWV_SHIFT (0) /* Bits 0-1: Low-Voltage Warning Voltage Select */
#define PMC_LVDSC2_LVWV_MASK (3 << PMC_LVDSC2_LVWV_SHIFT)
# define PMC_LVDSC2_LVWV_LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */
# define PMC_LVDSC2_LVWV_MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */
# define PMC_LVDSC2_LVWV_MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */
# define PMC_LVDSC2_LVWV_HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */
/* Bits 2-4: Reserved */
#define PMC_LVDSC2_LVWIE (1 << 5) /* Bit 5: Low-Voltage Warning Interrupt Enable */
#define PMC_LVDSC2_LVWACK (1 << 6) /* Bit 6: Low-Voltage Warning Acknowledge */
#define PMC_LVDSC2_LVWF (1 << 7) /* Bit 7: Low-Voltage Warning Flag */
#define PMC_LVDSC2_LVWV_SHIFT (0) /* Bits 0-1: Low-Voltage Warning Voltage Select */
#define PMC_LVDSC2_LVWV_MASK (3 << PMC_LVDSC2_LVWV_SHIFT)
# define PMC_LVDSC2_LVWV_LOW (0 << PMC_LVDSC2_LVWV_SHIFT) /* Low trip point selected (VLVW = VLVW1H/L) */
# define PMC_LVDSC2_LVWV_MID1 (1 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 1 trip point selected (VLVW = VLVW2H/L) */
# define PMC_LVDSC2_LVWV_MID2 (2 << PMC_LVDSC2_LVWV_SHIFT) /* Mid 2 trip point selected (VLVW = VLVW3H/L) */
# define PMC_LVDSC2_LVWV_HIGH (3 << PMC_LVDSC2_LVWV_SHIFT) /* High trip point selected (VLVW = VLVW4H/L) */
/* Bits 2-4: Reserved */
#define PMC_LVDSC2_LVWIE (1 << 5) /* Bit 5: Low-Voltage Warning Interrupt Enable */
#define PMC_LVDSC2_LVWACK (1 << 6) /* Bit 6: Low-Voltage Warning Acknowledge */
#define PMC_LVDSC2_LVWF (1 << 7) /* Bit 7: Low-Voltage Warning Flag */
/* Regulator Status and Control Register */
#define PMC_REGSC_BGBE (1 << 0) /* Bit 0: Bandgap Buffer Enable */
/* Bit 1: Reserved */
#define PMC_REGSC_BGBE (1 << 0) /* Bit 0: Bandgap Buffer Enable */
/* Bit 1: Reserved */
#if defined(KINETIS_PMC_HAS_REGSC_REGONS)
# define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */
# define PMC_REGSC_REGONS (1 << 2) /* Bit 2: Regulator in Run Regulation Status */
#endif
#if defined(KINETIS_PMC_HAS_REGSC_ACKISO)
# define PMC_REGSC_ACKISO (1 << 3) /* Bit 3: Acknowledge Isolation */
# define PMC_REGSC_ACKISO (1 << 3) /* Bit 3: Acknowledge Isolation */
#endif
#if defined(KINETIS_PMC_HAS_REGSC_VLPRS)
# define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */
# define PMC_REGSC_VLPRS (1 << 3) /* Bit 3: Very Low Power Run Status */
#endif
#if defined(KINETIS_PMC_HAS_REGSC_BGEN)
# define PMC_REGSC_BGEN (1 << 4) /* Bit 4: Bandgap Enable In VLPx Operation */
# define PMC_REGSC_BGEN (1 << 4) /* Bit 4: Bandgap Enable In VLPx Operation */
#endif
#if defined(KINETIS_PMC_HAS_REGSC_TRAMPO)
# define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */
# define PMC_REGSC_TRAMPO (1 << 4) /* Bit 4: For devices with FlexNVM: Traditional RAM Power Option */
#endif
/* Bits 5-7: Reserved */
/* High Voltage Detect Status And Control 1 register */
#if defined(KINETIS_PMC_HAS_HVDSC1)
# define PMC_HVDSC1_HVDV (1 << 0) /* Bit 0: High-Voltage Detect Voltage Select */
/* Bits 1-3: Reserved */
# define PMC_HVDSC1_HVDRE (1 << 4) /* Bit 4: High-Voltage Detect Reset Enable */
# define PMC_HVDSC1_HVDIE (1 << 5) /* Bit 5: High-Voltage Detect Interrupt Enable */
# define PMC_HVDSC1_HVDACK (1 << 6) /* Bit 6: High-Voltage Detect Acknowledge */
# define PMC_HVDSC1_HVDF (1 << 7) /* Bit 7: High-Voltage Detect Flag */
#endif
/* SRAM VLLS2 Control register */
#if defined(KINETIS_PMC_HAS_SRAMCTL)
# define PMC_SRAMCTL_MASK 0xff
# define PMC_SRAMCTL_VLLS2PD (1 << (n)) /* Bits 0-7: SRAM VLLS2 Powerdown */
#endif
/* Bits 5-7: Reserved */
/************************************************************************************
* Public Types