SMP Signals: Fix some SMP signal delivery logic. Was not handling some critical sections correctly and was missing logic to signal tasks running on other CPUs.
This commit is contained in:
Gregory Nutt
parent
fba247b119
commit
c5b00ccfc4
@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/arm_schedulesigaction.c
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*
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* Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013, 2015-2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -51,6 +51,8 @@
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#include "up_internal.h"
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#include "up_arch.h"
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#include "irq/irq.h"
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#ifndef CONFIG_DISABLE_SIGNALS
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/****************************************************************************
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@ -90,6 +92,7 @@
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*
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****************************************************************************/
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#ifndef CONFIG_SMP
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void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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{
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irqstate_t flags;
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@ -105,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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if (!tcb->xcp.sigdeliver)
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{
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/* First, handle some special cases when the signal is being delivered
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* to the currently executing task.
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* to task that is currently executing on this CPU.
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*/
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sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
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@ -153,18 +156,6 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
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CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
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#ifdef CONFIG_SMP
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/* In an SMP configuration, the interrupt disable logic also
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* involves spinlocks that are configured per the TCB irqcount
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* field. This is logically equivalent to enter_critical_section().
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* The matching call to leave_critical_section() will be
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* performed in up_sigdeliver().
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*/
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DEBUGASSERT(tcb->irqcount < INT16_MAX);
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tcb->irqcount++;
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#endif
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/* And make sure that the saved context in the TCB is the same
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* as the interrupt return context.
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*/
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@ -175,7 +166,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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/* Otherwise, we are (1) signaling a task is not running from an
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* interrupt handler or (2) we are not in an interrupt handler and the
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* running task is signalling some non-running task.
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* running task is signalling some other non-running task.
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*/
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else
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@ -195,23 +186,175 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
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tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
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#ifdef CONFIG_SMP
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/* In an SMP configuration, the interrupt disable logic also
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* involves spinlocks that are configured per the TCB irqcount
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* field. This is logically equivalent to enter_critical_section();
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* The matching leave_critical_section will be performed in
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* The matching call to leave_critical_section() will be performed
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* in up_sigdeliver().
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*/
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DEBUGASSERT(tcb->irqcount < INT16_MAX);
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tcb->irqcount++;
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#endif
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}
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}
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leave_critical_section(flags);
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}
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#endif /* !CONFIG_SMP */
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#ifdef CONFIG_SMP
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void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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{
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irqstate_t flags;
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int cpu;
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int me;
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sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
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/* Make sure that interrupts are disabled */
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flags = enter_critical_section();
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/* Refuse to handle nested signal actions */
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if (!tcb->xcp.sigdeliver)
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{
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/* First, handle some special cases when the signal is being delivered
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* to task that is currently executing on any CPU.
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*/
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sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
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me = this_cpu();
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cpu = tcb->cpu;
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if (tcb->task_state == TSTATE_TASK_RUNNING)
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{
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/* CASE 1: We are not in an interrupt handler and a task is
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* signalling itself for some reason.
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*/
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if (cpu == me && !CURRENT_REGS)
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{
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/* In this case just deliver the signal now. */
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sigdeliver(tcb);
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}
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/* CASE 2: The task that needs to receive the signal is running.
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* This could happen if the task is running on another CPU OR if
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* we are in an interrupt handler and the task is running on this
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* CPU. In the former case, we will have to PAUSE the other CPU
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* first. But in either case, we will have to modify the return
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* state as well as the state in the TCB.
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*
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* Hmmm... there looks like a latent bug here: The following logic
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* would fail in the strange case where we are in an interrupt
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* handler, the thread is signalling itself, but a context switch
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* to another task has occurred so that CURRENT_REGS does not
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* refer to the thread of this_task()!
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*/
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else
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{
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/* If we signalling a task running on the other CPU, we have
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* to PAUSE the other CPU.
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*/
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if (cpu != me)
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{
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up_cpu_pause(cpu);
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}
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/* Save the return lr and cpsr and one scratch register
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* These will be restored by the signal trampoline after
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* the signals have been delivered.
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*/
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tcb->xcp.sigdeliver = sigdeliver;
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tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
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tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
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/* Increment the IRQ lock count so that when the task is restarted,
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* it will hold the IRQ spinlock.
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*/
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DEBUGASSERT(tcb->irqcount < INT16_MAX);
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tcb->irqcount++;
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/* Handle a possible race condition where the TCB was suspended
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* just before we paused the other CPU.
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*/
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if (tcb->task_state != TSTATE_TASK_RUNNING)
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{
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/* Then set up to vector to the trampoline with interrupts
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* disabled
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*/
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tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
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tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
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}
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else
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{
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/* Then set up to vector to the trampoline with interrupts
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* disabled
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*/
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CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
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CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
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/* In an SMP configuration, the interrupt disable logic also
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* involves spinlocks that are configured per the TCB irqcount
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* field. This is logically equivalent to enter_critical_section().
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* The matching call to leave_critical_section() will be
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* performed in up_sigdeliver().
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*/
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spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
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&g_cpu_irqlock);
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/* And make sure that the saved context in the TCB is the same
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* as the interrupt return context.
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*/
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up_savestate(tcb->xcp.regs);
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}
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/* RESUME the other CPU if it was PAUSED */
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if (cpu != me)
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{
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up_cpu_pause(cpu);
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}
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}
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}
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/* Otherwise, we are (1) signaling a task is not running from an
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* interrupt handler or (2) we are not in an interrupt handler and the
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* running task is signalling some other non-running task.
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*/
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else
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{
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/* Save the return lr and cpsr and one scratch register. These
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* will be restored by the signal trampoline after the signals
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* have been delivered.
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*/
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tcb->xcp.sigdeliver = sigdeliver;
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tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
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tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
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/* Increment the IRQ lock count so that when the task is restarted,
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* it will hold the IRQ spinlock.
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*/
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DEBUGASSERT(tcb->irqcount < INT16_MAX);
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tcb->irqcount++;
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/* Then set up to vector to the trampoline with interrupts
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* disabled
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*/
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tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
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tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
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}
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}
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leave_critical_section(flags);
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}
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#endif /* CONFIG_SMP */
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#endif /* !CONFIG_DISABLE_SIGNALS */
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/armv7-m/up_schedulesigaction.c
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*
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* Copyright (C) 2009-2014, 2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2014, 2016-2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -52,6 +52,8 @@
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#include "up_internal.h"
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#include "up_arch.h"
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#include "irq/irq.h"
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#ifndef CONFIG_DISABLE_SIGNALS
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/****************************************************************************
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@ -91,6 +93,7 @@
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*
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****************************************************************************/
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#ifndef CONFIG_SMP
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void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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{
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irqstate_t flags;
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@ -165,19 +168,6 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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#ifdef CONFIG_BUILD_PROTECTED
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CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR;
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#endif
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#ifdef CONFIG_SMP
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/* In an SMP configuration, the interrupt disable logic also
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* involves spinlocks that are configured per the TCB irqcount
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* field. This is logically equivalent to enter_critical_section().
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* The matching call to leave_critical_section() will be
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* performed in up_sigdeliver().
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*/
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DEBUGASSERT(tcb->irqcount < INT16_MAX);
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tcb->irqcount++;
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#endif
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/* And make sure that the saved context in the TCB is the same
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* as the interrupt return context.
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*/
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@ -224,23 +214,215 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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#ifdef CONFIG_BUILD_PROTECTED
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tcb->xcp.regs[REG_LR] = EXC_RETURN_PRIVTHR;
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#endif
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}
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}
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leave_critical_section(flags);
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}
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#endif /* !CONFIG_SMP */
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#ifdef CONFIG_SMP
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/* In an SMP configuration, the interrupt disable logic also
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* involves spinlocks that are configured per the TCB irqcount
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* field. This is logically equivalent to enter_critical_section();
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* The matching leave_critical_section will be performed in
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* The matching call to leave_critical_section() will be performed
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* in up_sigdeliver().
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void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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{
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irqstate_t flags;
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int cpu;
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int me;
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sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
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/* Make sure that interrupts are disabled */
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flags = enter_critical_section();
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/* Refuse to handle nested signal actions */
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if (!tcb->xcp.sigdeliver)
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{
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/* First, handle some special cases when the signal is being delivered
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* to task that is currently executing on any CPU.
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*/
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sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
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me = this_cpu();
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cpu = tcb->cpu;
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if (tcb->task_state == TSTATE_TASK_RUNNING)
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{
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/* CASE 1: We are not in an interrupt handler and a task is
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* signalling itself for some reason.
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*/
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if (cpu == me && !CURRENT_REGS)
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{
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/* In this case just deliver the signal now. */
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sigdeliver(tcb);
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}
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/* CASE 2: The task that needs to receive the signal is running.
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* This could happen if the task is running on another CPU OR if
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* we are in an interrupt handler and the task is running on this
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* CPU. In the former case, we will have to PAUSE the other CPU
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* first. But in either case, we will have to modify the return
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* state as well as the state in the TCB.
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*
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* Hmmm... there looks like a latent bug here: The following logic
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* would fail in the strange case where we are in an interrupt
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* handler, the thread is signalling itself, but a context switch
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* to another task has occurred so that CURRENT_REGS does not
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* refer to the thread of this_task()!
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*/
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else
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{
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/* If we signalling a task running on the other CPU, we have
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* to PAUSE the other CPU.
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*/
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if (cpu != me)
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{
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up_cpu_pause(cpu);
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}
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/* Save the return PC, CPSR and either the BASEPRI or PRIMASK
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* registers (and perhaps also the LR). These will be
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* restored by the signal trampoline after the signal has been
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* delivered.
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*/
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tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
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tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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tcb->xcp.saved_basepri = CURRENT_REGS[REG_BASEPRI];
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#else
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tcb->xcp.saved_primask = CURRENT_REGS[REG_PRIMASK];
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#endif
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tcb->xcp.saved_xpsr = CURRENT_REGS[REG_XPSR];
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#ifdef CONFIG_BUILD_PROTECTED
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tcb->xcp.saved_lr = CURRENT_REGS[REG_LR];
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#endif
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/* Increment the IRQ lock count so that when the task is restarted,
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* it will hold the IRQ spinlock.
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*/
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DEBUGASSERT(tcb->irqcount < INT16_MAX);
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tcb->irqcount++;
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/* Handle a possible race condition where the TCB was suspended
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* just before we paused the other CPU.
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*/
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if (tcb->task_state != TSTATE_TASK_RUNNING)
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{
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/* Then set up to vector to the trampoline with interrupts
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* disabled. We must already be in privileged thread mode
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* to be here.
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*/
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tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
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#else
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tcb->xcp.regs[REG_PRIMASK] = 1;
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#endif
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tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T;
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#ifdef CONFIG_BUILD_PROTECTED
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tcb->xcp.regs[REG_LR] = EXC_RETURN_PRIVTHR;
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#endif
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}
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else
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{
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/* Then set up to vector to the trampoline with interrupts
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* disabled
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*/
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CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
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#else
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CURRENT_REGS[REG_PRIMASK] = 1;
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#endif
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CURRENT_REGS[REG_XPSR] = ARMV7M_XPSR_T;
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#ifdef CONFIG_BUILD_PROTECTED
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CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR;
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#endif
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/* In an SMP configuration, the interrupt disable logic also
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* involves spinlocks that are configured per the TCB irqcount
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* field. This is logically equivalent to enter_critical_section().
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* The matching call to leave_critical_section() will be
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* performed in up_sigdeliver().
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*/
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spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
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&g_cpu_irqlock);
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/* And make sure that the saved context in the TCB is the same
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* as the interrupt return context.
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*/
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up_savestate(tcb->xcp.regs);
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}
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/* RESUME the other CPU if it was PAUSED */
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if (cpu != me)
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{
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up_cpu_pause(cpu);
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}
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}
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}
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/* Otherwise, we are (1) signaling a task is not running from an
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* interrupt handler or (2) we are not in an interrupt handler and the
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* running task is signalling some other non-running task.
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*/
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else
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{
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/* Save the return PC, CPSR and either the BASEPRI or PRIMASK
|
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* registers (and perhaps also the LR). These will be restored
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* by the signal trampoline after the signal has been delivered.
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*/
|
||||
|
||||
tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
|
||||
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
tcb->xcp.saved_basepri = tcb->xcp.regs[REG_BASEPRI];
|
||||
#else
|
||||
tcb->xcp.saved_primask = tcb->xcp.regs[REG_PRIMASK];
|
||||
#endif
|
||||
tcb->xcp.saved_xpsr = tcb->xcp.regs[REG_XPSR];
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
tcb->xcp.saved_lr = tcb->xcp.regs[REG_LR];
|
||||
#endif
|
||||
/* Increment the IRQ lock count so that when the task is restarted,
|
||||
* it will hold the IRQ spinlock.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(tcb->irqcount < INT16_MAX);
|
||||
tcb->irqcount++;
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled. We must already be in privileged thread mode to be
|
||||
* here.
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
|
||||
#else
|
||||
tcb->xcp.regs[REG_PRIMASK] = 1;
|
||||
#endif
|
||||
tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T;
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
tcb->xcp.regs[REG_LR] = EXC_RETURN_PRIVTHR;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#endif /* !CONFIG_DISABLE_SIGNALS */
|
||||
|
||||
@ -54,18 +54,6 @@
|
||||
|
||||
#ifndef CONFIG_DISABLE_SIGNALS
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/common/arm_schedulesigaction.c
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -49,6 +49,8 @@
|
||||
#include "sched/sched.h"
|
||||
#include "xtensa.h"
|
||||
|
||||
#include "irq/irq.h"
|
||||
|
||||
#ifndef CONFIG_DISABLE_SIGNALS
|
||||
|
||||
/****************************************************************************
|
||||
@ -88,6 +90,7 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
{
|
||||
irqstate_t flags;
|
||||
@ -135,9 +138,8 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
|
||||
else
|
||||
{
|
||||
/* Save the return lr and cpsr and one scratch register
|
||||
* These will be restored by the signal trampoline after
|
||||
* the signals have been delivered.
|
||||
/* Save the return pc and ps. These will be restored by the
|
||||
* signal trampoline after the signals have been delivered.
|
||||
*
|
||||
* NOTE: that hi-priority interrupts are not disabled.
|
||||
*/
|
||||
@ -172,29 +174,204 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
|
||||
else
|
||||
{
|
||||
/* Save the return lr and cpsr and one scratch register. These
|
||||
* will be restored by the signal trampoline after the signals
|
||||
* have been delivered.
|
||||
/* Save the return pc and ps. These will be restored by the
|
||||
* signal trampoline after the signals have been delivered.
|
||||
*
|
||||
* NOTE: that hi-priority interrupts are not disabled.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
|
||||
tcb->xcp.saved_ps = tcb->xcp.regs[REG_PS];
|
||||
tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
|
||||
tcb->xcp.saved_ps = CURRENT_REGS[REG_PS];
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
|
||||
#else
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* !CONFIG_SMP */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int cpu;
|
||||
int me;
|
||||
|
||||
sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
|
||||
|
||||
/* Make sure that interrupts are disabled */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Refuse to handle nested signal actions */
|
||||
|
||||
if (!tcb->xcp.sigdeliver)
|
||||
{
|
||||
/* First, handle some special cases when the signal is being delivered
|
||||
* to task that is currently executing on any CPU.
|
||||
*/
|
||||
|
||||
sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
|
||||
|
||||
me = this_cpu();
|
||||
cpu = tcb->cpu;
|
||||
|
||||
if (tcb->task_state == TSTATE_TASK_RUNNING)
|
||||
{
|
||||
/* CASE 1: We are not in an interrupt handler and a task is
|
||||
* signalling itself for some reason.
|
||||
*/
|
||||
|
||||
if (cpu == me && !CURRENT_REGS)
|
||||
{
|
||||
/* In this case just deliver the signal now. */
|
||||
|
||||
sigdeliver(tcb);
|
||||
}
|
||||
|
||||
/* CASE 2: The task that needs to receive the signal is running.
|
||||
* This could happen if the task is running on another CPU OR if
|
||||
* we are in an interrupt handler and the task is running on this
|
||||
* CPU. In the former case, we will have to PAUSE the other CPU
|
||||
* first. But in either case, we will have to modify the return
|
||||
* state as well as the state in the TCB.
|
||||
*
|
||||
* Hmmm... there looks like a latent bug here: The following logic
|
||||
* would fail in the strange case where we are in an interrupt
|
||||
* handler, the thread is signalling itself, but a context switch
|
||||
* to another task has occurred so that CURRENT_REGS does not
|
||||
* refer to the thread of this_task()!
|
||||
*/
|
||||
|
||||
else
|
||||
{
|
||||
/* If we signalling a task running on the other CPU, we have
|
||||
* to PAUSE the other CPU.
|
||||
*/
|
||||
|
||||
if (cpu != me)
|
||||
{
|
||||
up_cpu_pause(cpu);
|
||||
}
|
||||
|
||||
/* Save the return pc and ps. These will be restored by the
|
||||
* signal trampoline after the signals have been delivered.
|
||||
*
|
||||
* NOTE: that hi-priority interrupts are not disabled.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
|
||||
tcb->xcp.saved_ps = CURRENT_REGS[REG_PS];
|
||||
|
||||
/* Increment the IRQ lock count so that when the task is restarted,
|
||||
* it will hold the IRQ spinlock.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(tcb->irqcount < INT16_MAX);
|
||||
tcb->irqcount++;
|
||||
|
||||
/* Handle a possible race condition where the TCB was suspended
|
||||
* just before we paused the other CPU.
|
||||
*/
|
||||
|
||||
if (tcb->task_state != TSTATE_TASK_RUNNING)
|
||||
{
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
|
||||
#else
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
|
||||
#else
|
||||
CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
|
||||
#endif
|
||||
/* In an SMP configuration, the interrupt disable logic also
|
||||
* involves spinlocks that are configured per the TCB irqcount
|
||||
* field. This is logically equivalent to enter_critical_section().
|
||||
* The matching call to leave_critical_section() will be
|
||||
* performed in up_sigdeliver().
|
||||
*/
|
||||
|
||||
spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
|
||||
&g_cpu_irqlock);
|
||||
|
||||
/* And make sure that the saved context in the TCB is the same
|
||||
* as the interrupt return context.
|
||||
*/
|
||||
|
||||
xtensa_savestate(tcb->xcp.regs);
|
||||
}
|
||||
|
||||
/* RESUME the other CPU if it was PAUSED */
|
||||
|
||||
if (cpu != me)
|
||||
{
|
||||
up_cpu_pause(cpu);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Otherwise, we are (1) signaling a task is not running from an
|
||||
* interrupt handler or (2) we are not in an interrupt handler and the
|
||||
* running task is signalling some other non-running task.
|
||||
*/
|
||||
|
||||
else
|
||||
{
|
||||
/* Save the return pc and ps. These will be restored by the
|
||||
* signal trampoline after the signals have been delivered.
|
||||
*
|
||||
* NOTE: that hi-priority interrupts are not disabled.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
|
||||
tcb->xcp.saved_ps = CURRENT_REGS[REG_PS];
|
||||
|
||||
/* Increment the IRQ lock count so that when the task is restarted,
|
||||
* it will hold the IRQ spinlock.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(tcb->irqcount < INT16_MAX);
|
||||
tcb->irqcount++;
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)_xtensa_sig_trampoline;
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
|
||||
#else
|
||||
tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#endif /* !CONFIG_DISABLE_SIGNALS */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user