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Merge remote-tracking branch 'origin/master' into ieee802154

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This commit is contained in:
Gregory Nutt 2017-04-24 17:34:35 -06:00
commit c5e636ad84
17 changed files with 106 additions and 48 deletions
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2
arch/arm/src/common/up_udelay.c
View File

@ -59,7 +59,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/arm/src/lpc11xx/Kconfig
View File

@ -222,7 +222,7 @@ config CAN_SAM
The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line).
config CAN_LOOPBACK
bool "CAN looopback mode"
bool "CAN loopback mode"
default n
---help---
Enable CAN loopback mode

2
arch/arm/src/lpc17xx/Kconfig
View File

@ -589,7 +589,7 @@ config CAN_SAM
The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line).
config CAN_LOOPBACK
bool "CAN looopback mode"
bool "CAN loopback mode"
default n
---help---
Enable CAN loopback mode

36
arch/arm/src/sam34/Kconfig
View File

@ -572,7 +572,6 @@ config SAM34_TWIS
bool
default n
config SAM34_TWIM0
bool "Two-wire Master Interface 0 (TWIM0)"
default n
@ -1142,6 +1141,41 @@ config SAM34_SPI_REGDEBUG
endmenu # AT91SAM3/4 SPI device driver options
endif # SAM34_SPI0 || SAM34_SPI1
if SAM34_TWIM
menu "AT91SAM3/4 TWI master device driver options"
config SAM34_TWIM0_FREQUENCY
int "TWI0 Frequency"
default 100000
depends on SAM34_TWIM0
config SAM34_TWIM1_FREQUENCY
int "TWI1 Frequency"
default 100000
depends on SAM34_TWIM1
config SAM34_TWIM2_FREQUENCY
int "TWI2 Frequency"
default 100000
depends on SAM34_TWIM2
config SAM34_TWIM3_FREQUENCY
int "TWI3 Frequency"
default 100000
depends on SAM34_TWIM3
config SAM34_TWI_REGDEBUG
bool "TWI register level debug"
depends on DEBUG_I2C_INFO
default n
---help---
Output detailed register-level TWI device debug information.
Very invasive! Requires also CONFIG_DEBUG_I2C_INFO.
endmenu # TWI device driver options
endif # SAM34_TWIM
menu "AT91SAM3/4 EMAC device driver options"
depends on SAM34_EMAC

30
arch/arm/src/sam34/sam_twi.c
View File

@ -71,19 +71,21 @@
#include "sam_gpio.h"
#include "sam_twi.h"
#if defined(CONFIG_SAM34_TWI0) || defined(CONFIG_SAM34_TWI1)
/* REVISIT: Missing support for TWI2 master */
#if defined(CONFIG_SAM34_TWIM0) || defined(CONFIG_SAM34_TWIM1)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
#ifndef CONFIG_SAM34_TWI0_FREQUENCY
# define CONFIG_SAM34_TWI0_FREQUENCY 100000
#ifndef CONFIG_SAM34_TWIM0_FREQUENCY
# define CONFIG_SAM34_TWIM0_FREQUENCY 100000
#endif
#ifndef CONFIG_SAM34_TWI1_FREQUENCY
# define CONFIG_SAM34_TWI1_FREQUENCY 100000
#ifndef CONFIG_SAM34_TWIM1_FREQUENCY
# define CONFIG_SAM34_TWIM1_FREQUENCY 100000
#endif
#ifndef CONFIG_DEBUG_I2C_INFO
@ -187,11 +189,11 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
* Private Data
****************************************************************************/
#ifdef CONFIG_SAM34_TWI0
#ifdef CONFIG_SAM34_TWIM0
static struct twi_dev_s g_twi0;
#endif
#ifdef CONFIG_SAM34_TWI1
#ifdef CONFIG_SAM34_TWIM1
static struct twi_dev_s g_twi1;
#endif
@ -430,7 +432,7 @@ static void twi_wakeup(struct twi_dev_s *priv, int result)
*
****************************************************************************/
static int twi_interrupt(int irq, FAR void *context, FAR void *arg);
static int twi_interrupt(int irq, FAR void *context, FAR void *arg)
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
struct i2c_msg_s *msg;
@ -901,7 +903,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
flags = enter_critical_section();
#ifdef CONFIG_SAM34_TWI0
#ifdef CONFIG_SAM34_TWIM0
if (bus == 0)
{
/* Set up TWI0 register base address and IRQ number */
@ -922,18 +924,18 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Select the TWI frequency, and peripheral ID */
frequency = CONFIG_SAM34_TWI0_FREQUENCY;
frequency = CONFIG_SAM34_TWIM0_FREQUENCY;
pid = SAM_PID_TWI0;
}
else
#endif
#ifdef CONFIG_SAM34_TWI1
#ifdef CONFIG_SAM34_TWIM1
if (bus == 1)
{
/* Set up TWI1 register base address and IRQ number */
priv = &g_twi1;
priv->base = SAM_TWI0_BASE;
priv->base = SAM_TWI1_BASE;
priv->irq = SAM_IRQ_TWI1;
priv->twi = 1;
@ -948,7 +950,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Select the TWI frequency, and peripheral ID */
frequency = CONFIG_SAMA5_TWI1_FREQUENCY;
frequency = CONFIG_SAM34_TWIM1_FREQUENCY;
pid = SAM_PID_TWI1;
}
else
@ -1029,4 +1031,4 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
return OK;
}
#endif /* CONFIG_SAM34_TWI0 || CONFIG_SAM34_TWI1 */
#endif /* CONFIG_SAM34_TWIM0 || CONFIG_SAM34_TWIM1 */

2
arch/avr/src/common/up_udelay.c
View File

@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/hc/src/common/up_udelay.c
View File

@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/mips/src/common/up_udelay.c
View File

@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/misoc/src/common/misoc_udelay.c
View File

@ -59,7 +59,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/renesas/src/common/up_udelay.c
View File

@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/x86/src/common/up_udelay.c
View File

@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/xtensa/src/common/xtensa_udelay.c
View File

@ -59,7 +59,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/z16/src/common/up_udelay.c
View File

@ -77,7 +77,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

2
arch/z80/src/common/up_udelay.c
View File

@ -77,7 +77,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***

40
drivers/usbdev/usbmsc_scsi.c
View File

@ -508,7 +508,7 @@ static inline int usbmsc_cmdrequestsense(FAR struct usbmsc_dev_s *priv,
static inline int usbmsc_cmdread6(FAR struct usbmsc_dev_s *priv)
{
FAR struct scsicmd_read6_s *read6 = (FAR struct scsicmd_read6_s *)priv->cdb;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.xfrlen = (uint16_t)read6->xfrlen;
@ -521,6 +521,8 @@ static inline int usbmsc_cmdread6(FAR struct usbmsc_dev_s *priv)
USBMSC_FLAGS_DIRDEVICE2HOST | USBMSC_FLAGS_BLOCKXFR);
if (ret == OK)
{
lun = priv->lun;
/* Get the Logical Block Address (LBA) from cdb[] as the starting sector */
priv->sector = (uint32_t)(read6->mslba & SCSICMD_READ6_MSLBAMASK) << 16 |
@ -568,7 +570,7 @@ static inline int usbmsc_cmdread6(FAR struct usbmsc_dev_s *priv)
static inline int usbmsc_cmdwrite6(FAR struct usbmsc_dev_s *priv)
{
FAR struct scsicmd_write6_s *write6 = (FAR struct scsicmd_write6_s *)priv->cdb;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.xfrlen = (uint16_t)write6->xfrlen;
@ -581,6 +583,8 @@ static inline int usbmsc_cmdwrite6(FAR struct usbmsc_dev_s *priv)
USBMSC_FLAGS_DIRHOST2DEVICE | USBMSC_FLAGS_BLOCKXFR);
if (ret == OK)
{
lun = priv->lun;
/* Get the Logical Block Address (LBA) from cdb[] as the starting sector */
priv->sector = (uint32_t)(write6->mslba & SCSICMD_WRITE6_MSLBAMASK) << 16 | (uint32_t)usbmsc_getbe16(write6->lslba);
@ -880,7 +884,7 @@ static inline int usbmsc_cmdpreventmediumremoval(FAR struct usbmsc_dev_s *priv)
#ifdef CONFIG_USBMSC_REMOVABLE
FAR struct scsicmd_preventmediumremoval_s *pmr = (FAR struct scsicmd_preventmediumremoval_s *)priv->cdb;
#endif
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.alloclen = 0;
@ -888,6 +892,8 @@ static inline int usbmsc_cmdpreventmediumremoval(FAR struct usbmsc_dev_s *priv)
USBMSC_FLAGS_DIRNONE);
if (ret == OK)
{
lun = priv->lun;
#ifndef CONFIG_USBMSC_REMOVABLE
lun->sd = SCSI_KCQIR_INVALIDCOMMAND;
ret = -EINVAL;
@ -919,7 +925,7 @@ static inline int usbmsc_cmdreadformatcapacity(FAR struct usbmsc_dev_s *priv,
{
FAR struct scsicmd_readformatcapcacities_s *rfc = (FAR struct scsicmd_readformatcapcacities_s *)priv->cdb;
FAR struct scsiresp_readformatcapacities_s *hdr;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.alloclen = usbmsc_getbe16(rfc->alloclen);
@ -927,6 +933,8 @@ static inline int usbmsc_cmdreadformatcapacity(FAR struct usbmsc_dev_s *priv,
USBMSC_FLAGS_DIRDEVICE2HOST);
if (ret == OK)
{
lun = priv->lun;
hdr = (FAR struct scsiresp_readformatcapacities_s *)buf;
memset(hdr, 0, SCSIRESP_READFORMATCAPACITIES_SIZEOF);
hdr->listlen = SCSIRESP_CURRCAPACITYDESC_SIZEOF;
@ -955,7 +963,7 @@ static int inline usbmsc_cmdreadcapacity10(FAR struct usbmsc_dev_s *priv,
{
FAR struct scsicmd_readcapacity10_s *rcc = (FAR struct scsicmd_readcapacity10_s *)priv->cdb;
FAR struct scsiresp_readcapacity10_s *rcr = (FAR struct scsiresp_readcapacity10_s *)buf;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
uint32_t lba;
int ret;
@ -964,6 +972,8 @@ static int inline usbmsc_cmdreadcapacity10(FAR struct usbmsc_dev_s *priv,
USBMSC_FLAGS_DIRDEVICE2HOST);
if (ret == OK)
{
lun = priv->lun;
/* Check the PMI and LBA fields */
lba = usbmsc_getbe32(rcc->lba);
@ -996,7 +1006,7 @@ static int inline usbmsc_cmdreadcapacity10(FAR struct usbmsc_dev_s *priv,
static inline int usbmsc_cmdread10(FAR struct usbmsc_dev_s *priv)
{
struct scsicmd_read10_s *read10 = (struct scsicmd_read10_s *)priv->cdb;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.xfrlen = usbmsc_getbe16(read10->xfrlen);
@ -1004,6 +1014,8 @@ static inline int usbmsc_cmdread10(FAR struct usbmsc_dev_s *priv)
USBMSC_FLAGS_DIRDEVICE2HOST | USBMSC_FLAGS_BLOCKXFR);
if (ret == OK)
{
lun = priv->lun;
/* Get the Logical Block Address (LBA) from cdb[] as the starting sector */
priv->sector = usbmsc_getbe32(read10->lba);
@ -1058,7 +1070,7 @@ static inline int usbmsc_cmdread10(FAR struct usbmsc_dev_s *priv)
static inline int usbmsc_cmdwrite10(FAR struct usbmsc_dev_s *priv)
{
struct scsicmd_write10_s *write10 = (struct scsicmd_write10_s *)priv->cdb;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.xfrlen = usbmsc_getbe16(write10->xfrlen);
@ -1066,6 +1078,8 @@ static inline int usbmsc_cmdwrite10(FAR struct usbmsc_dev_s *priv)
USBMSC_FLAGS_DIRHOST2DEVICE | USBMSC_FLAGS_BLOCKXFR);
if (ret == OK)
{
lun = priv->lun;
/* Get the Logical Block Address (LBA) from cdb[] as the starting sector */
priv->sector = usbmsc_getbe32(write10->lba);
@ -1129,7 +1143,7 @@ static inline int usbmsc_cmdwrite10(FAR struct usbmsc_dev_s *priv)
static inline int usbmsc_cmdverify10(FAR struct usbmsc_dev_s *priv)
{
FAR struct scsicmd_verify10_s *verf = (FAR struct scsicmd_verify10_s *)priv->cdb;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
uint32_t lba;
uint16_t blocks;
size_t sector;
@ -1141,6 +1155,8 @@ static inline int usbmsc_cmdverify10(FAR struct usbmsc_dev_s *priv)
ret = usbmsc_setupcmd(priv, SCSICMD_VERIFY10_SIZEOF, USBMSC_FLAGS_DIRNONE);
if (ret == OK)
{
lun = priv->lun;
/* Verify the starting and ending LBA */
lba = usbmsc_getbe32(verf->lba);
@ -1317,7 +1333,7 @@ static int inline usbmsc_cmdmodesense10(FAR struct usbmsc_dev_s *priv,
static inline int usbmsc_cmdread12(FAR struct usbmsc_dev_s *priv)
{
struct scsicmd_read12_s *read12 = (struct scsicmd_read12_s *)priv->cdb;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.xfrlen = usbmsc_getbe32(read12->xfrlen);
@ -1325,6 +1341,8 @@ static inline int usbmsc_cmdread12(FAR struct usbmsc_dev_s *priv)
USBMSC_FLAGS_DIRDEVICE2HOST | USBMSC_FLAGS_BLOCKXFR);
if (ret == OK)
{
lun = priv->lun;
/* Get the Logical Block Address (LBA) from cdb[] as the starting sector */
priv->sector = usbmsc_getbe32(read12->lba);
@ -1379,7 +1397,7 @@ static inline int usbmsc_cmdread12(FAR struct usbmsc_dev_s *priv)
static inline int usbmsc_cmdwrite12(FAR struct usbmsc_dev_s *priv)
{
struct scsicmd_write12_s *write12 = (struct scsicmd_write12_s *)priv->cdb;
FAR struct usbmsc_lun_s *lun = priv->lun;
FAR struct usbmsc_lun_s *lun;
int ret;
priv->u.xfrlen = usbmsc_getbe32(write12->xfrlen);
@ -1387,6 +1405,8 @@ static inline int usbmsc_cmdwrite12(FAR struct usbmsc_dev_s *priv)
USBMSC_FLAGS_DIRHOST2DEVICE | USBMSC_FLAGS_BLOCKXFR);
if (ret == OK)
{
lun = priv->lun;
/* Get the Logical Block Address (LBA) from cdb[] as the starting sector */
priv->sector = usbmsc_getbe32(write12->lba);

2
include/nuttx/sched.h
View File

@ -168,7 +168,7 @@
# define CHILD_FLAG_TTYPE_TASK (0 << CHILD_FLAG_TTYPE_SHIFT) /* Normal user task */
# define CHILD_FLAG_TTYPE_PTHREAD (1 << CHILD_FLAG_TTYPE_SHIFT) /* User pthread */
# define CHILD_FLAG_TTYPE_KERNEL (2 << CHILD_FLAG_TTYPE_SHIFT) /* Kernel thread */
#define CHILD_FLAG_EXITED (1 << 0) /* Bit 2: The child thread has exit'ed */
#define CHILD_FLAG_EXITED (1 << 2) /* Bit 2: The child thread has exit'ed */
/* Bits 3-7: Available */
/* Sporadic scheduler flags */

22
net/sixlowpan/README.txt
View File

@ -10,12 +10,14 @@ Optimal 6loWPAN Configuration
128 112 96 80 64 48 32 16
---- ---- ---- ---- ---- ---- ---- ----
xxxx xxxx xxxx xxxx xxxx 00ff fe00 MMMM 2-byte Rime address IEEE 48-bit MAC
fe80 0000 0000 0000 NNNN NNNN NNNN NNNN 8-byte Rime address IEEE EUI-64
AAAA xxxx xxxx xxxx xxxx 00ff fe00 MMMM 2-byte Rime address IEEE 48-bit MAC
AAAA 0000 0000 0000 NNNN NNNN NNNN NNNN 8-byte Rime address IEEE EUI-64
Where MMM is the 2-byte rime address XOR 0x0200. For example, the MAC
Where MMM is the 2-byte rime address XORed 0x0200. For example, the MAC
address of 0xabcd would be 0xa9cd. And NNNN NNNN NNNN NNNN is the 8-byte
rime address address XOR 02000 0000 0000 0000
rime address address XOR 02000 0000 0000 0000.
For link-local address, AAAA is 0xfe80
3. MAC based link-local addresses
@ -33,9 +35,9 @@ Optimal 6loWPAN Configuration
Fragmentation Headers
---------------------
A fragment header is placed at the beginning of the outgoing packet just
after the MAC when the payload is too large to fit in a single IEEE 802.15.4
frame. The fragment header contains three fields: Datagram size, datagram tag
and datagram offset.
after the MAC header when the payload is too large to fit in a single IEEE
802.15.4 frame. The fragment header contains three fields: Datagram size,
datagram tag and datagram offset.
1. Datagram size describes the total (un-fragmented) payload.
2. Datagram tag identifies the set of fragments and is used to match
@ -65,7 +67,7 @@ this is a HC1 compressed first frame of a packet
This is the second frame of the same transfer:
41 88 01 cefa 3412 cdab ### 9-byte MAC header
e50e 000b 0a ### 5 byte FRAGN header
e50e 000b 0d ### 5 byte FRAGN header
42 ### SIXLOWPAN_DISPATCH_HC1
fb ### RIME_HC1_HC_UDP_HC1_ENCODING
e0 ### RIME_HC1_HC_UDP_UDP_ENCODING
@ -81,5 +83,5 @@ This is the second frame of the same transfer:
The payload length is encoded in the LS 11-bits of the first 16-bit value:
In this example the payload size is 0x050e or 1,294. The tag is 0x000b. In
the second frame, the fifth byte contains the offset 0x0a which is 10 << 3 =
80 bytes, the size of the payload on the first packet.
the second frame, the fifth byte contains the offset 0x0d which is 13 << 3 =
104 bytes, the size of the payload on the first packet.