sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/armv7-a & armv7-r:Add invalidate icache behavior

Browse Source 
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
This commit is contained in:
chenrun1 2022-12-23 15:42:36 +08:00 committed by Xiang Xiao
parent 7e4c5d3daa
commit c61195bcc9
6 changed files with 84 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm/src/armv7-a/arm_cache.c
View File

@ -53,7 +53,28 @@
void up_invalidate_icache_all(void)
{
cp15_invalidate_icache();
cp15_invalidate_icache_all();
}
/****************************************************************************
* Name: up_invalidate_icache
*
* Description:
* Validate the specified range instruction cache as PoU,
* and flush the branch target cache
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
****************************************************************************/
void up_invalidate_icache(uintptr_t start, uintptr_t end)
{
cp15_invalidate_icache(start, end);
}
/****************************************************************************

20
arch/arm/src/armv7-a/cp15_cacheops.c
View File

@ -189,10 +189,28 @@ void cp15_dcache_op_level(uint32_t level, int op)
ARM_ISB();
}
void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
{
uint32_t line;
line = cp15_cache_get_info(NULL, NULL);
start &= ~(line - 1);
ARM_DSB();
while (start < end)
{
cp15_invalidate_icache_bymva(start);
start += line;
}
ARM_ISB();
}
void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
{
cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
cp15_invalidate_icache();
cp15_invalidate_icache_all();
}
void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)

2
arch/arm/src/armv7-a/cp15_cacheops.h
View File

@ -681,7 +681,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
*
****************************************************************************/
static inline void cp15_invalidate_icache(void)
static inline void cp15_invalidate_icache_all(void)
{
CP15_SET(ICIALLU, 0);
ARM_ISB();

23
arch/arm/src/armv7-r/arm_cache.c
View File

@ -53,7 +53,28 @@
void up_invalidate_icache_all(void)
{
cp15_invalidate_icache();
cp15_invalidate_icache_all();
}
/****************************************************************************
* Name: up_invalidate_icache
*
* Description:
* Validate the specified range instruction cache as PoU,
* and flush the branch target cache
*
* Input Parameters:
* start - virtual start address of region
* end - virtual end address of region + 1
*
* Returned Value:
* None
*
****************************************************************************/
void up_invalidate_icache(uintptr_t start, uintptr_t end)
{
cp15_invalidate_icache(start, end);
}
/****************************************************************************

20
arch/arm/src/armv7-r/cp15_cacheops.c
View File

@ -189,10 +189,28 @@ void cp15_dcache_op_level(uint32_t level, int op)
ARM_ISB();
}
void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
{
uint32_t line;
line = cp15_cache_get_info(NULL, NULL);
start &= ~(line - 1);
ARM_DSB();
while (start < end)
{
cp15_invalidate_icache_bymva(start);
start += line;
}
ARM_ISB();
}
void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
{
cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
cp15_invalidate_icache();
cp15_invalidate_icache_all();
}
void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)

2
arch/arm/src/armv7-r/cp15_cacheops.h
View File

@ -688,7 +688,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
*
****************************************************************************/
static inline void cp15_invalidate_icache(void)
static inline void cp15_invalidate_icache_all(void)
{
CP15_SET(ICIALLU, 0);
ARM_ISB();