SAMA5 NAND: Basic NAND access now work (software ECC and no DMA)
This commit is contained in:
Gregory Nutt
parent
06dca0d263
commit
c62a9c269a
@ -182,10 +182,9 @@ static void nand_wait_cmddone(struct sam_nandcs_s *priv);
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static void nand_setup_cmddone(struct sam_nandcs_s *priv);
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static void nand_wait_xfrdone(struct sam_nandcs_s *priv);
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static void nand_setup_xfrdone(struct sam_nandcs_s *priv);
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#ifdef USE_RBEDGE
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static void nand_wait_rbedge(struct sam_nandcs_s *priv);
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static void nand_setup_rbedge(struct sam_nandcs_s *priv);
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#else
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#if 0 /* Not used */
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static void nand_wait_nfcbusy(struct sam_nandcs_s *priv);
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#endif
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static uint32_t nand_nfc_poll(void);
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@ -431,12 +430,18 @@ static int nand_operation_complete(struct sam_nandcs_s *priv)
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nand_nfc_cleale(priv, 0, COMMAND_STATUS, 0, 0, 0);
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status = READ_DATA8(&priv->raw);
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if (((status & STATUS_READY) == 0) || ((status & STATUS_ERROR) != 0))
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/* On successful completion, the NAND will be READY with no ERROR conditions */
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if ((status & STATUS_ERROR) != 0)
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{
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return false;
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return -EIO;
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}
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else if ((status & STATUS_READY) == 0)
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{
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return -EBUSY;
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}
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return true;
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return OK;
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}
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/****************************************************************************
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@ -856,7 +861,6 @@ static void nand_setup_xfrdone(struct sam_nandcs_s *priv)
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*
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****************************************************************************/
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#ifdef USE_RBEDGE
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static void nand_wait_rbedge(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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@ -891,7 +895,6 @@ static void nand_wait_rbedge(struct sam_nandcs_s *priv)
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while (!g_nand.rbedge);
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#endif
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}
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#endif
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/****************************************************************************
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* Name: nand_setup_rbedge
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@ -907,7 +910,6 @@ static void nand_wait_rbedge(struct sam_nandcs_s *priv)
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*
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****************************************************************************/
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#ifdef USE_RBEDGE
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static void nand_setup_rbedge(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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@ -935,7 +937,6 @@ static void nand_setup_rbedge(struct sam_nandcs_s *priv)
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g_nand.rbedge = false;
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#endif
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}
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#endif
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/****************************************************************************
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* Name: nand_wait_nfcbusy
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@ -951,7 +952,7 @@ static void nand_setup_rbedge(struct sam_nandcs_s *priv)
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*
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****************************************************************************/
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#ifndef USE_RBEDGE
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#if 0 /* Not used */
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static void nand_wait_nfcbusy(struct sam_nandcs_s *priv)
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{
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uint32_t sr;
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@ -1000,7 +1001,7 @@ static uint32_t nand_nfc_poll(void)
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sr = nand_getreg(SAM_HSMC_SR);
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#ifndef CONFIG_SAMA5_NAND_REGDEBUG
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fllvdbg("sr=%08x\n", sr);
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// fllvdbg("sr=%08x\n", sr);
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#endif
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/* When set to one, this XFRDONE indicates that the NFC has terminated
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@ -1025,20 +1026,18 @@ static uint32_t nand_nfc_poll(void)
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g_nand.cmddone = true;
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}
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#ifdef USE_RBEDGE
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/* If set to one, the RBEDGE0 flag indicates that an edge has been detected
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* on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the
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* SMC_CFG register, only rising or falling edge is detected. This flag is
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* reset after the status read.
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*/
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if ((pending & HSMC_NFCINT_RBEDGE0) != 0)
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if ((sr & HSMC_NFCINT_RBEDGE0) != 0)
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{
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/* Set the latching RBEDGE0 status */
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g_nand.rbedge = true;
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}
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#endif
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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irqrestore(flags);
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@ -1101,7 +1100,6 @@ static int hsmc_interrupt(int irq, void *context)
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nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_CMDDONE);
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}
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#ifdef USE_RBEDGE
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/* If set to one, the RBEDGE0 flag indicates that an edge has been detected
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* on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the
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* SMC_CFG register, only rising or falling edge is detected. This flag is
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@ -1118,7 +1116,6 @@ static int hsmc_interrupt(int irq, void *context)
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nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_RBEDGE0);
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}
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#endif
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return OK;
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}
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@ -2150,14 +2147,12 @@ static int nand_writepage_noecc(struct sam_nandcs_s *priv, off_t block,
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COMMAND_WRITE_1, 0, 0, rowaddr);
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nand_wait_xfrdone(priv);
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#ifdef USE_RBEDGE
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nand_setup_rbedge(priv);
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nand_nfc_cleale(priv, HSMC_CLE_WRITE_EN, COMMAND_WRITE_2, 0, 0, 0);
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nand_wait_rbedge(priv);
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#else
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nand_nfc_cleale(priv, HSMC_CLE_WRITE_EN, COMMAND_WRITE_2, 0, 0, 0);
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nand_wait_nfcbusy(priv);
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#endif
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/* Check if the transfer completed successfully */
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ret = nand_operation_complete(priv);
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if (ret < 0)
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{
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@ -2874,7 +2869,15 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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}
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/* Initialize the NAND hardware for this CS */
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/* Perform board-specific SMC intialization for this CS */
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/* Perform board-specific SMC intialization for this CS. This should include:
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*
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* 1. Enable clocking to the HSMC
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* 2. Configuration timing for the HSMC CS
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* 3. Configuration of PIO pins
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*
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* Other than enabling the HSMC, these are all things that the board-cognizant
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* logic is best prepared to handle.
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*/
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ret = board_nandflash_config(cs);
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if (ret < 0)
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@ -252,13 +252,6 @@
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#undef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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/* In the write sequence, there is a step where we should wait on an R/B
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* edge transition. The step currently hangs but, presumably must be
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* restored when NAND is working.
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*/
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#undef USE_RBEDGE
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -266,6 +259,9 @@
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* select. The struct nand_raw_s must appear at the beginning of the
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* definition so that you can freely cast between pointers to struct
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* nand_raw_s and struct sam_nandcs_s.
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*
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* NOTE: Currently, only SAMA5D3x CS3 can support NAND. The logic here would
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* support NAND on any CS, but that capability is not needed.
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*/
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struct sam_nandcs_s
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@ -303,17 +299,14 @@ struct sam_nand_s
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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volatile bool cmddone; /* True: NFC command has completed (latching) */
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volatile bool xfrdone; /* True: Transfer has completed (latching) */
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#ifdef USE_RBEDGE
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volatile bool rbedge; /* True: Ready/busy edge detected (latching) */
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#endif
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sem_t waitsem; /* Used to wait for one of the above states */
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#else
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bool cmddone; /* True: NFC command has completed (latching) */
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bool xfrdone; /* True: Transfer has completed (latching) */
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#ifdef USE_RBEDGE
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bool rbedge; /* True: Ready/busy edge detected (latching) */
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#endif
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#endif
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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